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51. 发明授权

US09455220B2 Apparatus and method for placing stressors on interconnects within an integrated circuit device to manage electromigration failures 有权
标题翻译：将应激物放置在集成电路器件内的互连件上以管理电迁移故障的装置和方法
公开(公告)号：US09455220B2
公开(公告)日：2016-09-27
申请号：US14292886
申请日：2014-05-31
申请人： Mehul D. Shroff , Douglas M Reber , Edward O. Travis
发明人： Mehul D. Shroff , Douglas M Reber , Edward O. Travis
IPC分类号： H01L21/4763 , H01L23/522 , G06F17/50 , H01L21/768 , H01L23/532
CPC分类号： H01L23/5283 , G06F17/5077 , H01L21/76834 , H01L21/76838 , H01L21/76849 , H01L21/76852 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method for selecting locations within an integrated circuit device for placing stressors to manage electromigration failures includes calculating an electric current for an interconnect within the integrated circuit device and determining an electromigration stress profile for the interconnect based on the electric current. The method further includes determining an area on the interconnect for placing a stressor to alter the electromigration stress profile for the interconnect.
摘要翻译：用于选择集成电路装置中用于放置应力源以管理电迁移故障的位置的方法包括计算集成电路装置内的互连的电流，并基于电流确定互连的电迁移应力分布。该方法还包括确定互连上的区域以放置应力源以改变互连的电迁移应力分布。

52. 发明授权

US09455216B2 Semiconductor device package and method of manufacture 有权
标题翻译：半导体器件封装及其制造方法
公开(公告)号：US09455216B2
公开(公告)日：2016-09-27
申请号：US14696917
申请日：2015-04-27
申请人： Freescale Semiconductor, Inc.
发明人： Dwight L. Daniels , Stephen R. Hooper , Alan J. Magnus , Justin E. Poarch
IPC分类号： H01L23/495 , H01L23/00 , H01L21/48 , H01L23/31
CPC分类号： H01L23/49537 , H01L21/4842 , H01L23/3107 , H01L23/3114 , H01L23/49541 , H01L23/49548 , H01L23/49558 , H01L23/49586 , H01L24/97 , H01L2924/181 , Y10T29/49121 , H01L2924/00
摘要： A structure to improve saw singulation quality and wettability of integrated circuit packages (140) is assembled with lead frames (112) having half-etched recesses (134) in leads. In one embodiment, the structure is a lead frame strip (110) having a plurality of lead frames. Each of the lead frames includes a depression (130) that is at least partially filled with a material (400) prior to singulating the lead frame strip. In another embodiment, the structure is a semiconductor device package (140) that includes a semiconductor device encapsulated in a package body (142) having a plurality of leads (120). Each lead has an exposed portion external to the package. There is recess (134) at a corner of each lead. Each recess has a generally concave configuration. Each recess is filled with a removable material (300).
摘要翻译：用于提高集成电路封装（140）的锯切质量和润湿性的结构与在引线中具有半蚀刻凹槽（134）的引线框架（112）组装在一起。在一个实施例中，该结构是具有多个引线框架的引线框架条（110）。每个引线框架包括在分割引线框架条之前至少部分地填充有材料（400）的凹陷（130）。在另一个实施例中，该结构是半导体器件封装（140），其包括封装在具有多个引线（120）的封装主体（142）中的半导体器件。每个引线在封装外部具有暴露部分。在每个引线的拐角处有凹槽（134）。每个凹部具有大致凹形的构造。每个凹部填充有可移除材料（300）。

53. 发明授权

US09449129B2 Method and apparatus for accelerating sparse matrix operations in full accuracy circuit simulation 有权
标题翻译：用于在全精度电路仿真中加速稀疏矩阵运算的方法和装置
公开(公告)号：US09449129B2
公开(公告)日：2016-09-20
申请号：US13873621
申请日：2013-04-30
申请人： Freescale Semiconductor, Inc.
发明人： Kiran Kumar Gullapalli , Steven D. Hamm
IPC分类号： G06F7/60 , G06F17/50
CPC分类号： G06F17/5036 , G06F17/5022
摘要： A system and method of accelerating sparse matrix operations in full accuracy simulation of a circuit includes determining repetitive blocks of the circuit, determining a set of values of a current block, determining whether the state of the current block is sufficiently close to the state of a stored block solution when the corresponding values are within a predetermined error range, and performing a reduced computation using the stored block solution to provide a solution for the current block when the states are sufficiently close to each other. The reduced computation includes retrieving previously stored solutions and performing substantially simplified matrix and vector operations while maintaining accuracy of the solution. Reduced precision versions of the values may be used to generate a hash index used to store the block solutions. Stored redundant device information may also be used to simplify device solutions in a similar manner.
摘要翻译：在电路的全精度仿真中加速稀疏矩阵运算的系统和方法包括确定电路的重复块，确定当前块的一组值，确定当前块的状态是否足够接近于当前块的状态当相应的值在预定的误差范围内时，使用存储的块解来执行减少的计算，以便当状态彼此充分接近时为当前块提供解决方案。减少的计算包括检索先前存储的解决方案并执行基本上简化的矩阵和向量操作，同时保持解决方案的准确性。可以使用精简版本的精简版本来生成用于存储块解决方案的散列索引。存储的冗余设备信息也可以用于以类似的方式简化设备解决方案。

54. 发明授权

US09448283B2 Circuit arrangement for logic built-in self-test of a semiconductor device and a method of operating such circuit arrangement 有权
标题翻译：用于半导体器件的逻辑内置自检的电路布置和操作这种电路布置的方法
公开(公告)号：US09448283B2
公开(公告)日：2016-09-20
申请号：US14421889
申请日：2012-08-22
申请人： Heiko Ahrens , Claudia Latzel , Bernhard Richter
发明人： Heiko Ahrens , Claudia Latzel , Bernhard Richter
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/3185 , G01R31/3187
CPC分类号： G01R31/3177 , G01R31/318547 , G01R31/318575 , G01R31/3187
摘要： A circuit arrangement for Logic Built-In Self-Test (LBIST) includes a clock source configured to generate a system clock, a first clock division circuitry configured to derive a first punched-out clock and a plurality of scan chains operable at the first punched-out clock. Each scan chain has an associated output circuitry responsive to a leading edge of the first punched-out clock. The circuit arrangement includes a second clock division circuitry configured to derive a second punched-out clock. The second punched-out clock has a delay of one or more system clock periods relative to the first punched-out clock. A compacting logic is configured to compact signals received from the scan chains. A sequential retiming element connects the compacting logic to an input circuitry of a MISR. The sequential retiming element is responsive to a trailing edge of the second punched-out clock. The input circuitry is responsive to a leading edge of the second punched-out clock.
摘要翻译：用于逻辑内置自检（LBIST）的电路装置包括被配置为产生系统时钟的时钟源，被配置为导出第一冲出时钟的第一时钟分频电路和可在第一冲压时操作的多个扫描链 - 时钟。每个扫描链具有响应于第一冲出时钟的前沿的相关联的输出电路。电路装置包括被配置为导出第二冲出时钟的第二时钟分频电路。第二冲出时钟相对于第一冲出时钟具有一个或多个系统时钟周期的延迟。压缩逻辑被配置为压缩从扫描链接收的信号。连续重新定时元件将压实逻辑连接到MISR的输入电路。顺序重新定时元件响应于第二冲出时钟的后沿。输入电路响应于第二冲出时钟的前沿。

55. 发明申请

US20160266180A1 LOW JITTER PULSE OUTPUT FOR POWER METER 审中-公开
标题翻译：低功率脉冲串脉冲输出
公开(公告)号：US20160266180A1
公开(公告)日：2016-09-15
申请号：US15025042
申请日：2013-09-27
申请人： Martin MIENKINA , Radomir KOZUB , Ludek SLOSARCIK , Lukas VACULIK
发明人： MARTIN MIENKINA , RADOMIR KOZUB , LUDEK SLOSARCIK , LUKAS VACULIK
IPC分类号： G01R21/127 , G01R21/133
CPC分类号： G01R21/127 , G01R21/133 , G01R22/06 , G01R35/04 , G06F1/26
摘要： There is provided an energy consumption meter device (1) comprising the processor (8) arranged to receive input data from the sampling unit. The processor calculates at a calculation step [n] an energy contribution value using ΔE using a sampled voltage value and a sampled current value. The processor will calculate an energy value E[n] using a reminder value which was calculated at a previous calculation step [n−1]. The processor will then calculate a relative delay Td′ using the threshold value, the reminder value and the energy value, and generate an output pulse at an output time tpulse which is delayed for the relative delay Td′ with respect to the calculation time step[n]. By delaying the output pulse with a value which is a closest proximity of Td, the cycle-by-cycle jitter is less or equal to the clock frequency of the timer tclk.
摘要翻译：提供了一种能量消耗计装置（1），包括处理器（8），其被布置成从采样单元接收输入数据。处理器使用采样电压值和采样电流值，使用ΔE在计算步骤[n]计算能量贡献值。处理器将使用在先前的计算步骤[n-1]计算的提醒值来计算能量值E [n]。然后，处理器将使用阈值，提醒值和能量值来计算相对延迟Td'，并且在相对于计算时间步长相对于延迟Td'延迟的输出时间tpulse处产生输出脉冲[ n]。通过以与Td最接近的值延迟输出脉冲，逐周期抖动小于或等于定时器tclk的时钟频率。

56. 发明授权

US09445050B2 Teleconferencing environment having auditory and visual cues 有权
标题翻译：具有听觉和视觉线索的电话会议环境
公开(公告)号：US09445050B2
公开(公告)日：2016-09-13
申请号：US14543031
申请日：2014-11-17
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Edward O. Travis , Douglas M. Reber
IPC分类号： H04N7/14 , H04N7/15 , H04L29/06 , G10L17/00
CPC分类号： H04N7/15 , G10L17/005 , H04L65/403 , H04N7/147
摘要： A teleconferencing environment is provided in which both audio and visual cues are used to identify active participants and presenters. Embodiments provide an artificial environment, configurable by each participant in a teleconference, that directs the attention of a user to an identifier of an active participant or presenter. This direction is provided, in part, by stereo-enhanced audio that is associated with a position of a visual identifier of an active participant or presenter that has been placed on a window of a computer screen. The direction is also provided, in part, by promotion and demotion of attendees between attendee, active participant, and current presenter and automatic placement of an image related to an attendee on the screen in response to such promotion and demotion.
摘要翻译：提供电话会议环境，其中使用音频和视觉线索来识别活动参与者和演示者。实施例提供了可由电话会议中的每个参与者配置的人造环境，其将用户的注意力引导到主动参与者或演示者的标识符。该方向部分地由与被放置在计算机屏幕的窗口上的主动参与者或演示者的视觉标识符的位置相关联的立体声增强音频提供。方向也部分通过参加者，积极参与者和现任主持人的参与者的升级和降级，以及响应于这种升级和降级在屏幕上自动放置与参加者相关的图像。

57. 发明授权

US09443782B1 Method of bond pad protection during wafer processing 有权
标题翻译：晶圆加工过程中焊盘保护的方法
公开(公告)号：US09443782B1
公开(公告)日：2016-09-13
申请号：US14823069
申请日：2015-08-11
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Robert F. Steimle , Dwight L. Daniels , Veera M. Gunturu
IPC分类号： H01L21/00 , H01L23/31 , H01L21/02 , H01L21/82 , H01L21/56 , H01L23/00
CPC分类号： H01L23/3157 , H01L21/02013 , H01L21/50 , H01L21/561 , H01L21/6835 , H01L21/78 , H01L21/82 , H01L23/04 , H01L23/10 , H01L23/564 , H01L2221/68377
摘要： A method for protecting terminal elements on a wafer during wafer level fabrication processes entails applying a protective coating to the terminal elements prior to further processing operations. These processing operations may include back side grinding of the wafer and/or saw-to-reveal operations to expose the terminal elements from a cap wafer of a wafer structure. The protective coating can protect the terminal elements from potentially damaging contaminants, such as debris from the grinding or saw-to-reveal operations. Furthermore, the protective coating can protect the bond pads from coming into contact with a rapidly oxidizing environment when exposed to water. The protective coating may be a hot-water soluble thermoplastic material the melts from a solid form to a liquid form at a relatively low temperature to enable application of the protective coating in liquid form onto the terminal elements and clean removal of the protective coating from the terminal elements.
摘要翻译：在晶片级制造过程中保护晶片上的端子元件的方法需要在进一步处理操作之前对端子元件施加保护涂层。这些处理操作可以包括晶片的背面研磨和/或锯到显示操作，以从晶片结构的盖晶片露出端子元件。保护涂层可以保护端子元件免受潜在的破坏性污染物，例如磨削或锯切操作中的碎屑。此外，当暴露于水时，保护涂层可以保护接合垫不与快速氧化环境接触。保护性涂层可以是热水可溶的热塑性材料，其在相对较低的温度下从固体形式熔化成液体形式，以使得能够将液体形式的保护涂层施加到端子元件上，并将保护涂层从终端元素。

58. 发明授权

US09443041B2 Simulation system and method for testing a simulation of a device against one or more violation rules 有权
标题翻译：用于根据一个或多个违规规则测试设备的仿真的仿真系统和方法
公开(公告)号：US09443041B2
公开(公告)日：2016-09-13
申请号：US14398885
申请日：2012-09-13
申请人： Mehul Shroff , Peter Abramowitz , Xavier Hours
发明人： Mehul Shroff , Peter Abramowitz , Xavier Hours
IPC分类号： G06F17/50 , G06F11/26
CPC分类号： G06F17/5009 , G06F11/261 , G06F17/5022 , G06F17/5045 , G06F17/5081
摘要： A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of the device using a device design, a device model and a simulation scenario; and one or more violation monitor for each violation rule. At least one of the violation monitors comprises a violation information detector and a threshold controller. The violation information detector is arranged to detect one or more violations of the respective violation rule of the one or more violation rules during the executing the simulation of the device and, for each violation, determine information representing the respective violation, wherein the detecting the one or more violations comprises comparing a simulated parameter against a threshold. The threshold controller is arranged to determine the threshold for the respective violation rule of the one or more violation rules in dependence on a temporal characteristic of a violation associated with the respective violation rule. A method of testing a simulation of a device against one or more violation rules is also described.
摘要翻译：描述了用于针对一个或多个违规规则来测试设备的模拟的仿真系统。该仿真系统包括：使用设备设计，设备模型和仿真场景执行设备仿真的设备模拟器; 以及每个违规规则的一个或多个违规监视器。至少一个违规监视器包括违规信息检测器和阈值控制器。违规信息检测器被布置为在执行设备的仿真期间检测对一个或多个违规规则的相应违规规则的一个或多个违反，并且对于每个违规，确定表示相应违反的信息，其中检测一个或更多违法行为包括将模拟参数与阈值进行比较。阈值控制器被设置为根据与相应违反规则相关联的违规的时间特征来确定一个或多个违规规则的相应违规规则的阈值。还描述了针对一个或多个违规规则测试设备的模拟的方法。

59. 发明授权

US09438191B2 Radio frequency power amplifier circuit 有权
标题翻译：射频功率放大电路
公开(公告)号：US09438191B2
公开(公告)日：2016-09-06
申请号：US14514556
申请日：2014-10-15
申请人： Igor Ivanovich Blednov
发明人： Igor Ivanovich Blednov
IPC分类号： H01B1/04 , H03F3/68 , H03F3/60 , H03F1/02 , H03F3/19 , H03F3/21 , H04B1/04 , H03F3/195 , H03F3/24 , H04W88/08
CPC分类号： H03F3/602 , H01L2224/49111 , H01L2224/49175 , H03F1/02 , H03F1/0288 , H03F3/19 , H03F3/195 , H03F3/211 , H03F3/24 , H03F3/245 , H03F2200/213 , H03F2200/408 , H03F2200/451 , H03F2203/21106 , H04B1/04 , H04B1/0483 , H04B2001/0425 , H04B2001/045 , H04W88/08
摘要： An RF power amplifier circuit has an input terminal for receiving an input signal having an input power, and an output terminal for outputting an output signal. The RF power amplifier circuit comprises three amplifier stages and an input power splitter for providing respective power fraction signals to respective inputs of each amplifier stage. The input power splitter comprises a first input transmission line arranged between a first node and a second node, a second input transmission line arranged between a third node and a fourth node, and an electrical reactive element having a first terminal electrically connected to both the first and the second nodes, and a second terminal electrically coupled to a third one of the respective three inputs.
摘要翻译： RF功率放大器电路具有用于接收具有输入功率的输入信号的输入端子和用于输出输出信号的输出端子。 RF功率放大器电路包括三个放大器级和输入功率分配器，用于将各个功率分数信号提供给每个放大器级的相应输入。输入功率分配器包括布置在第一节点和第二节点之间的第一输入传输线，布置在第三节点和第四节点之间的第二输入传输线，以及电反应元件，其具有电连接到第一节点和第二节点的第一节点和第二节点，以及电耦合到相应的三个输入中的第三个的第二终端。

60. 发明授权

US09438184B2 Integrated passive device assemblies for RF amplifiers, and methods of manufacture thereof 有权
标题翻译：用于RF放大器的集成无源器件组件及其制造方法
公开(公告)号：US09438184B2
公开(公告)日：2016-09-06
申请号：US14317572
申请日：2014-06-27
申请人： Jeffrey K. Jones , Basim H. Noori , Michael E. Watts
发明人： Jeffrey K. Jones , Basim H. Noori , Michael E. Watts
IPC分类号： H01L21/8242 , H01L29/86 , H01L29/06 , H03F3/21 , H01L25/00 , H01L25/16 , H01L23/00 , H03F1/56 , H01L23/047 , H03F3/195 , H03F3/193
CPC分类号： H03F3/21 , H01G4/385 , H01G4/40 , H01L23/047 , H01L23/481 , H01L23/488 , H01L23/66 , H01L24/48 , H01L24/49 , H01L24/85 , H01L25/165 , H01L25/50 , H01L2223/6611 , H01L2223/6655 , H01L2223/6672 , H01L2224/48091 , H01L2224/48111 , H01L2224/49052 , H01L2224/49175 , H01L2224/49433 , H01L2924/00014 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/1304 , H01L2924/13091 , H01L2924/19104 , H03F1/565 , H03F3/193 , H03F3/195 , H03F2200/222 , H03F2200/387 , H03F2200/451 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/05599
摘要： An embodiment of an integrated passive device (IPD) assembly includes a first capacitor formed over a semiconductor substrate, where the first capacitor includes a first capacitor electrode, a second capacitor electrode, and dielectric material that electrically insulates the first capacitor electrode from the second capacitor electrode. The IPD assembly also includes a first contact pad exposed at a top surface of the IPD assembly and electrically coupled to the second capacitor electrode, and a second contact pad exposed at the top surface of the IPD. A second capacitor is coupled to the top surface of the IPD, and includes a first terminal electrically coupled to the first contact pad, and a second terminal electrically coupled to the second contact pad. The IPD assembly may be included in a packaged RF device, forming portions of an output impedance matching circuit and an envelope frequency termination circuit.
摘要翻译：集成无源器件（IPD）组件的实施例包括形成在半导体衬底上的第一电容器，其中第一电容器包括第一电容器电极，第二电容器电极和将第一电容器电极与第二电容器电绝缘的电介质材料电极。 IPD组件还包括暴露在IPD组件的顶表面处并电耦合到第二电容器电极的第一接触焊盘和暴露在IPD的顶表面处的第二接触焊盘。第二电容器耦合到IPD的顶表面，并且包括电耦合到第一接触焊盘的第一端子和电耦合到第二接触焊盘的第二端子。 IPD组件可以包括在封装的RF器件中，形成输出阻抗匹配电路的一部分和封装频率终止电路。

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