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1. 发明授权

US09685405B2 Fuse/resistor utilizing interconnect and vias and method of making 有权
公开(公告)号：US09685405B2
公开(公告)日：2017-06-20
申请号：US13907497
申请日：2013-05-31
申请人： Mehul D. Shroff , Douglas M. Reber , Edward O. Travis
发明人： Mehul D. Shroff , Douglas M. Reber , Edward O. Travis
IPC分类号： H01L23/525 , H01L23/522 , H01L49/02
CPC分类号： H01L23/5256 , H01L23/5228 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure comprising a fuse/resistor structure over a functional layer having a substrate. The fuse/resistor structure includes a via, a first interconnect layer, and a second interconnect layer. The via is over the functional layer and has a first end and a second end vertically opposite the first end, wherein the first end is bounded by a first edge and a second edge opposite the first edge and the second end is bounded by a third edge and a fourth edge opposite the third edge. The first interconnect layer includes a first metal layer running horizontally and contacting the first end and completely extending from the first edge to the second edge. The second interconnect layer includes a second metal layer running horizontally and contacting the second end of the via and extending past the third edge but reaching less than half way to the fourth edge.

2. 发明申请

US20150348898A1 APPARATUS AND METHOD FOR PLACING STRESSORS WITHIN AN INTEGRATED CIRCUIT DEVICE TO MANAGE ELECTROMIGRATION FAILURES 有权
标题翻译：用于在集成电路设备中放置压电器以管理电气故障的装置和方法
公开(公告)号：US20150348898A1
公开(公告)日：2015-12-03
申请号：US14292886
申请日：2014-05-31
申请人： Mehul D. Shroff , Douglas M. Reber , Edward O. Travis
发明人： Mehul D. Shroff , Douglas M. Reber , Edward O. Travis
IPC分类号： H01L23/528 , H01L21/768 , H01L23/522 , G06F17/50
CPC分类号： H01L23/5283 , G06F17/5077 , H01L21/76834 , H01L21/76838 , H01L21/76849 , H01L21/76852 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method for selecting locations within an integrated circuit device for placing stressors to manage electromigration failures includes calculating an electric current for an interconnect within the integrated circuit device and determining an electromigration stress profile for the interconnect based on the electric current. The method further includes determining an area on the interconnect for placing a stressor to alter the electromigration stress profile for the interconnect.
摘要翻译：用于选择集成电路装置中用于放置应力源以管理电迁移故障的位置的方法包括计算集成电路装置内的互连的电流，并基于电流确定互连的电迁移应力分布。该方法还包括确定互连上的区域以放置应力源以改变互连的电迁移应力分布。

3. 发明申请

US20150279854A1 METHOD FOR FORMING A SPLIT-GATE DEVICE 有权
标题翻译：形成分闸装置的方法
公开(公告)号：US20150279854A1
公开(公告)日：2015-10-01
申请号：US14228678
申请日：2014-03-28
申请人： MARK D. HALL , Mehul D. Shroff
发明人： MARK D. HALL , Mehul D. Shroff
IPC分类号： H01L27/115 , H01L21/306 , H01L21/321 , H01L21/3105 , H01L29/423 , H01L29/49 , H01L29/51 , H01L21/311 , H01L21/28 , H01L29/66
CPC分类号： H01L27/11568 , H01L21/31051 , H01L27/11534 , H01L27/11573 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/4916 , H01L29/511 , H01L29/66545 , H01L29/66825 , H01L29/66833 , H01L29/7881
摘要： Forming a semiconductor device in an NVM region and in a logic region using a semiconductor substrate includes forming a dielectric layer and forming a first gate material layer over the dielectric layer. In the logic region, a high-k dielectric and a barrier layer are formed. A second gate material layer is formed over the barrier and the first material layer. Patterning results in gate-region fill material over the NVM region and a logic stack comprising a portion of the second gate material layer and a portion of the barrier layer in the logic region. An opening in the gate-region fill material leaves a select gate formed from a portion of the gate-region fill material adjacent to the opening. A control gate is formed in the opening over a charge storage layer. The portion of the second gate material layer is replaced with a metallic logic gate.
摘要翻译：在NVM区域和使用半导体衬底的逻辑区域中形成半导体器件包括形成电介质层并在电介质层上形成第一栅极材料层。在逻辑区域中，形成高k电介质和阻挡层。在阻挡层和第一材料层之上形成第二栅极材料层。图案化导致NVM区域上的栅极区域填充材料和包括第二栅极材料层的一部分和逻辑区域中的势垒层的一部分的逻辑堆叠。栅极填充材料中的开口离开由与开口相邻的栅极 - 区域填充材料的一部分形成的选择栅极。在电荷存储层上的开口中形成控制栅极。第二栅极材料层的部分被金属逻辑门替代。

4. 发明申请

US20150234961A1 METHOD AND APPARATUS FOR CIRCUIT RELIABILITY AGING 审中-公开
标题翻译：电路可靠性老化的方法与装置
公开(公告)号：US20150234961A1
公开(公告)日：2015-08-20
申请号：US14558694
申请日：2014-12-02
申请人： Zhichen Zhang , Xavier Hours , Mehul D. Shroff , Chuanzheng Wang , Qilin Zhang
发明人： Zhichen Zhang , Xavier Hours , Mehul D. Shroff , Chuanzheng Wang , Qilin Zhang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/76
摘要： A method for integrated circuit reliability aging simulation includes dividing a target time period into N stages including a first stage and a second stage; obtaining first parameter values of a reliability model for the first stage; performing a first simulation on the circuit based on the reliability model and the first parameter values to obtain first aging results; obtaining second parameter values of the reliability model for the second stage; and performing a second simulation on the circuit based on the reliability model and the second parameter values to obtain second aging results.
摘要翻译：一种用于集成电路可靠性老化模拟的方法，包括将目标时间段划分为包括第一阶段和第二阶段的N个阶段; 获得第一阶段的可靠性模型的第一参数值; 基于可靠性模型和第一参数值在电路上执行第一模拟以获得第一老化结果; 获得第二阶段的可靠性模型的第二参数值; 以及基于所述可靠性模型和所述第二参数值在所述电路上执行第二仿真以获得第二老化结果。

5. 发明授权

US08951892B2 Applications for nanopillar structures 有权
标题翻译：纳米柱结构的应用
公开(公告)号：US08951892B2
公开(公告)日：2015-02-10
申请号：US13539070
申请日：2012-06-29
申请人： Mark D. Hall , Mehul D. Shroff
发明人： Mark D. Hall , Mehul D. Shroff
IPC分类号： H01L21/02 , H01L29/66 , B82Y40/00
CPC分类号： H01L29/0676 , B60C23/00 , B81B1/00 , B81B2203/0361 , B82Y20/00 , B82Y30/00 , B82Y40/00 , G01L9/06 , G01N33/0031 , G02B6/107 , G02B6/126 , G02B2006/12097 , H01L21/3086 , H01L29/0665 , H01L29/66 , H01L33/18 , H01L41/1132 , H01L43/02
摘要： A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. A second nanocluster layer is formed on the substrate. A second region of the hard mask overlying a second region of the substrate is etched to create a second pattern in the hard mask. The substrate is then etched through the hard mask to form a first set of nanopillars in the first region of the substrate and a second set of nanopillars in the second region of the substrate. By varying the nanocluster deposition steps between the first and second layers of nanoclusters, the first and second sets of nanopillars will exhibit different characteristics.
摘要翻译：公开的制造混合纳米柱装置的方法包括在基底上形成掩模和硬掩模上的纳米团簇层。然后蚀刻硬掩模以将由第一层纳米团簇形成的图案转移到硬掩模的第一区域中。在基板上形成第二纳米团簇层。蚀刻覆盖衬底的第二区域的硬掩模的第二区域，以在硬掩模中产生第二图案。然后将衬底通过硬掩模蚀刻以在衬底的第一区域中形成第一组纳米柱，并在衬底的第二区域中形成第二组纳米柱。通过改变第一和第二层纳米团簇之间的纳米团簇沉积步骤，第一组和第二组纳米颗粒将呈现不同的特征。

6. 发明申请

US20150002211A1 METHOD AND SYSTEM FOR RECOVERING FROM TRANSISTOR AGING USING HEATING 有权
标题翻译：使用加热从晶体管老化恢复的方法和系统
公开(公告)号：US20150002211A1
公开(公告)日：2015-01-01
申请号：US13929013
申请日：2013-06-27
申请人： Bradley P. Smith , Mehul D. Shroff
发明人： Bradley P. Smith , Mehul D. Shroff
IPC分类号： H01L29/43 , G05F1/10
CPC分类号： H01L21/28176
摘要： A mechanism is provided for extending useable lifetimes of semiconductor devices that are subject to trapped charge carriers in a gate dielectric. Embodiments of the present invention provide heat to the gate dielectric region from one or more sources, where the heat sources are included in a package along with the semiconductor device. It has been determined that heat, when applied during a period when the channel region of a transistor is in accumulation mode or is not providing a current across the channel, can at least partially recover the device from trapped charge carrier effects. Embodiments of the present invention supply heat to the affected gate dielectric region using mechanisms available where the semiconductor device is used (e.g., in the field).
摘要翻译：提供了一种用于延长在栅极电介质中经受捕获的载流子的半导体器件的可用寿命的机制。本发明的实施例从一个或多个源向栅介质区提供热量，其中热源与半导体器件一起包括在封装中。已经确定，当在晶体管的沟道区域处于积聚模式或不通过沟道提供电流的时段期间施加的热量可以至少部分地将器件从俘获的电荷载体效应中恢复。本发明的实施例使用可用于使用半导体器件的机构（例如，在现场）向受影响的栅极电介质区域供热。

7. 发明授权

US08906764B2 Non-volatile memory (NVM) and logic integration 有权
标题翻译：非易失性存储器（NVM）和逻辑集成
公开(公告)号：US08906764B2
公开(公告)日：2014-12-09
申请号：US13441426
申请日：2012-04-06
申请人： Mehul D. Shroff , Mark D. Hall
发明人： Mehul D. Shroff , Mark D. Hall
IPC分类号： H01L21/8247
CPC分类号： H01L21/28273 , H01L27/11534 , H01L29/42328 , H01L29/42332 , H01L29/66545 , H01L29/66825 , H01L29/7881
摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over an NVM work function setting metal, the NVM work function setting metal is on a high-k dielectric, and a metal logic gate of a logic transistor is similarly formed over work function setting and high-k dielectric materials. The logic transistor is formed while portions of the metal select gate of the NVM cell are formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate.
摘要翻译：形成NVM单元和逻辑晶体管的方法使用半导体衬底。 NVM单元的金属选择栅极形成在NVM工作功能设定金属上，NVM工作功能设定金属位于高k电介质上，逻辑晶体管的金属逻辑门类似地形成工作功能设定和高电平 -k电介质材料。在形成NVM单元的金属选择栅极的部分的同时形成逻辑晶体管。在形成NVM单元的同时，保护逻辑晶体管，包括使用纳米晶体形成电荷存储区域，并在金属选择栅极的一部分上形成金属控制栅极以及在基板上的电荷存储区域的一部分。蚀刻电荷存储区域以与金属控制栅极对准。

8. 发明授权

US08713498B2 Method and system for physical verification using network segment current 有权
标题翻译：使用网段电流进行身份验证的方法和系统
公开(公告)号：US08713498B2
公开(公告)日：2014-04-29
申请号：US13216769
申请日：2011-08-24
申请人： Mehul D. Shroff , Ertugrul Demircan
发明人： Mehul D. Shroff , Ertugrul Demircan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A data processing system determines current information corresponding to a node included at a device design. Physical layout information corresponding to the node is received, the physical layout information including one or more layout geometries, the one or more layout geometries providing a circuit network. The circuit network may be partitioned into two or more network segments. A current conducted at a network segment is identified based on the current information. Information representative of dimensions and metal layer of a layout geometry included at the network segment is received. The computer determines that the current exceeds a predetermined maximum threshold, the predetermined maximum threshold determined based on the dimensions and metal layer.
摘要翻译：数据处理系统确定与包括在设备设计中的节点相对应的当前信息。接收对应于节点的物理布局信息，物理布局信息包括一个或多个布局几何形状，一个或多个布局几何形状提供电路网络。电路网络可以被划分成两个或更多个网段。基于当前信息，识别在网段进行的电流。接收代表包括在网段中的布局几何尺寸和金属层的信息。计算机确定电流超过预定的最大阈值，基于尺寸和金属层确定的预定最大阈值。

9. 发明授权

US08709883B2 Implant for performance enhancement of selected transistors in an integrated circuit 有权
标题翻译：用于集成电路中所选晶体管的性能增强的种植体
公开(公告)号：US08709883B2
公开(公告)日：2014-04-29
申请号：US13213992
申请日：2011-08-19
申请人： Mehul D. Shroff , William F. Johnstone , Chad E. Weintraub
发明人： Mehul D. Shroff , William F. Johnstone , Chad E. Weintraub
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L27/088 , H01L21/823412 , H01L21/823493 , H01L27/0207
摘要： A first implant is performed into a substrate to form a well in which a plurality of transistors will be formed. Each transistor of a first subset of the plurality of transistors to be formed has a width that satisfies a predetermined width constraint and each transistor of a second subset has a width that does not satisfy the constraint. A second implant is performed at locations in the well in which transistors of the first subset will be formed and not at locations in the well in which transistors of the second subset will be formed. The transistors are formed, wherein a channel region of each transistor of the first subset is formed in a portion of the substrate which received the second implant and a channel region of each transistor of the second subset is formed in a portion of the substrate which did not receive the second implant.
摘要翻译：将第一种植入物进行衬底以形成其中将形成多个晶体管的阱。要形成的多个晶体管的第一子集的每个晶体管具有满足预定宽度约束的宽度，并且第二子集的每个晶体管具有不满足约束的宽度。第二种注入在阱的位置处进行，其中第一子集的晶体管将被形成，而不在其中将形成第二子集的晶体管的阱中的位置处。形成晶体管，其中第一子集的每个晶体管的沟道区形成在接收第二注入的衬底的一部分中，并且第二子集的每个晶体管的沟道区形成在衬底的一部分中没有接受第二次植入。

10. 发明申请

US20140094029A1 METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN METAL LAYERS 有权
公开(公告)号：US20140094029A1
公开(公告)日：2014-04-03
申请号：US14096051
申请日：2013-12-04
申请人： DOUGLAS M. REBER , Mehul D. Shroff , Edward O. Travis
发明人： DOUGLAS M. REBER , Mehul D. Shroff , Edward O. Travis
IPC分类号： H01L21/768
CPC分类号： H01L21/76877 , G06F17/5077 , H01L21/4763 , H01L21/76816 , H01L23/5226 , H01L29/401 , H01L2924/0002 , H01L2924/00
摘要： A method includes forming a connection between a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A via location for a first via between the first metal layer and the second metal layer is identified. Additional locations for first additional vias are determined. The first additional vias are determined to be necessary for stress migration issues. Additional locations necessary for second additional vias are determined. The second additional vias are determined to be necessary for electromigration issues. The first via and the one of the group consisting of (i) the first additional vias and second additional vias (ii) the first additional vias plus a number of vias sufficient for electromigration issues taking into account that the first additional vias, after taking into account the stress migration issues, still have an effective via number greater than zero.

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