专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US07710193B2 High voltage generator and word line driving high voltage generator of memory device 有权
标题翻译：高压发生器和字线驱动高压发生器的存储器件
公开(公告)号：US07710193B2
公开(公告)日：2010-05-04
申请号：US11528282
申请日：2006-09-28
申请人： Jae-Il Kim , Chang-Ho Do
发明人： Jae-Il Kim , Chang-Ho Do
IPC分类号： G05F3/02
CPC分类号： G11C11/4085 , G11C5/145 , G11C8/08 , G11C11/4074
摘要： A high voltage generator includes: a detection unit for comparing a reference voltage with a high voltage and detecting a voltage level of the high voltage; an oscillator selection unit for generating a first control signal and a second control signal in response to an output signal of the detection unit and a selection signal corresponding to a data operation mode; an oscillator for generating clock signals having different frequencies in response to the first control signal and the second control signal; and a pumping unit for generating the high voltage by performing a charge pumping operation in response to the clock signals.
摘要翻译：高电压发生器包括：用于将参考电压与高电压进行比较并检测高电压电平的检测单元; 振荡器选择单元，用于响应于所述检测单元的输出信号和对应于数据操作模式的选择信号产生第一控制信号和第二控制信号; 用于响应于所述第一控制信号和所述第二控制信号产生具有不同频率的时钟信号的振荡器; 以及用于通过响应于时钟信号执行电荷泵送操作来产生高电压的泵送单元。

52. 发明授权

US07710162B2 Differential amplifier 失效
标题翻译：差分放大器
公开(公告)号：US07710162B2
公开(公告)日：2010-05-04
申请号：US11478091
申请日：2006-06-30
申请人： Sung-Joo Ha
发明人： Sung-Joo Ha
IPC分类号： H03F3/45
CPC分类号： H03F3/45179 , H03F1/34 , H03F2203/45466 , H03F2203/45481
摘要： A differential amplifier includes an amplification unit and a feedback unit. The amplification unit amplifies a voltage difference between a first input signal and a second input signal and outputs a first output signal and a second output signal. The feedback unit amplifies a voltage difference between a first feedback signal based on the first output signal and a second feedback signal based on the second output signal.
摘要翻译：差分放大器包括放大单元和反馈单元。放大单元放大第一输入信号和第二输入信号之间的电压差，并输出第一输出信号和第二输出信号。反馈单元基于第一输出信号放大第一反馈信号和基于第二输出信号的第二反馈信号之间的电压差。

53. 发明授权

US07710143B2 Impedance matching circuit and semiconductor memory device with the same 有权
标题翻译：阻抗匹配电路和半导体存储器件相同
公开(公告)号：US07710143B2
公开(公告)日：2010-05-04
申请号：US11967659
申请日：2007-12-31
申请人： Chun-Seok Jeong , Jae-Jin Lee
发明人： Chun-Seok Jeong , Jae-Jin Lee
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0005 , G11C5/063 , G11C7/1048 , G11C2207/2254
摘要： An impedance matching circuit of a semiconductor memory device performs a ZQ calibration with initial values that reflect an offset error according to variations in a manufacturing process. The impedance matching circuit includes a first pull-down resistance unit, a first pull-up resistance unit, and a code generation unit. The first pull-down resistance unit supplies a ground voltage to a first node, thereby determining an initial pull-down code. The first pull-up resistance unit supplies a supply voltage to the first node, thereby determining an initial pull-up code or a voltage level on the first node. The code generation unit generates pull-down and pull-up calibration codes using the initial pull-down and pull-up codes as respective initial values.
摘要翻译：半导体存储器件的阻抗匹配电路根据制造过程中的变化，以反映偏移误差的初始值来执行ZQ校准。阻抗匹配电路包括第一下拉电阻单元，第一上拉电阻单元和代码生成单元。第一下拉电阻单元向第一节点提供接地电压，从而确定初始下拉代码。第一上拉电阻单元向第一节点提供电源电压，从而确定第一节点上的初始上拉代码或电压电平。代码生成单元使用初始下拉和上拉代码作为相应的初始值生成下拉和上拉校准代码。

54. 发明授权

US07706210B2 Semiconductor memory device including delay locked loop and method for driving the same 有权
标题翻译：包括延迟锁定环的半导体存储器件及其驱动方法
公开(公告)号：US07706210B2
公开(公告)日：2010-04-27
申请号：US11819564
申请日：2007-06-28
申请人： Jee-Yul Kim , Beom-Ju Shin
发明人： Jee-Yul Kim , Beom-Ju Shin
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066
摘要： A semiconductor memory device includes: a delay locked loop (DLL) for delaying an external clock to generate a DLL clock signal; an internal command signal generator for generating an internal command signal in response to an external command; a delay circuit for delaying the internal command signal by a delay time corresponding to a delay time of the DLL to output a delayed internal command signal; and an output enable signal generator for generating an output enable signal based on the delayed internal command signal and the DLL clock signal.
摘要翻译：半导体存储器件包括：延迟锁定环（DLL），用于延迟外部时钟以产生DLL时钟信号; 内部命令信号发生器，用于响应于外部命令产生内部命令信号; 延迟电路，用于将所述内部命令信号延迟与所述DLL的延迟时间对应的延迟时间，以输出延迟的内部命令信号; 以及输出使能信号发生器，用于基于延迟的内部命令信号和DLL时钟信号产生输出使能信号。

55. 发明授权

US07706199B2 Circuit and method for parallel test of memory device 失效
标题翻译：存储器件并行测试电路及方法
公开(公告)号：US07706199B2
公开(公告)日：2010-04-27
申请号：US12000123
申请日：2007-12-10
申请人： Young-Jun Ku , Kee-Teok Park
发明人： Young-Jun Ku , Kee-Teok Park
IPC分类号： G11C29/00
CPC分类号： G11C29/40 , G11C2029/2602
摘要： A test circuit in a memory device includes a first compression unit configured to compress data of a plurality of cells to transmit first compressed data to a plurality of input/output lines, and a second compression unit configured to compress the first compressed data on the plurality of input/output line to output second compressed data to at least one output pin, wherein the second compression unit operates in a low compressing mode and a high compressing mode in response to a data compression selecting signal.
摘要翻译：存储器件中的测试电路包括：第一压缩单元，被配置为压缩多个单元的数据以将第一压缩数据发送到多个输入/输出线;以及第二压缩单元，被配置为压缩多个单元上的第一压缩数据输出/输出线以将第二压缩数据输出到至少一个输出引脚，其中响应于数据压缩选择信号，第二压缩单元以低压缩模式和高压缩模式操作。

56. 发明授权

US07706196B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07706196B2
公开(公告)日：2010-04-27
申请号：US12003680
申请日：2007-12-31
申请人： Kyung-Whan Kim , Ji-Eun Jang
发明人： Kyung-Whan Kim , Ji-Eun Jang
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1045 , G11C11/4076 , G11C11/408 , G11C2207/2254
摘要： A semiconductor memory device is provided to improve the tAA characteristics. The semiconductor memory device includes: a discrimination signal generating unit for generating a first discrimination signal denoting a write operation of the semiconductor memory device; a selective delay unit for delaying a command-group signal in response to a second discrimination signal; and a fuse unit for generating the second discrimination signal based on the first discrimination signal, the second discrimination signal determining whether the selective delay unit selectively delays the command-group signal in response to the first discrimination signal.
摘要翻译：提供半导体存储器件以改善tAA特性。半导体存储器件包括：识别信号产生单元，用于产生表示半导体存储器件的写入操作的第一鉴别信号; 选择延迟单元，用于响应于第二鉴别信号延迟命令组信号; 以及熔丝单元，用于基于所述第一判别信号产生所述第二判别信号，所述第二判别信号确定所述选择延迟单元是否响应于所述第一判别信号有选择地延迟所述命令组信号。

57. 发明授权

US07701796B2 Memory device with self refresh cycle control function 有权
标题翻译：具有自刷新周期控制功能的存储器件
公开(公告)号：US07701796B2
公开(公告)日：2010-04-20
申请号：US12327299
申请日：2008-12-03
申请人： Jee-Yul Kim
发明人： Jee-Yul Kim
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/04 , G11C11/40615 , G11C11/40626 , G11C2211/4061
摘要： Provided is a memory device capable of automatically controlling a self refresh cycle by sensing an ambient temperature, rather than setting Extended Mode Register Set (EMRS) code. The memory device includes a temperature sensing unit for generating a first voltage independent of a temperature variation and a second voltage dependent upon a temperature variation, a comparing unit for comparing the first voltage with the second voltage to provide a comparison result signal, and a self refresh signal generating unit for receiving a self refresh entry signal and generating a self refresh signal of temperature compensated cycle under the control of the comparison result signal.
摘要翻译：提供了能够通过感测环境温度来自动控制自刷新周期的存储器件，而不是设置扩展模式寄存器组（EMRS）代码。存储装置包括用于产生独立于温度变化的第一电压和取决于温度变化的第二电压的温度感测单元，用于将第一电压与第二电压进行比较以提供比较结果信号的比较单元和自身刷新信号产生单元，用于在比较结果信号的控制下接收自刷新输入信号并产生温度补偿周期的自刷新信号。

58. 发明授权

US07701786B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07701786B2
公开(公告)日：2010-04-20
申请号：US11528641
申请日：2006-09-28
申请人： Sang-Hee Lee
发明人： Sang-Hee Lee
IPC分类号： G11C7/00
CPC分类号： G11C5/145 , G11C7/065 , G11C7/08 , G11C11/4091 , G11C2207/065
摘要： A semiconductor memory device changes a pulse width of an over driving signal according to operation modes, which differ by a degree of accessing memory banks during an over driving operation. An over driver supplies an RTO line of the bit line sense amplifier with an over driving voltage in response to the over driving signal and an over driving signal generator changes a pulse width of the over driving signal according to the operation modes. An increase in the VCORE due to excess supply voltage VDD in the over driving operation is prevented.
摘要翻译：半导体存储器件根据操作模式改变过驱动信号的脉冲宽度，该操作模式在过驱动操作期间存取存储体的程度不同。过驱动器响应于过驱动信号而提供具有过驱动电压的位线读出放大器的RTO线，并且过驱动信号发生器根据操作模式改变过驱动信号的脉冲宽度。防止过驱动时电源电压VDD过大导致的VCORE增加。

59. 发明授权

US07697368B2 Semiconductor memory device and method of inputting addresses therein 失效
标题翻译：半导体存储器件及其中输入地址的方法
公开(公告)号：US07697368B2
公开(公告)日：2010-04-13
申请号：US11967577
申请日：2007-12-31
申请人： Khil-Ohk Kang
发明人： Khil-Ohk Kang
IPC分类号： G11C11/00
CPC分类号： G11C29/48 , G11C8/06 , G11C29/1201
摘要： A semiconductor memory device is capable of reducing a test time by sharing input pins of addresses for the test, thereby reducing test costs also. The semiconductor memory device includes first and second address buffer units. The first address buffer unit is configured to transmit a plurality of normal addresses to an internal circuit and store one or more of the received normal addresses. The second address buffer unit is configured to transmit one or more external bank addresses to the internal circuit as internal bank addresses in a normal mode and transmit addresses stored in the first address buffer unit to the internal circuit as the internal bank addresses in a test mode.
摘要翻译：半导体存储器件能够通过共享用于测试的地址的输入引脚来减少测试时间，从而降低测试成本。半导体存储器件包括第一和第二地址缓冲器单元。第一地址缓冲器单元被配置为向内部电路发送多个正常地址，并且存储所接收的正常地址中的一个或多个。第二地址缓冲器单元被配置为将内部电路中的一个或多个外部存储体地址作为正常模式的内部存储体地址发送，并且将内部存储在第一地址缓冲器单元中的地址作为内部存储体以测试模式地址发送到内部电路。

60. 发明授权

US07687389B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07687389B2
公开(公告)日：2010-03-30
申请号：US11448678
申请日：2006-06-08
申请人： Kwan-Yong Lim , Min-Gyu Sung , Heung-Jae Cho , Hong-Seon Yang
发明人： Kwan-Yong Lim , Min-Gyu Sung , Heung-Jae Cho , Hong-Seon Yang
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28247
摘要： A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, forming a first gate conductive layer over the gate insulation layer, forming a barrier metal over the first gate conductive layer, sequentially forming a second gate conductive layer and a gate hard mask over the barrier metal, patterning the gate hard mask, the second gate conductive layer, the barrier metal, the first gate conductive layer, and the gate insulation layer to form a gate pattern, and performing a plasma selective gate re-oxidation process on the gate pattern.
摘要翻译：一种制造半导体器件的方法包括在衬底上形成栅极绝缘层，在栅极绝缘层上形成第一栅极导电层，在第一栅极导电层上形成阻挡金属，依次形成第二栅极导电层和栅极图案化栅极硬掩模，第二栅极导电层，势垒金属，第一栅极导电层和栅极绝缘层以形成栅极图案，并且执行等离子体选择性栅极再氧化工艺在门模式上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式