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1. 发明授权

US08035428B2 Power-up circuit for semiconductor memory device 有权
标题翻译：半导体存储器件的上电电路
公开(公告)号：US08035428B2
公开(公告)日：2011-10-11
申请号：US12495282
申请日：2009-06-30
申请人： Khil-Ohk Kang
发明人： Khil-Ohk Kang
IPC分类号： H03L7/00
CPC分类号： H03K17/20 , G11C5/143
摘要： A power-up circuit for a semiconductor memory device includes a voltage division unit configured to divide a power supply voltage, a first power-up generation unit configured to detect a voltage level of a first divided voltage of the voltage division unit during an initial stage of applying a power supply to generate a first power-up signal and a second power-up generation unit configured to detect a voltage level of a second divided voltage of the voltage division unit, after the first power-up signal is generated from the first power-up generation unit, to generate a second power-up signal.
摘要翻译：半导体存储器件的上电电路包括：分压单元，被配置为分配电源电压;第一上电生成单元，被配置为在初始阶段检测分压单元的第一分压的电压电平施加电源以产生第一上电信号;以及第二上电生成单元，被配置为在从所述第一上电信号生成所述第一上电信号之后检测所述分压单元的第二分压的电压电平上电生成单元，以产生第二上电信号。

2. 发明申请

US20110210794A1 VOLTAGE SENSING CIRCUIT CAPABLE OF CONTROLLING A PUMP VOLTAGE STABLY GENERATED IN A LOW VOLTAGE ENVIRONMENT 有权
标题翻译：电压感应电路可控制在低电压环境中稳定产生的泵电压
公开(公告)号：US20110210794A1
公开(公告)日：2011-09-01
申请号：US13101411
申请日：2011-05-05
申请人： Woo-Seung HAN , Khil-Ohk Kang
发明人： Woo-Seung HAN , Khil-Ohk Kang
IPC分类号： H03F3/45
CPC分类号： G11C5/145
摘要： Herein, a voltage sensing circuit, which is capable of controlling a pumping voltage to be stably generated in a low voltage environment, is provided. The voltage sensing circuit includes a current mirror having first and second terminals, a first switching element configured to control current on the first terminal of the current mirror by a reference voltage, a second switching element configured to control current from the second terminal of the current mirror in response to a pumping voltage, and a third switching element configured to control current sources of the first and second switching elements to receive a negative voltage.
摘要翻译：这里，提供了能够在低电压环境下稳定地产生泵浦电压的电压检测电路。电压检测电路包括具有第一和第二端子的电流镜，第一开关元件，被配置为通过参考电压来控制电流镜的第一端子上的电流;第二开关元件，被配置为控制来自电流的第二端子的电流响应于泵浦电压反射镜;以及第三开关元件，其被配置为控制第一和第二开关元件的电流源以接收负电压。

3. 发明授权

US07936633B2 Circuit and method of generating voltage of semiconductor memory apparatus 失效
标题翻译：电路和半导体存储装置的电压产生方法
公开(公告)号：US07936633B2
公开(公告)日：2011-05-03
申请号：US12575663
申请日：2009-10-08
申请人： Khil-Ohk Kang
发明人： Khil-Ohk Kang
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C11/4074
摘要： A circuit for generating a voltage of a semiconductor memory apparatus includes a control unit that outputs a driving control signal in response to an enable signal and a burn-in signal, a first voltage generating unit that generates and outputs a first voltage in response to the enable signal, and a voltage maintaining unit that maintains the first voltage in response to the driving control signal.
摘要翻译：用于产生半导体存储装置的电压的电路包括：控制单元，其响应于使能信号和老化信号而输出驱动控制信号;第一电压产生单元，其响应于第二电压产生并输出第一电压使能信号，和维持单元，其维持响应于驱动控制信号的第一电压。

4. 发明授权

US07697368B2 Semiconductor memory device and method of inputting addresses therein 失效
标题翻译：半导体存储器件及其中输入地址的方法
公开(公告)号：US07697368B2
公开(公告)日：2010-04-13
申请号：US11967577
申请日：2007-12-31
申请人： Khil-Ohk Kang
发明人： Khil-Ohk Kang
IPC分类号： G11C11/00
CPC分类号： G11C29/48 , G11C8/06 , G11C29/1201
摘要： A semiconductor memory device is capable of reducing a test time by sharing input pins of addresses for the test, thereby reducing test costs also. The semiconductor memory device includes first and second address buffer units. The first address buffer unit is configured to transmit a plurality of normal addresses to an internal circuit and store one or more of the received normal addresses. The second address buffer unit is configured to transmit one or more external bank addresses to the internal circuit as internal bank addresses in a normal mode and transmit addresses stored in the first address buffer unit to the internal circuit as the internal bank addresses in a test mode.
摘要翻译：半导体存储器件能够通过共享用于测试的地址的输入引脚来减少测试时间，从而降低测试成本。半导体存储器件包括第一和第二地址缓冲器单元。第一地址缓冲器单元被配置为向内部电路发送多个正常地址，并且存储所接收的正常地址中的一个或多个。第二地址缓冲器单元被配置为将内部电路中的一个或多个外部存储体地址作为正常模式的内部存储体地址发送，并且将内部存储在第一地址缓冲器单元中的地址作为内部存储体以测试模式地址发送到内部电路。

5. 发明申请

US20100020623A1 CIRCUIT AND METHOD OF GENERATING VOLTAGE OF SEMICONDUCTOR MEMORY APPARATUS 失效
标题翻译：用于生成半导体存储器电压的电路和方法
公开(公告)号：US20100020623A1
公开(公告)日：2010-01-28
申请号：US12575663
申请日：2009-10-08
申请人： KHIL OHK KANG
发明人： KHIL OHK KANG
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C11/4074
摘要： A circuit for generating a voltage of a semiconductor memory apparatus includes a control unit that outputs a driving control signal in response to an enable signal and a burn-in signal, a first voltage generating unit that generates and outputs a first voltage in response to the enable signal, and a voltage maintaining unit that maintains the first voltage in response to the driving control signal.
摘要翻译：用于产生半导体存储装置的电压的电路包括：控制单元，其响应于使能信号和老化信号而输出驱动控制信号;第一电压产生单元，其响应于第二电压产生并输出第一电压使能信号，和维持单元，其维持响应于驱动控制信号的第一电压。

6. 发明申请

US20100014361A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME 失效
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20100014361A1
公开(公告)日：2010-01-21
申请号：US12565587
申请日：2009-09-23
申请人： Khil-Ohk KANG
发明人： Khil-Ohk KANG
IPC分类号： G11C7/06 , G11C7/02
CPC分类号： G11C11/4091 , G11C7/08
摘要： A semiconductor memory device can stabilize a voltage level of a normal driving voltage terminal in a normal driving operation, which is performed after an overdriving operation, even when an overdriving voltage is unstable due to environmental factors of the semiconductor memory device in the overdriving operation. The semiconductor memory device includes a bit line sense amplifier for performing an amplification operation using a normal driving voltage or an overdriving voltage to sense and amplify data applied to bit lines, a normal driving voltage compensator configured to drive a normal driving voltage terminal according to a voltage level of the normal driving voltage terminal and target normal driving voltage levels, and a discharge enable signal generator configured to generate a discharge enable signal by adjusting an activation period of the discharge enable signal according to the overdriving voltage.
摘要翻译：半导体存储器件即使在过驱动操作中由于半导体存储器件的环境因素导致过驱动电压不稳定，也能够在过驱动之后执行的正常驱动操作中稳定正常驱动电压端子的电压电平。半导体存储器件包括：位线读出放大器，用于使用正常驱动电压或过驱动电压进行放大操作，以检测和放大施加到位线的数据;正常驱动电压补偿器，被配置为驱动正常驱动电压端子，正常驱动电压端子的电压电平和目标正常驱动电压电平，以及放电使能信号发生器，被配置为通过根据过驱动电压调节放电使能信号的激活周期来产生放电使能信号。

7. 发明申请

US20090168553A1 Semiconductor memory device and method of operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20090168553A1
公开(公告)日：2009-07-02
申请号：US12217045
申请日：2008-06-30
申请人： Khil-Ohk Kang
发明人： Khil-Ohk Kang
IPC分类号： G11C7/00
CPC分类号： G11C11/4074 , G11C5/143 , G11C5/147 , G11C11/4072
摘要： Semiconductor memory device and method of operating the same includes an enable signal generator configured to generate first and second enable signals having activation timings determined in response to activation of an active command, the first enable signal being deactivated after a first time from a deactivation timing of the active command, and the second enable signal being deactivated after a second time longer than the first time from the deactivation timing of the active command. Internal voltage generators are configured to generate internal voltages. At least one of the internal voltage generators is turned on/off in response to the first enable signal, and at least one other of the internal voltage generators is turned on/off in response to the second enable signals.
摘要翻译：半导体存储器件及其操作方法包括使能信号发生器，其被配置为产生具有响应于有效命令的激活而确定的激活定时的第一和第二使能信号，所述第一使能信号在第一次从停止定时所述激活命令和所述第二使能信号在从所述激活命令的去激活定时开始的第二时间长于所述第一时间之后被去激活。内部电压发生器配置为产生内部电压。内部电压发生器中的至少一个响应于第一使能信号而导通/截止，并且内部电压发生器中的至少一个响应于第二使能信号而导通/截止。

8. 发明授权

US07539072B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07539072B2
公开(公告)日：2009-05-26
申请号：US11647707
申请日：2006-12-29
申请人： Khil-Ohk Kang
发明人： Khil-Ohk Kang
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C5/14 , G11C5/147
摘要： A semiconductor memory device generates an internal voltage by using one detecting circuit at the burn-in and normal modes. The semiconductor memory device includes a burn-in adjusting circuit to produce a burn-in mode test signal, a first reference voltage generating circuit to produce a first reference voltage for a burn-in test in response to the burn-in mode test signal, a second reference voltage generating circuit to produce a second reference voltage for a normal mode, a detecting circuit for detecting voltage levels of the first and second reference voltages and outputting a detection signal and an internal voltage generating circuit for generating an internal voltage in response to the detection signal.
摘要翻译：半导体存储器件通过在老化模式和正常模式下使用一个检测电路产生内部电压。该半导体存储器件包括一个产生老化模式测试信号的老化调节电路，一个响应于老化模式测试信号产生老化测试的第一参考电压的第一参考电压产生电路，第二参考电压产生电路，用于产生用于正常模式的第二参考电压;检测电路，用于检测第一和第二参考电压的电压电平，并输出检测信号;以及内部电压产生电路，用于响应于检测信号。

9. 发明申请

US20080303504A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20080303504A1
公开(公告)日：2008-12-11
申请号：US11987936
申请日：2007-12-06
申请人： Khil-Ohk Kang , Sang-Jin Byeon
发明人： Khil-Ohk Kang , Sang-Jin Byeon
IPC分类号： G05F3/16
CPC分类号： G05F3/30 , G11C5/143 , G11C5/147 , G11C7/04
摘要： A semiconductor device includes: a first reference voltage generator for generating a first reference voltage; a first band gap circuit for dividing a voltage at a second reference voltage output node to produce a first and a second band gap voltages having a property relative to temperature variations; a first comparator for receiving the first reference voltage as a bias input and comparing the first band gap voltage with the second band gap voltage; and a first driver for pull-up driving the second reference voltage output node in response to an output signal of the first comparator.
摘要翻译：半导体器件包括：用于产生第一参考电压的第一参考电压发生器; 第一带隙电路，用于分割第二参考电压输出节点处的电压，以产生具有相对于温度变化的性质的第一和第二带隙电压; 第一比较器，用于接收第一参考电压作为偏置输入，并将第一带隙电压与第二带隙电压进行比较; 以及用于响应于第一比较器的输出信号上拉驱动第二参考电压输出节点的第一驱动器。

10. 发明申请

US20080089149A1 Semiconductor memory apparatus for allocating different read/write operating time to every bank 有权
标题翻译：用于向每个银行分配不同读/写操作时间的半导体存储装置
公开(公告)号：US20080089149A1
公开(公告)日：2008-04-17
申请号：US11822655
申请日：2007-07-09
申请人： Khil-Ohk Kang
发明人： Khil-Ohk Kang
IPC分类号： G11C7/12
CPC分类号： G11C11/406 , G11C7/08 , G11C11/40618 , G11C11/4091 , G11C2207/065 , G11C2211/4065
摘要： A semiconductor memory apparatus includes an active signal generation unit that generates a plurality of active signals having different enable timings in response to a refresh signal, a precharge signal generation unit that delays at least one of the active signals to generate at least one precharge signal for enabling at least two equalizer signals at the same time, and a sense amplifier driver control unit that generates the plurality of equalizer signals for controlling individual sense amplifier drivers in response to the plurality of active signals and the precharge signal.
摘要翻译：一种半导体存储装置，包括有源信号生成单元，其响应于刷新信号生成具有不同的使能定时的多个有源信号;预充电信号生成单元，其延迟至少一个有源信号以生成至少一个预充电信号，同时实现至少两个均衡器信号;以及读出放大器驱动器控制单元，其响应于所述多个有源信号和预充电信号而产生用于控制各个读出放大器驱动器的多个均衡器信号。

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