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51. 发明授权

US07893456B1 Thyristor-based memory and its method of operation 失效
标题翻译：基于晶闸管的存储器及其操作方法
公开(公告)号：US07893456B1
公开(公告)日：2011-02-22
申请号：US12368226
申请日：2009-02-09
申请人： Farid Nemati , Kevin J. Yang
发明人： Farid Nemati , Kevin J. Yang
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： A thyristor-based memory may comprise a thyristor accessible via an access transistor. A temperature dependent bias may be applied to at least one of a supporting substrate and an electrode capacitively-coupled to a base region of the thyristor. The voltage level of the adaptive bias may change with respect to temperature and may influence and/or compensate an inherent bipolar gain of the thyristor in accordance with the change in bias and may enhance its performance and/or reliability over a range of operating temperature. In a particular embodiment, the thyristor may be formed in a layer of silicon of an SOI substrate and the adaptive bias coupled to a supporting substrate of the SOI structure.
摘要翻译：基于晶闸管的存储器可以包括通过存取晶体管可访问的晶闸管。可以将温度依赖偏压施加到电容耦合到晶闸管的基极区域的支撑衬底和电极中的至少一个。自适应偏置的电压电平可以相对于温度而变化，并且可以根据偏置的变化影响和/或补偿晶闸管的固有双极增益，并且可以在一定范围的工作温度下增强其性能和/或可靠性。在特定实施例中，晶闸管可以形成在SOI衬底的硅层中，并且耦合到SOI结构的支撑衬底的自适应偏置。

52. 发明授权

US07859011B2 High ion/Ioff SOI MOSFET using body voltage control 失效
标题翻译：高离子/半导体SOI MOSFET采用体电压控制
公开(公告)号：US07859011B2
公开(公告)日：2010-12-28
申请号：US12368171
申请日：2009-02-09
申请人： Zachary K. Lee , Farid Nemati , Scott Robins
发明人： Zachary K. Lee , Farid Nemati , Scott Robins
IPC分类号： H01L29/74
CPC分类号： H01L27/1203 , H01L29/7841
摘要： A semiconductor device may comprise a partially-depleted SOI MOSFET having a floating body region disposed between a source and drain. The floating body region may be driven to receive injected carriers for adjusting its potential during operation of the MOSFET. In a particular case, the MOSFET may comprise another region of semiconductor material in contiguous relationship with a drain/source region of the MOSFET and on a side thereof opposite to the body region. This additional region may be formed with a conductivity of type opposite the drain/source, and may establish an effective bipolar device per the body, the drain/source and the additional region. The geometries and doping thereof may be designed to establish a transport gain of magnitude sufficient to assist the injection of carriers into the floating body region, yet small enough to guard against inter-latching with the MOSFET.
摘要翻译：半导体器件可以包括部分耗尽的SOI MOSFET，其具有设置在源极和漏极之间的浮体区域。可以驱动浮体区域以接收注入的载流子，以在MOSFET的操作期间调整其电位。在特定的情况下，MOSFET可以包括与MOSFET的漏极/源极区域和与体区域相对的一侧连续关系的半导体材料的另一区域。该附加区域可以形成为具有与漏极/源极相反的类型的导电性，并且可以建立每个主体，漏极/源极和附加区域的有效双极器件。其几何形状和掺杂可被设计成建立足以帮助载流子注入浮体区域的传输增益，但足够小以防止与MOSFET的互锁。

53. 发明授权

US07856545B2 FPGA co-processor for accelerated computation 有权
标题翻译： FPGA协处理器用于加速计算
公开(公告)号：US07856545B2
公开(公告)日：2010-12-21
申请号：US11829801
申请日：2007-07-27
申请人： Steven Casselman
发明人： Steven Casselman
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F15/7867 , H05K1/0286 , H05K1/141 , H05K2201/10212 , H05K2201/10325 , H05K2201/10689 , Y02D10/12 , Y02D10/13
摘要： A co-processor module for accelerating computational performance includes a Field Programmable Gate Array (“FPGA”) and a Programmable Logic Device (“PLD”) coupled to the FPGA and configured to control start-up configuration of the FPGA. A non-volatile memory is coupled to the PLD and configured to store a start-up bitstream for the start-up configuration of the FPGA. A mechanical and electrical interface is for being plugged into a microprocessor socket of a motherboard for direct communication with at least one microprocessor capable of being coupled to the motherboard. After completion of a start-up cycle, the FPGA is configured for direct communication with the at least one microprocessor via a microprocessor bus to which the microprocessor socket is coupled.
摘要翻译：用于加速计算性能的协处理器模块包括耦合到FPGA的现场可编程门阵列（“FPGA”）和可编程逻辑器件（“PLD”），并被配置为控制FPGA的启动配置。非易失性存储器耦合到PLD并且被配置为存储用于FPGA的启动配置的启动比特流。机械和电气接口用于插入到母板的微处理器插座中，用于与至少一个能够耦合到母板的微处理器直接通信。在完成启动周期之后，FPGA配置成经由与微处理器插座耦合到的微处理器总线与至少一个微处理器直接通信。

54. 发明授权

US07578337B2 Heat dissipating device 失效
标题翻译：散热装置
公开(公告)号：US07578337B2
公开(公告)日：2009-08-25
申请号：US11262301
申请日：2005-10-27
申请人： Michael Spokoiny , James M. Kerner , Craig J. Lux , James M. Maurus
发明人： Michael Spokoiny , James M. Kerner , Craig J. Lux , James M. Maurus
IPC分类号： F28F7/00 , F28F13/12 , H05K7/20
CPC分类号： H05K7/20254 , F28F3/022 , F28F3/12
摘要： A heat dissipation device with a fluid cavity that utilizes a hybrid of star pins with concave surfaces and sharp edges, and truncated dimples, which creates turbulence and a vortex phenomenon perpendicular to fluid flow transmission, and increases the heat transfer coefficient without increasing restriction of fluid flow through the device. This process increases the heat transfer along local pins which are located around each truncated dimple. This effect allows the use of taller pins than previous devices thus increasing the surface of heat transfer and thus these pins have a more efficient heat transfer coefficient along the total length of the pin, not possible previously. Star pins with sharp edges prevent the distortion of the highly efficient vortex flow which increases fluid flow and simultaneously intensifies the desired phenomena of extraordinary turbulence.
摘要翻译：具有流体腔的散热装置，其利用具有凹面和锋利边缘的星形销的混合物以及截断的凹坑，其产生垂直于流体流动传递的湍流和涡流现象，并且增加传热系数而不增加流体的限制流过设备。该过程增加沿着位于每个截短凹坑周围的局部引脚的热传递。这种效应允许使用比以前的装置更高的销，因此增加了热传递的表面，因此这些销沿着销的总长度具有更有效的传热系数，这是先前不可能的。具有锋利边缘的星形销防止了高效涡流的变形，这增加了流体流动，同时增强了所需的非凡湍流现象。

55. 发明授权

US07554130B1 Reducing effects of parasitic transistors in thyristor-based memory using an isolation or damage region 失效
标题翻译：使用隔离或损坏区域减少寄生晶体管在基于晶闸管的存储器中的影响
公开(公告)号：US07554130B1
公开(公告)日：2009-06-30
申请号：US11361869
申请日：2006-02-23
申请人： Scott Robins , Kevin J. Yang , Rajesh N. Gupta
发明人： Scott Robins , Kevin J. Yang , Rajesh N. Gupta
IPC分类号： H01L29/74
CPC分类号： H01L27/1027 , H01L29/7436
摘要： An integrated circuit having memory, including thyristor-based memory cells, is described, where each of the thyristor-based memory cells includes a thyristor-based storage element and an access transistor. Where the thyristor-based storage element includes an anode region and a cathode region, a pair of the thyristor-based memory cells are commonly coupled via a bitline associated with the access transistor or via a reference voltage line coupled to the anode region. Bitline or anode regions are separated from one another by an isolation region. In another configuration, a bitline region has a locally implant-damaged region to inhibit charge transfer between the pair. In yet another configuration, a storage node contact or contacts respectively can extend over or are coupled to a storage node line extending over an isolation region. In this latter configuration, a source/drain region and the cathode region are separated from one another by an isolation region.
摘要翻译：描述了一种具有存储器的集成电路，包括基于晶闸管的存储单元，其中每个基于晶闸管的存储单元包括基于晶闸管的存储元件和存取晶体管。在基于晶闸管的存储元件包括阳极区域和阴极区域的情况下，一对基于晶闸管的存储单元通常经由与存取晶体管相关联的位线或经由耦合到阳极区域的参考电压线耦合。位线或阳极区域通过隔离区域彼此分离。在另一种配置中，位线区域具有局部注入损坏区域，以阻止该对之间的电荷转移。在另一种配置中，存储节点接触点或触头分别可以延伸超过或耦合到在隔离区域上延伸的存储节点线。在后一种配置中，源极/漏极区域和阴极区域通过隔离区域彼此分离。

56. 发明授权

US07537120B1 System for a hair colorist 有权
标题翻译：发色系统
公开(公告)号：US07537120B1
公开(公告)日：2009-05-26
申请号：US11521761
申请日：2006-09-15
申请人： Rey Cardenas
发明人： Rey Cardenas
IPC分类号： B65D69/00
CPC分类号： B44D2/002
摘要： Equipment for dispensing sheet goods and use of hair coloring solutions, or in other words a system for a hair colorist, is described. An aspect of the invention is a system for a hair colorist including a housing defining a first region capable of receiving one or more sheets of a stack of sheet goods. An indexing device is located on an exterior surface of the housing. A first bowl configured to be mated with the indexing device to restrain movement of the first bowl.
摘要翻译：描述用于分配片状物品和使用染发剂的设备，或换句话说，用于染发剂的系统。本发明的一个方面是一种用于头发着色器的系统，其包括限定能够接收一个或多个片材堆叠的第一区域的壳体。分度装置位于壳体的外表面上。第一碗，其构造成与分度装置配合以限制第一碗的运动。

57. 发明授权

US07381999B1 Workfunction-adjusted thyristor-based memory device 失效
标题翻译：工作功能调整晶闸管的存储器件
公开(公告)号：US07381999B1
公开(公告)日：2008-06-03
申请号：US11187777
申请日：2005-07-21
申请人： Kevin J. Yang
发明人： Kevin J. Yang
IPC分类号： H01L29/74
CPC分类号： H01L29/7436 , H01L27/1027 , H01L27/105
摘要： A memory device having a thyristor-based storage element and an access device coupled to the thyristor-based storage element at a common storage node is described. The thyristor-based storage element has a first gate stack, where the first gate stack has a first workfunction configured to a base region of the thyristor-based storage element. The access device has a second gate stack, where the second gate stack has a second workfunction. The first gate stack includes a first conductive layer formed over a gate dielectric and a second conductive layer formed over the first conductive layer. The second gate stack includes the second conductive layer formed over the gate dielectric. The first workfunction is operationally distinct from the second workfunction.
摘要翻译：描述了具有基于晶闸管的存储元件和在公共存储节点处耦合到基于晶闸管的存储元件的存取装置的存储器件。基于晶闸管的存储元件具有第一栅极堆叠，其中第一栅极堆叠具有配置到基于晶闸管的存储元件的基极区域的第一功函数。接入设备具有第二门堆叠，其中第二门堆叠具有第二功函数。第一栅极堆叠包括形成在栅极电介质上的第一导电层和形成在第一导电层上的第二导电层。第二栅极堆叠包括形成在栅极电介质上的第二导电层。第一个功能功能与第二个功能功能不同。

58. 发明授权

US07379381B1 State maintenance pulsing for a memory device 失效
标题翻译：用于存储设备的状态维护脉冲
公开(公告)号：US07379381B1
公开(公告)日：2008-05-27
申请号：US11175057
申请日：2005-07-05
申请人： Richard Roy , Farid Nemati
发明人： Richard Roy , Farid Nemati
IPC分类号： G11C8/00
CPC分类号： G11C11/404 , G11C11/406 , G11C11/40622
摘要： State maintenance of a memory cell and, more particularly, state maintenance pulsing of identified memory cells more frequently than other memory cells, is described. A memory array includes an array of memory cells. State maintenance circuitry is coupled to the array of memory cells. The state maintenance circuitry is configured to select between a first restore address and a second restore address. In a given operation cycle, the first restore address is associated with a first line in the array of memory cells, and the second restore address is associated with a second line in the array of memory cells. The first line has first memory cells coupled thereto. The second line has second memory cells coupled thereto. The first memory cells are capable of passing a threshold retention time with a first frequency of restore cycling. The second memory cells are capable of passing the threshold retention time with a second frequency of restore cycling. The second frequency of restore cycling is greater than the first frequency of restore cycling.
摘要翻译：描述了存储器单元的状态维护，更具体地，描述了比其他存储器单元更频繁地状态维持所标识的存储器单元的脉冲。存储器阵列包括存储器单元阵列。状态维护电路耦合到存储器单元阵列。状态维护电路被配置为在第一恢复地址和第二恢复地址之间进行选择。在给定的操作周期中，第一恢复地址与存储器单元阵列中的第一行相关联，并且第二恢复地址与存储器单元阵列中的第二行相关联。第一行具有耦合到其上的第一存储单元。第二行具有与其耦合的第二存储单元。第一存储器单元能够以第一恢复循环频率通过阈值保持时间。第二存储器单元能够以第二恢复循环频率通过阈值保持时间。恢复循环的第二个频率大于恢复循环的第一个频率。

59. 发明授权

US07319622B1 Bitline shielding for thyristor-based memory 失效
标题翻译：基于晶闸管的存储器的位线屏蔽
公开(公告)号：US07319622B1
公开(公告)日：2008-01-15
申请号：US11174813
申请日：2005-07-05
申请人： Richard Roy
发明人： Richard Roy
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C5/025 , G11C7/12 , G11C7/18 , G11C2211/5614
摘要： Method and apparatus for writing and reading information to and from a memory cell. For a read, a write path is used to electrically shield at least one adjacent bitline from a bitline associated with the memory cell to be read, and the memory cell is read while the at least one adjacent bitline is electrically shielded from the bitline associated with the memory cell being read. For a write, the write path is used to electrically shield at the least one adjacent bitline from a bitline associated with a memory cell to be written to; memory cells coupled to a wordline are read and buffered; and the memory cell is written to while the at least one adjacent bitline is electrically shielded from the writing to the memory cell.
摘要翻译：用于向存储器单元写入和读取信息的方法和装置。对于读取，写入路径用于将电子屏蔽来自与要读取的存储器单元相关联的位线的至少一个相邻位线，并且读取存储器单元，同时将至少一个相邻位线与与...相关联的位线电屏蔽正在读取存储单元。对于写入，写入路径用于在与要写入的存储器单元相关联的位线的至少一个相邻位线处电屏蔽; 耦合到字线的存储单元被读取和缓冲; 并且所述存储单元被写入，而所述至少一个相邻位线与所述存储单元的写入电屏蔽。

60. 发明授权

US07152520B2 Method and apparatus for collecting liquid and extracting tea essence from a tea bag 有权
标题翻译：收集液体并从茶包中提取茶精的方法和设备
公开(公告)号：US07152520B2
公开(公告)日：2006-12-26
申请号：US10943789
申请日：2004-09-17
申请人： James M. Kerner
发明人： James M. Kerner
IPC分类号： A47J19/02 , A23N1/00 , B30B9/02
CPC分类号： A47G19/12 , A47G21/106
摘要： A tea bag press and container assembly configured for receiving a tea bag during or after brewing, which conceals the wet tea bag, collects dripping liquid, and extracts tea liquid essence by efficiently compressing the wet tea bag vertically or sidewardly. In a vertical compression embodiment, a lid has an integral press element that compresses the tea bag against a tea bag support means in the bottom of the container upon applying pressure to the lid. In a sideward compression embodiment, a flexible container retains the tea bag during sideward compression, such as between the thumb and fingers, for releasing tea liquid from the bag. The tea bag press-container assembly is designed to reduce staining and mess on saucers, tables and fabric caused by a dripping tea bag and provides efficient extraction and pouring of tea liquid into an existing beverage, or the brewing of an additional beverage.
摘要翻译：一种茶袋压榨容器组件，其构造为在冲泡期间或之后接收茶包，其隐藏湿茶袋，收集滴液，并通过有效地压缩湿茶袋垂直或侧向提取茶液精华。在垂直压缩实施例中，盖子具有整体的压力元件，该压力元件在向盖子施加压力时将茶袋压靠在容器底部的茶袋支撑装置上。在侧向压缩实施例中，柔性容器在侧向压缩期间（例如拇指和手指之间）保留茶袋，用于从袋中释放茶液。茶袋压力容器组件设计用于减少由滴水茶包引起的碟子，桌子和织物上的污染和混乱，并且可以有效地将茶液提取并倒入现有饮料中，或者冲泡另外的饮料。

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