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1. 发明授权

US10573368B2 Memory system having combined high density, low bandwidth and low density, high bandwidth memories 有权
公开(公告)号：US10573368B2
公开(公告)日：2020-02-25
申请号：US16098916
申请日：2017-03-06
申请人： Sukalpa Biswas , Farid Nemati
发明人： Sukalpa Biswas , Farid Nemati
IPC分类号： G11C11/402 , G11C5/06 , G11C5/02 , G11C7/02 , G11C11/406 , H01L25/065 , H01L27/02
摘要： In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g. an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

2. 发明授权

US09082494B2 Memory cells having a common gate terminal 有权
标题翻译：具有公共栅极端子的存储单元
公开(公告)号：US09082494B2
公开(公告)日：2015-07-14
申请号：US13350061
申请日：2012-01-13
申请人： Rajesh N. Gupta , Farid Nemati
发明人： Rajesh N. Gupta , Farid Nemati
IPC分类号： G11C11/00 , G11C11/16 , H01L45/00 , H01L27/22 , H01L27/24
CPC分类号： H01L27/2454 , G11C11/161 , G11C11/1659 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/141 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1608
摘要： Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.
摘要翻译：这里描述了具有公共栅极端子的存储单元阵列及其操作和形成方法。作为示例，存储器单元阵列可以包括一组存储器单元，每个存储单元具有耦合到选择器件的电阻存储元件。每个选择装置包括第一端子，第二端子和栅极端子，其中栅极端子对于该组的每个存储器单元是公用的。

3. 发明授权

US07893456B1 Thyristor-based memory and its method of operation 失效
标题翻译：基于晶闸管的存储器及其操作方法
公开(公告)号：US07893456B1
公开(公告)日：2011-02-22
申请号：US12368226
申请日：2009-02-09
申请人： Farid Nemati , Kevin J. Yang
发明人： Farid Nemati , Kevin J. Yang
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： A thyristor-based memory may comprise a thyristor accessible via an access transistor. A temperature dependent bias may be applied to at least one of a supporting substrate and an electrode capacitively-coupled to a base region of the thyristor. The voltage level of the adaptive bias may change with respect to temperature and may influence and/or compensate an inherent bipolar gain of the thyristor in accordance with the change in bias and may enhance its performance and/or reliability over a range of operating temperature. In a particular embodiment, the thyristor may be formed in a layer of silicon of an SOI substrate and the adaptive bias coupled to a supporting substrate of the SOI structure.
摘要翻译：基于晶闸管的存储器可以包括通过存取晶体管可访问的晶闸管。可以将温度依赖偏压施加到电容耦合到晶闸管的基极区域的支撑衬底和电极中的至少一个。自适应偏置的电压电平可以相对于温度而变化，并且可以根据偏置的变化影响和/或补偿晶闸管的固有双极增益，并且可以在一定范围的工作温度下增强其性能和/或可靠性。在特定实施例中，晶闸管可以形成在SOI衬底的硅层中，并且耦合到SOI结构的支撑衬底的自适应偏置。

4. 发明授权

US07859011B2 High ion/Ioff SOI MOSFET using body voltage control 失效
标题翻译：高离子/半导体SOI MOSFET采用体电压控制
公开(公告)号：US07859011B2
公开(公告)日：2010-12-28
申请号：US12368171
申请日：2009-02-09
申请人： Zachary K. Lee , Farid Nemati , Scott Robins
发明人： Zachary K. Lee , Farid Nemati , Scott Robins
IPC分类号： H01L29/74
CPC分类号： H01L27/1203 , H01L29/7841
摘要： A semiconductor device may comprise a partially-depleted SOI MOSFET having a floating body region disposed between a source and drain. The floating body region may be driven to receive injected carriers for adjusting its potential during operation of the MOSFET. In a particular case, the MOSFET may comprise another region of semiconductor material in contiguous relationship with a drain/source region of the MOSFET and on a side thereof opposite to the body region. This additional region may be formed with a conductivity of type opposite the drain/source, and may establish an effective bipolar device per the body, the drain/source and the additional region. The geometries and doping thereof may be designed to establish a transport gain of magnitude sufficient to assist the injection of carriers into the floating body region, yet small enough to guard against inter-latching with the MOSFET.
摘要翻译：半导体器件可以包括部分耗尽的SOI MOSFET，其具有设置在源极和漏极之间的浮体区域。可以驱动浮体区域以接收注入的载流子，以在MOSFET的操作期间调整其电位。在特定的情况下，MOSFET可以包括与MOSFET的漏极/源极区域和与体区域相对的一侧连续关系的半导体材料的另一区域。该附加区域可以形成为具有与漏极/源极相反的类型的导电性，并且可以建立每个主体，漏极/源极和附加区域的有效双极器件。其几何形状和掺杂可被设计成建立足以帮助载流子注入浮体区域的传输增益，但足够小以防止与MOSFET的互锁。

5. 发明授权

US07379381B1 State maintenance pulsing for a memory device 失效
标题翻译：用于存储设备的状态维护脉冲
公开(公告)号：US07379381B1
公开(公告)日：2008-05-27
申请号：US11175057
申请日：2005-07-05
申请人： Richard Roy , Farid Nemati
发明人： Richard Roy , Farid Nemati
IPC分类号： G11C8/00
CPC分类号： G11C11/404 , G11C11/406 , G11C11/40622
摘要： State maintenance of a memory cell and, more particularly, state maintenance pulsing of identified memory cells more frequently than other memory cells, is described. A memory array includes an array of memory cells. State maintenance circuitry is coupled to the array of memory cells. The state maintenance circuitry is configured to select between a first restore address and a second restore address. In a given operation cycle, the first restore address is associated with a first line in the array of memory cells, and the second restore address is associated with a second line in the array of memory cells. The first line has first memory cells coupled thereto. The second line has second memory cells coupled thereto. The first memory cells are capable of passing a threshold retention time with a first frequency of restore cycling. The second memory cells are capable of passing the threshold retention time with a second frequency of restore cycling. The second frequency of restore cycling is greater than the first frequency of restore cycling.
摘要翻译：描述了存储器单元的状态维护，更具体地，描述了比其他存储器单元更频繁地状态维持所标识的存储器单元的脉冲。存储器阵列包括存储器单元阵列。状态维护电路耦合到存储器单元阵列。状态维护电路被配置为在第一恢复地址和第二恢复地址之间进行选择。在给定的操作周期中，第一恢复地址与存储器单元阵列中的第一行相关联，并且第二恢复地址与存储器单元阵列中的第二行相关联。第一行具有耦合到其上的第一存储单元。第二行具有与其耦合的第二存储单元。第一存储器单元能够以第一恢复循环频率通过阈值保持时间。第二存储器单元能够以第二恢复循环频率通过阈值保持时间。恢复循环的第二个频率大于恢复循环的第一个频率。

6. 发明授权

US07365373B2 Thyristor-type memory device 失效
标题翻译：晶闸管型存储器件
公开(公告)号：US07365373B2
公开(公告)日：2008-04-29
申请号：US11206627
申请日：2005-08-18
申请人： Farid Nemati , James D. Plummer
发明人： Farid Nemati , James D. Plummer
IPC分类号： H01L29/423
CPC分类号： H01L29/74 , G11C11/39 , H01L27/0617 , H01L27/0688 , H01L27/1023 , H01L27/1027 , H01L27/11 , H01L27/1104 , H01L29/41716 , H01L29/42308 , H01L29/749 , H01L29/87
摘要： A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word line that is used to provide read and write access to the memory cell. A second word line is located adjacent to and separated by an insulative material from one of the doped regions of the thyristor device for write operations to the memory cell, for example, by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and/or from the low conductance state to the high conductance. This type of memory circuit can be implemented to significantly reduce standby power consumption and access time.
摘要翻译：晶闸管器件可用于实现包括高密度存储单元阵列和单个单元电路的各种半导体存储器电路。在一个示例性实施例中，晶闸管器件包括具有相反极性的掺杂区域，以及用于向存储器单元提供读取和写入访问的第一字线。第二字线例如通过增强晶闸管器件从高电导状态到高电导状态的切换而位于与用于写入操作的晶闸管器件的掺杂区域中的一个的绝缘材料相邻并由绝缘材料隔开的位置低电导状态和/或从低电导状态到高电导状态。可以实现这种类型的存储器电路，以显着降低待机功耗和访问时间。

7. 发明授权

US07304327B1 Thyristor circuit and approach for temperature stability 失效
标题翻译：晶闸管电路和温度稳定性方法
公开(公告)号：US07304327B1
公开(公告)日：2007-12-04
申请号：US10706162
申请日：2003-11-12
申请人： Farid Nemati , Kailash Gopalakrishnan , Andrew E. Horch
发明人： Farid Nemati , Kailash Gopalakrishnan , Andrew E. Horch
IPC分类号： H01L29/745
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： Switching operations, such as those used in memory devices, are enhanced using a semiconductor device having a thyristor adapted to switch between conducting and blocking states and operate at low power. According to an example embodiment of the present invention, thyristor characteristics are managed over a broad temperature range using a control circuit for coupling a signal, such as a DC voltage signal, to a portion of a thyristor for controlling temperature-related operation thereof, e.g., for controlling bipolar gains. In one implementation, a control port adaptively adjusts a signal coupled to the thyristor as a function of temperature, such that at relatively low temperatures unwanted increases in holding current (IH) are prevented. In another implementation, the control port couples the signal at relatively high temperature operation for controlling the forward blocking voltage (VFB) in such a manner that a blocking state of the thyristor is held. In still another implementation, a circuit controller is adapted for applying the signal to the thyristor via the control port as a function of temperature by monitoring operation of a reference thyristor. With these approaches, thyristor operation can be maintained in a relatively stable manner over a broad temperature range.
摘要翻译：使用具有适于在导通和阻塞状态之间切换并且以低功率操作的晶闸管的半导体器件来增强诸如存储器件中使用的切换操作。根据本发明的示例性实施例，使用用于将诸如DC电压信号的信号耦合到用于控制其温度相关操作的晶闸管的一部分的控制电路，在宽温度范围内管理晶闸管特性，例如，用于控制双极增益。在一个实施方案中，控制端口自适应地调节作为温度的函数耦合到晶闸管的信号，使得在相对较低的温度下，防止了保持电流（I H H）的不期望的增加。在另一实施方案中，控制端口以相对较高的温度操作耦合信号，以便控制可控硅晶闸管的阻塞状态的方式来控制正向阻断电压（V SUB FB）。在另一个实施方式中，电路控制器适于通过监视参考晶闸管的操作，通过控制端口将信号作为温度的函数施加到晶闸管。利用这些方法，可以在宽的温度范围内以相对稳定的方式保持晶闸管操作。

8. 发明授权

US07109532B1 High Ion/Ioff SOI MOSFET using body voltage control 失效
公开(公告)号：US07109532B1
公开(公告)日：2006-09-19
申请号：US10746758
申请日：2003-12-23
申请人： Zachary K. Lee , Farid Nemati , Scott Robins
发明人： Zachary K. Lee , Farid Nemati , Scott Robins
IPC分类号： H01L29/74 , H01L27/12
CPC分类号： H01L27/1203 , H01L29/7841
摘要： A semiconductor device may comprise a partially-depleted SOI MOSFET having a floating body region disposed between a source and drain. The floating body region may be driven to receive injected carriers for adjusting its potential during operation of the MOSFET. In a particular case, the MOSFET may comprise another region of semiconductor material in contiguous relationship with a drain/source region of the MOSFET and on a side thereof opposite to the body region. This additional region may be formed with a conductivity of type opposite the drain/source, and may establish an effective bipolar device per the body, the drain/source and the additional region. The geometries and doping thereof may be designed to establish a transport gain of magnitude sufficient to assist the injection of carriers into the floating body region, yet small enough to guard against inter-latching with the MOSFET.

9. 发明申请

US20060011940A1 Thyristor-type memory device 失效
标题翻译：晶闸管型存储器件
公开(公告)号：US20060011940A1
公开(公告)日：2006-01-19
申请号：US11206627
申请日：2005-08-18
申请人： Farid Nemati , James Plummer
发明人： Farid Nemati , James Plummer
IPC分类号： H01L29/423
CPC分类号： H01L29/74 , G11C11/39 , H01L27/0617 , H01L27/0688 , H01L27/1023 , H01L27/1027 , H01L27/11 , H01L27/1104 , H01L29/41716 , H01L29/42308 , H01L29/749 , H01L29/87
摘要： A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word line that is used to provide read and write access to the memory cell. A second word line is located adjacent to and separated by an insulative material from one of the doped regions of the thyristor device for write operations to the memory cell, for example, by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and/or from the low conductance state to the high conductance. This type of memory circuit can be implemented to significantly reduce standby power consumption and access time.
摘要翻译：晶闸管器件可用于实现包括高密度存储单元阵列和单个单元电路的各种半导体存储器电路。在一个示例性实施例中，晶闸管器件包括具有相反极性的掺杂区域，以及用于向存储器单元提供读取和写入访问的第一字线。第二字线例如通过增强晶闸管器件从高电导状态到高电导状态的切换而位于与用于写入操作的晶闸管器件的掺杂区域中的一个的绝缘材料相邻并由绝缘材料隔开的位置低电导状态和/或从低电导状态到高电导状态。可以实现这种类型的存储器电路，以显着降低待机功耗和访问时间。

10. 发明授权

US06911680B1 Self-aligned thin capacitively-coupled thyristor structure 失效
标题翻译：自对准薄电容耦合晶闸管结构
公开(公告)号：US06911680B1
公开(公告)日：2005-06-28
申请号：US10890031
申请日：2004-07-13
申请人： Andrew Horch , Scott Robins , Farid Nemati
发明人： Andrew Horch , Scott Robins , Farid Nemati
IPC分类号： H01L21/331 , H01L27/11 , H01L29/74 , H01L29/745
CPC分类号： H01L29/66242 , H01L27/11 , H01L29/7436 , H01L29/7455
摘要： A semiconductor memory device having a thyristor is manufactured in a manner that makes possible self-alignment of one or more portions of the thyristor. According to an example embodiment of the present invention, a gate is formed over a first portion of doped substrate. The gate is used to mask a portion of the doped substrate and a second portion of the substrate is doped before or after a spacer is formed. After the second portion of the substrate is doped, the spacer is then formed adjacent to the gate and used to mask the second portion of the substrate while a third portion of the substrate is doped. The gate and spacer are thus used to form self-aligned doped portions of the substrate, wherein the first and second portions form base regions and the third portion form an emitter region of a thyristor. In another implementation, the spacer is also adapted to prevent formation of salicide on the portion of the thyristor beneath the spacer, self-aligning the salicide to the junction between the second and third portions. In addition, dimensions such as width and other characteristics of the doped portions that are used to form a thyristor can be controlled without necessarily using a separate mask.
摘要翻译：制造具有晶闸管的半导体存储器件以能够使晶闸管的一个或多个部分自对准的方式。根据本发明的示例性实施例，在掺杂衬底的第一部分上形成栅极。栅极用于掩模掺杂衬底的一部分，并且衬底的第二部分在形成间隔物之前或之后被掺杂。在衬底的第二部分被掺杂之后，然后在衬底的第三部分被掺杂的同时，将衬底形成为邻近栅极并用于掩蔽衬底的第二部分。因此，栅极和间隔物用于形成衬底的自对准掺杂部分，其中第一和第二部分形成基极区，第三部分形成晶闸管的发射极区。在另一实施方案中，间隔物还适于防止在间隔物下方的可控硅部分上形成自对准硅化物，使自对准硅化物与第二和第三部分之间的连接处。此外，可以控制用于形成晶闸管的掺杂部分的宽度和其它特性的尺寸，而不必使用单独的掩模。

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