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51. 发明授权

US06621310B1 Reducing power consumption variability of precharge-pulldown busses 有权
标题翻译：降低预充电总线的功耗变化
公开(公告)号：US06621310B1
公开(公告)日：2003-09-16
申请号：US09696105
申请日：2000-10-24
申请人： Samuel D. Naffziger
发明人： Samuel D. Naffziger
IPC分类号： H03B100
CPC分类号： H03K19/0016 , H01L2924/0002 , H01L2924/00
摘要： Current pulse matchers monitor the wires of a static or precharge-pulldown bus. Each current pulse matcher monitors the wire that it is connected to. For a precharge-pulldown bus, if the wire has been discharged during the pulldown cycle of the bus, the precharge current pulse matcher does not consume any current. If, however, the wire was not discharged during the pulldown cycle of the bus, then the precharge current pulse matcher consumes an amount of current that approximates the amount of current used to precharge that wire had it been discharged. For a static bus, the current pulse matcher does not shunt current if the wire has not just made a transition. Otherwise, the static bus current pulse matcher shunts an amount of current that may approximates the amount of current used to transition the bus signal from one logic state to another.
摘要翻译：电流脉冲匹配器监视静态或预充电下拉母线的导线。每个电流脉冲匹配器监视它连接的电线。对于预充电下拉母线，如果在总线的下拉周期中导线已经放电，则预充电电流脉冲匹配器不消耗任何电流。然而，如果在总线的下拉周期期间导线没有放电，则预充电电流脉冲匹配器消耗接近用于对已经放电的电线进行预充电的电流量的电流量。对于静态总线，如果电线没有进行过渡，则当前脉冲匹配器不会分流电流。否则，静态总线电流脉冲匹配器分流可能近似于用于将总线信号从一个逻辑状态转换到另一逻辑状态的电流量的电流量。

52. 发明授权

US06556501B1 Multi-port computer register file having shared word lines for read and write ports and storage elements that power down or enter a high-impendance state during write operations 失效
公开(公告)号：US06556501B1
公开(公告)日：2003-04-29
申请号：US09690934
申请日：2000-10-17
申请人： Samuel D. Naffziger
发明人： Samuel D. Naffziger
IPC分类号： G11C800
CPC分类号： G11C8/16 , G11C8/14
摘要： A multi-port computer register file has shared word lines for read and write ports and storage elements that power down during write operations. Assume that a register file in accordance with the present invention has R read ports and W write ports, and R is greater than W. In such a register file, each register will be accessed by W combined read/write word lines, a single direction line, and R-W read-only word lines. The direction line is asserted during a write operation, and is not asserted during a read operation, and also allows the storage elements comprising each register of the register file to be powered down or enter a high-impedance state during a write operation. During a read operation, the direction line remains deasserted and the storage elements remain powered up and active. For read ports sharing combined read/write word lines with write ports, the direction line is used as a multiplexer signal to enable a read operation at the read port represented by the combined read/write word line. For read ports that are not shared, a read-only word line is used to enable the read operation. During a write operation, the direction line is asserted and the storage elements are powered down or enter a high-impedance state. The direction line is used as a multiplexer signal to enable a write operation at the write port represented by the combined read/write word line. When the write operation ends, the direction line is deasserted, and the storage elements are powered up or leave the high-impedance state, thereby retaining the value written to the storage elements. The present invention provides two important benefits over the prior art. First, by powering down storage elements or placing storage elements in a high-impedance state during write operations, smaller transistors can be used to write values into storage elements. By using smaller transistors, the size and power requirements of the register file are reduced. Second, by using a direction line and combined word lines for read and write ports, the number of horizontal lines running across the register file are reduced.

53. 发明授权

US06539527B2 System and method of determining the noise sensitivity of an integrated circuit 有权
公开(公告)号：US06539527B2
公开(公告)日：2003-03-25
申请号：US09812661
申请日：2001-03-19
申请人： Samuel D. Naffziger , John D Wanek
发明人： Samuel D. Naffziger , John D Wanek
IPC分类号： G06F945
CPC分类号： G06F17/5036 , G01R31/002
摘要： The present invention includes an apparatus and a method of designing integrated circuits in which the susceptibility of the integrated circuit to noise is estimated by analyzing the components of the circuits. Suspected noise susceptibility factors were investigated to determine the effects of various potential factors on noise characteristics. It was determined that percent of “bad” capacitance to total capacitance of wire coupling pairs of components, the total length of the corresponding wires between pairs of components that are subject to capacitive coupling and driver output impedance of driving circuits each contributed significantly to noise factors in integrated circuits. It was also determined that the integrated circuit being analyzed can be analyzed as pairs of coupled components (drivers, receivers an interconnections between drivers and receivers) to which the noise susceptibility factors can be applied and used to determine the overall susceptibility of noise of the circuit.

54. 发明授权

US06509788B2 System and method utilizing on-chip voltage controlled frequency modulation to manage power consumption 有权
公开(公告)号：US06509788B2
公开(公告)日：2003-01-21
申请号：US09811255
申请日：2001-03-16
申请人： Samuel D. Naffziger , Don D Josephson
发明人： Samuel D. Naffziger , Don D Josephson
IPC分类号： H01J1982
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A system and method are disclosed which utilize an on-chip oscillator to provide the appropriate clock frequency for components of the chip to manage power consumption by the chip. More specifically, in a preferred embodiment of the present invention, an on-chip oscillator is utilized to provide the clock frequency for the chip's core circuitry, and such oscillator can dynamically adjust such clock frequency to manage the chip's power consumption. Thus, such on-chip oscillator generates the processor clock instead of the usual synchronous, externally controlled clock generator. A preferred embodiment of the present invention utilizes a voltage controlled frequency oscillator to control the chip's clock frequency in order to dynamically manage power consumption by the chip. Such oscillator is preferably operable to adjust its output frequency based on the voltage supplied to such oscillator to effectively manage the chip's power consumption.

55. 发明授权

US6075386A Dynamic logic gate with relaxed timing requirements and output state holding 失效
标题翻译：动态逻辑门具有放松的时序要求和输出状态保持
公开(公告)号：US6075386A
公开(公告)日：2000-06-13
申请号：US955729
申请日：1997-10-22
申请人： Samuel D. Naffziger
发明人： Samuel D. Naffziger
IPC分类号： G01R31/28 , H03K19/00 , H03K19/096
CPC分类号： H03K19/0963
摘要： A dynamic logic gate having a short precharge period during an evaluation phase of a clock and a tri-state hold period during a precharge phase of the clock. The evaluation time is extended into the precharge phase. As a result of extended evaluation time and no latching set-up time, evaluation timing for upstream logic is relaxed since upstream logic is not required to evaluate before the worst case time for the clock to enter the precharge phase. The gate provides the function of latching without the delay of latching. As a result of holding during the precharge phase of the clock, one latch is eliminated for testing. As a result of tri-stating during the precharge phase of the clock, control during testing is simplified. In a single-rail embodiment, the short precharge period is open loop. In a dual-rail implementation, the precharge period ends when both evaluation nodes are charged. In the dual-rail implementation, both evaluate nodes are tri-stated as soon as one node discharges, thereby providing first incidence latching.
摘要翻译：在时钟的预充电阶段期间具有短的预充电周期的动态逻辑门和在时钟的预充电阶段期间的三态保持时段。评估时间延长到预充电阶段。由于扩展的评估时间和没有锁存建立时间，上游逻辑的评估定时被放宽，因为上行逻辑不需要在时钟进入预充电阶段的最差时间之前进行评估。门提供锁定功能，无需延迟锁存。作为在时钟的预充电阶段期间保持的结果，消除了一个锁存器用于测试。由于在时钟的预充电阶段进行三态化的结果，简化了测试期间的控制。在单轨实施例中，短预充电周期是开环的。在双轨实现中，当两个评估节点被充电时，预充电周期结束。在双轨实现中，一旦节点放电，两个评估节点都是三态的，从而提供第一入射锁存。

56. 发明授权

US5949825A Regenerative clamp for multi-drop busses 失效
标题翻译：多滴总线的再生夹
公开(公告)号：US5949825A
公开(公告)日：1999-09-07
申请号：US932438
申请日：1997-09-17
申请人： Samuel D. Naffziger
发明人： Samuel D. Naffziger
IPC分类号： G06F3/00 , G06F13/40 , H03K5/007 , H03K5/08 , H03K5/1252 , H03K17/16 , H03K19/0175 , H04B3/00 , H04L23/00 , H04L25/02
CPC分类号： H03K5/1252 , H04L25/02
摘要： Reflections on bus stubs are reduced by sensing when transition occurs on the bus. When a transition is detected, an impedance matched clamp device is activated that clamps the signal to the new (post-transition) voltage for a short period of time. This clamping action reduces the energy in the reflected wave which reduces the ability of the reflected wave to change the voltage on the bus. A receiver detects when a transition occurs on the bus. The output of the receiver is coupled to a delay device. Logic gates combine the output of the delay device with the output of the receiver to produce two pulsed outputs. One pulsed output is pulsed in response to a low-to-high transition on the bus, the other pulsed output is pulsed in response to a high-to-low transition on the bus. These pulsed outputs control the clamp devices so that the clamp devices are only turned on for a short period of time.
摘要翻译：通过检测总线上的转换是否减少了母线短路的反射。当检测到转换时，启动阻抗匹配钳位装置，将信号钳位到新的（转换后）电压一段短时间。这种夹紧动作降低了反射波中的能量，从而降低了反射波改变总线电压的能力。接收机检测总线上何时发生转换。接收机的输出耦合到延迟装置。逻辑门将延迟器件的输出与接收器的输出相结合，产生两个脉冲输出。响应于总线上的低到高跃迁，一个脉冲输出被脉冲响应，另一个脉冲输出响应于总线上的高到低的转换脉冲。这些脉冲输出控制钳位装置，使钳位装置只在短时间内打开。

57. 发明授权

US5677863A Method of performing operand increment in a booth recoded multiply array 失效
标题翻译：在展位重编码乘法阵列中执行操作数增量的方法
公开(公告)号：US5677863A
公开(公告)日：1997-10-14
申请号：US627615
申请日：1996-04-04
申请人： Samuel D. Naffziger
发明人： Samuel D. Naffziger
IPC分类号： G06F7/50 , G06F7/52
CPC分类号： G06F7/5338 , G06F7/5055
摘要： A new and unique method of performing operand increment in a Booth recoded multiply array. Use of the new method allows operands to be incremented without adding any delay to the multiply array. Added hardware is minimal and requires very little surface area on an IC. The method comprises partitioning a multiplier into overlapping groups of N bits, wherein a first of a number of multiplier partitions comprises the multiplier's least significant bits, and a placeholder bit of less significance than the multiplier's least significant bits. The placeholder bit is set to a logic "1" when desiring to increment the multiplier. Multiples of a multiplicand are generated. Generation of even multiples necessitates shifts of the multiplicand. Bit vacancies created during these shifts are filled with logic "1"s when desiring to increment the multiplicand. Multiplicand multiples are then inverted. The multiplicand increment bit is exclusively ORed with the sign bit of each of the generated multiplicand multiples, and the outputs of the exclusive OR gates are added to the least significant bit positions of respective multiplicand multiples. Operation of the multiply array is otherwise similar to the operation of a standard Booth recoded multiply array.
摘要翻译：一种在Booth重新编码的乘法数组中执行操作数增量的新颖而独特的方法。使用新方法允许增加操作数，而不会对乘法数组造成任何延迟。添加的硬件很少，IC上的表面积很小。该方法包括将乘法器划分成N个比特的重叠组，其中多个乘法器分区中的第一个包括乘法器的最低有效位，以及比乘法器的最低有效位更不重要的占位符比特。当希望增加乘数时，占位符位设置为逻辑“1”。产生被乘数的倍数。乘法生成需要被乘数的移位。当想要增加被乘数时，在这些班次期间创建的位空位将填充逻辑“1”。然后将乘数乘以倒数。被乘数增量位与生成的被乘数中的每一个的符号位进行异或运算，并且异或门的输出被加到相应被乘数的最低有效位位置。乘法阵列的操作与标准布斯重编码乘法阵列的操作相似。

58. 发明授权

US09092219B2 Method and system of sampling to automatically scale digital power estimates with frequency 有权
标题翻译：采样的方法和系统，以频率自动缩放数字功率估计
公开(公告)号：US09092219B2
公开(公告)日：2015-07-28
申请号：US12917928
申请日：2010-11-02
申请人： Samuel D. Naffziger , Suresh B. Periyacheri
发明人： Samuel D. Naffziger , Suresh B. Periyacheri
IPC分类号： G06F1/32 , G01R31/317
CPC分类号： G06F11/3062 , G01R21/133 , G01R31/31721 , G06F1/3203 , G06F1/3206 , G06F1/3234 , Y02D10/00 , Y02D10/10
摘要： A method for automatically scaling estimates of digital power consumed by a portion of an integrated circuit (IC) device by the operating frequency of the portion of the IC are described herein. The method may include obtaining an energy value which may correspond to an amount of energy used by the portion of the IC. A cumulative energy value may be generated by repeatedly, at a frequency proportional to the operating frequency of the portion of the IC, obtaining energy values and adding each obtained energy value to a sum of energy values for the portion of the IC. The cumulative energy value may be sampled at a time sample interval to generate an estimate of the portion of the IC's digital power consumption that is automatically scaled with the operating frequency of the portion of the IC.
摘要翻译：本文描述了通过IC的该部分的工作频率自动缩放由集成电路（IC）器件的一部分消耗的数字功率的估计的方法。该方法可以包括获得可以对应于IC的该部分使用的能量的量的能量值。可以通过以与IC的该部分的工作频率成比例的频率重复地产生累积能量值，获得能量值并将每个获得的能量值加到IC的该部分的能量值之和。可以在时间采样间隔对累积能量值进行采样，以产生IC的数字功率消耗的部分的估计，该部分由IC部分的工作频率自动缩放。

59. 发明授权

US08942932B2 Determining transistor leakage for an integrated circuit 有权
标题翻译：确定集成电路的晶体管漏电流
公开(公告)号：US08942932B2
公开(公告)日：2015-01-27
申请号：US12872916
申请日：2010-08-31
申请人： Samuel D. Naffziger
发明人： Samuel D. Naffziger
IPC分类号： G21C17/00 , G06F17/30 , G06F1/32
CPC分类号： G06F1/3206
摘要： Techniques are disclosed relating to determining power consumption of an integrated circuit. In one embodiment, an integrated circuit is disclosed that includes a power monitor unit configured to receive a temperature of the integrated circuit, and to determine an estimate of power consumed by transistor leakage of the integrated circuit based on the received temperature. In one embodiment, to determine the estimate, the power monitor unit is configured to multiply a base value and a scaling factor that is adjusted based on the received temperature. In some embodiments, the power monitor unit is configured to receive performance state information of the integrated circuit, and to determine an estimate of power consumed by transistor leakage of the integrated circuit based on the performance state information.
摘要翻译：公开了关于确定集成电路的功率消耗的技术。在一个实施例中，公开了一种集成电路，其包括被配置为接收集成电路的温度的功率监视器单元，并且基于接收到的温度来确定集成电路的晶体管泄漏所消耗的功率的估计。在一个实施例中，为了确定估计，功率监视单元被配置为乘以基于接收温度调整的基值和缩放因子。在一些实施例中，功率监视器单元被配置为接收集成电路的性能状态信息，并且基于性能状态信息来确定集成电路的晶体管泄漏所消耗的功率的估计。

60. 发明授权

US08756442B2 System for processor power limit management 有权
标题翻译：处理器功率限制管理系统
公开(公告)号：US08756442B2
公开(公告)日：2014-06-17
申请号：US12970172
申请日：2010-12-16
申请人： Samuel D. Naffziger , John P. Petry , Kiran Bondalapati , William A. Hughes
发明人： Samuel D. Naffziger , John P. Petry , Kiran Bondalapati , William A. Hughes
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A processor power limiter and method is provided. The processor includes a first programmable location configured to store a processor power target. A power monitor is configured to estimate a power dissipation due to processor load. A power controller is configured to adjust a processor power parameter based on the power target and the power dissipation. The processor may include an interface for an operating system. A second programmable location may be configured to store a software processor power target accessible by the operating system. The processor may also include a sideband interface for an external agent. A third programmable location may be configured to store an agent processor power target accessible by the external agent. The power controller may be configured to adjust a processor core voltage and/or frequency such that the power dissipation stays below the processor power target, software processor power target and the agent processor power target.
摘要翻译：提供了一种处理器功率限制器和方法。处理器包括被配置为存储处理器功率目标的第一可编程位置。功率监视器配置为估计由于处理器负载引起的功耗。功率控制器被配置为基于功率目标和功率消耗来调整处理器功率参数。处理器可以包括用于操作系统的接口。可以将第二可编程位置配置为存储由操作系统可访问的软件处理器功率目标。处理器还可以包括用于外部代理的边带接口。可以将第三可编程位置配置为存储由外部代理可访问的代理处理器功率目标。功率控制器可以被配置为调整处理器核心电压和/或频率，使得功率消耗保持在处理器功率目标，软件处理器功率目标和代理处理器功率目标之下。

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