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1. 发明授权

US08793512B2 Method and apparatus for thermal control of processing nodes 有权
标题翻译：处理节点热控制的方法和装置
公开(公告)号：US08793512B2
公开(公告)日：2014-07-29
申请号：US12915361
申请日：2010-10-29
申请人： Alexander Branover , Samuel D. Naffziger
发明人： Alexander Branover , Samuel D. Naffziger
IPC分类号： G01K1/00 , G01K7/00
CPC分类号： G06F1/206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y02D50/20
摘要： An apparatus and method for per-node thermal control of processing nodes is disclosed. The apparatus includes a plurality of processing nodes, and further includes a power management unit configured to set a first frequency limit for at least one of the plurality of processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold, wherein the first detected temperature is associated with the one of the plurality of processing nodes. The power management unit is further configured to set a second frequency limit for each of the plurality of processing nodes responsive to receiving an indication of a second temperature greater than a second temperature threshold.
摘要翻译：公开了一种用于处理节点的每节点热控制的装置和方法。该装置包括多个处理节点，并且还包括功率管理单元，其被配置为响应于接收到大于第一温度阈值的第一检测温度的指示来设置多个处理节点中的至少一个的第一频率限制，其中所述第一检测温度与所述多个处理节点中的一个相关联。功率管理单元还被配置为响应于接收到大于第二温度阈值的第二温度的指示，为多个处理节点中的每一个设置第二频率限制。

2. 发明授权

US08742817B2 Controlling impedance of a switch using high impedance voltage sources to provide more efficient clocking 有权
标题翻译：使用高阻抗电压源控制开关的阻抗，以提供更有效的时钟
公开(公告)号：US08742817B2
公开(公告)日：2014-06-03
申请号：US13601155
申请日：2012-08-31
申请人： Visvesh S. Sathe , Samuel D. Naffziger
发明人： Visvesh S. Sathe , Samuel D. Naffziger
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/10 , G06F1/04
摘要： A clock system of an integrated circuit includes first and second transistors forming a switch that is used when switching the clock system between a resonant mode of operation and a non-resonant mode of operation. An inductor forms a resonant circuit with capacitance of the clock system in resonant mode. The switch receives a clock signal and supplies the clock signal to the inductor when the switch is closed and disconnects the inductor from the clock system when the switch is open. First and second high impedance voltage sources supply respective first and second voltages to the switch and a gate voltage of the first transistor transitions with the clock signal around the first voltage and a gate voltage of the second transistor transitions with the clock signal around the second voltage such that near constant overdrive voltages are maintained for the first and second transistors.
摘要翻译：集成电路的时钟系统包括形成开关的第一和第二晶体管，该开关用于在谐振工作模式和非谐振工作模式之间切换时钟系统。电感器在谐振模式下形成具有时钟系统的电容的谐振电路。当开关闭合时，开关接收时钟信号并将时钟信号提供给电感器，当开关断开时，断开电感与时钟系统的连接。第一和第二高阻抗电压源向开关提供相应的第一和第二电压，并且第一晶体管的栅极电压以围绕第一电压的时钟信号转变，并且第二晶体管的栅极电压以围绕第二电压的时钟信号转变使得对于第一和第二晶体管保持接近恒定的过驱动电压。

3. 发明授权

US08710868B2 Sense-amplifier monotizer 有权
标题翻译：感应放大器单调器
公开(公告)号：US08710868B2
公开(公告)日：2014-04-29
申请号：US12974203
申请日：2010-12-21
申请人： Samuel D. Naffziger , Visvesh S. Sathe , Srikanth Arekapudi
发明人： Samuel D. Naffziger , Visvesh S. Sathe , Srikanth Arekapudi
IPC分类号： G11C7/00
CPC分类号： G11C7/065
摘要： A sense-amplifier monotizer includes an amplifier circuit and a keeper circuit. The amplifier circuit outputs a predetermined logic state while a clock signal is in a first phase, and samples a data signal and outputs at least one of the data signal and a complementary logic state of the data signal while the clock signal is in a second phase. A subsequent change of the data signal does not affect an output of the amplifier circuit once the data signal is sampled while the clock signal is in the second phase. The keeper circuit keeps a logic state of the sampled data signal once the data signal is sampled while the clock signal is in the second phase. The amplifier circuit may receive multiple data signals, and output a data signal selected by the select signal and/or a complementary value while the clock signal is in the second phase.
摘要翻译：感测放大器单调器包括放大器电路和保持器电路。当时钟信号处于第一阶段时，放大器电路输出预定的逻辑状态，并对数据信号进行采样，并且在时钟信号处于第二阶段时输出数据信号和互补逻辑状态中的至少一个数据信号。一旦数据信号在时钟信号处于第二阶段被采样时，数据信号的随后变化就不影响放大器电路的输出。一旦在时钟信号处于第二阶段，数据信号被采样，保持器电路将保持采样数据信号的逻辑状态。放大器电路可以接收多个数据信号，并且在时钟信号处于第二阶段时输出由选择信号选择的数据信号和/或互补值。

4. 发明申请

US20140062564A1 PROGRAMMABLE CLOCK DRIVER 有权
标题翻译：可编程时钟驱动器
公开(公告)号：US20140062564A1
公开(公告)日：2014-03-06
申请号：US13601175
申请日：2012-08-31
申请人： Visvesh S. Sathe , Srikanth Arekapudi , Samuel D. Naffziger , Manivannan Bhoopathy
发明人： Visvesh S. Sathe , Srikanth Arekapudi , Samuel D. Naffziger , Manivannan Bhoopathy
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A clock driver circuit supplies a clock signal with a drive strength determined according to one or more control signals supplied to the clock driver that vary during run-time. The clock driver is operated with a first drive strength in a non-resonant mode of operation of an associated clock network and with a second drive strength in a resonant mode of operation of the associated clock network, the first drive strength being higher than the second drive strength.
摘要翻译：时钟驱动器电路提供具有根据提供给时钟驱动器的一个或多个控制信号确定的驱动强度的时钟信号，该时钟驱动器在运行时间内变化。时钟驱动器以相关时钟网络的非谐振工作模式的第一驱动强度和相关时钟网络的谐振工作模式下的第二驱动强度操作，第一驱动强度高于第二驱动强度驱动力。

5. 发明授权

US08504854B2 Managing multiple operating points for stable virtual frequencies 有权
标题翻译：为稳定的虚拟频率管理多个操作点
公开(公告)号：US08504854B2
公开(公告)日：2013-08-06
申请号：US12819777
申请日：2010-06-21
申请人： Samuel D. Naffziger , John P. Petry , William A. Hughes
发明人： Samuel D. Naffziger , John P. Petry , William A. Hughes
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A system and method for managing multiple discrete operating points to create a stable virtual operating point. One or more functional blocks within a processor produces data corresponding to an activity level associated with the respective functional block. A power manager determines a power consumption value based on the data once every given sample interval. In addition, the power manager determines a signed accumulated difference over time between a thermal design power (TDP) and the power consumption value. The power manager selects a next power-performance state (P-state) based on comparisons of the signed accumulated difference and given thresholds. Transitioning between P-states in this manner while the workload does not significantly change causes the processor to operate at a virtual operating point between supported discrete operating points.
摘要翻译：一种用于管理多个离散工作点以创建稳定的虚拟操作点的系统和方法。处理器内的一个或多个功能块产生对应于与相应功能块相关联的活动级别的数据。功率管理器基于每个给定采样间隔一次的数据来确定功耗值。此外，功率管理器确定在热设计功率（TDP）和功耗值之间随时间的经签名的积分差。功率管理器基于签名累积差和给定阈值的比较来选择下一个功率性能状态（P状态）。以这种方式在P状态之间转换，而工作负载不会显着变化，导致处理器在支持的离散工作点之间的虚拟工作点运行。

6. 发明授权

US08442786B2 Flexible power reporting in a computing system 有权
标题翻译：计算系统中灵活的电力报告
公开(公告)号：US08442786B2
公开(公告)日：2013-05-14
申请号：US12792308
申请日：2010-06-02
申请人： Samuel D. Naffziger , John P. Petry , Kiran K. Bondalapati , Mom-Eng Ng
发明人： Samuel D. Naffziger , John P. Petry , Kiran K. Bondalapati , Mom-Eng Ng
IPC分类号： G01R21/00 , G06F1/00
CPC分类号： G06F1/3203 , G06F1/206 , H05K7/20836 , Y02D10/16
摘要： A system and method for efficient reporting of power usage. A power reporting unit within a processor receives a power consumption number once every sample interval from a power monitor. The power monitor determines a power consumption number based on sampled signals within one or more functional blocks in the processor, rather than based on temperature. An average power consumption number is computed based on received power consumption numbers for a running time interval, wherein the running time interval is larger than the sample interval. This value is conveyed to an external agent. Responsive to receiving and processing the average power consumption number, the external agent may cause changes in a cooling system.
摘要翻译：一种有效报告电力使用的系统和方法。处理器内的电力报告单元从功率监视器接收每个采样间隔一次的功耗数字。功率监视器基于处理器中的一个或多个功能块内的采样信号而不是基于温度来确定功耗数。基于运行时间间隔的接收功耗数来计算平均功耗数，其中运行时间间隔大于采样间隔。该值传送给外部代理。响应于接收和处理平均功耗数量，外部代理可能导致冷却系统的变化。

7. 发明申请

US20120146708A1 METHOD AND APPARATUS FOR APPLICATION OF POWER DENSITY MULTIPLIERS OPTIMALLY IN A MULTICORE SYSTEM 有权
标题翻译：功率密度乘法器在多系统中的最佳应用方法与装置
公开(公告)号：US20120146708A1
公开(公告)日：2012-06-14
申请号：US12967535
申请日：2010-12-14
申请人： Samuel D. Naffziger , John P. Petry , Sridhar Sundaram
发明人： Samuel D. Naffziger , John P. Petry , Sridhar Sundaram
IPC分类号： H03K3/011
CPC分类号： G06F1/206 , G06F1/3287 , Y02D10/16 , Y02D10/171
摘要： A method and an apparatus are described that delay application of a higher order Power Density Multiplier (PDM) using a time based moving average of a number of active cores in a multicore system. A PDM is applied to a thermal design power budget of a thermal entity and performance of the thermal entity is increased by transferring available power from a thermal entity not in an active state to a thermal entity in an active state. Sufficient time is allowed for the cooling effect of reduced active cores, to influence the active core that receives the extra power (a higher PDM). Similarly delaying application of a lower PDM with the same moving average, but a different threshold, allows a core to retain a higher power allocation until the more active neighbor core(s) cause it to heat up, thereby boosting core performance.
摘要翻译：描述了使用多核系统中的多个活动核心的基于时间的移动平均来延迟应用较高阶功率密度乘数（PDM）的方法和装置。将PDM应用于热实体的热设计功率预算，并且通过将来自不处于活动状态的热实体的可用功率传递到处于活动状态的热实体的可用功率来增加热实体的性能。允许减少活动核心的冷却效果足够的时间来影响接收额外功率的有源核心（较高的PDM）。类似地延迟具有相同移动平均值但是不同阈值的较低PDM的应用允许核心保持较高的功率分配，直到较活跃的相邻核心使其升温，从而提高核心性能。

8. 发明申请

US20120109550A1 METHOD AND SYSTEM OF SAMPLING TO AUTOMATICALLY SCALE DIGITAL POWER ESTIMATES WITH FREQUENCY 有权
标题翻译：采用频率自动调整数字电源估计的方法和系统
公开(公告)号：US20120109550A1
公开(公告)日：2012-05-03
申请号：US12917928
申请日：2010-11-02
申请人： Samuel D. Naffziger , Suresh B. Periyacheri
发明人： Samuel D. Naffziger , Suresh B. Periyacheri
IPC分类号： G06F19/00 , G01R21/00
CPC分类号： G06F11/3062 , G01R21/133 , G01R31/31721 , G06F1/3203 , G06F1/3206 , G06F1/3234 , Y02D10/00 , Y02D10/10
摘要： A method for automatically scaling estimates of digital power consumed by a portion of an integrated circuit (IC) device by the operating frequency of the portion of the IC are described herein. The method may include obtaining an energy value which may correspond to an amount of energy used by the portion of the IC. A cumulative energy value may be generated by repeatedly, at a frequency proportional to the operating frequency of the portion of the IC, obtaining energy values and adding each obtained energy value to a sum of energy values for the portion of the IC. The cumulative energy value may be sampled at a time sample interval to generate an estimate of the portion of the IC's digital power consumption that is automatically scaled with the operating frequency of the portion of the IC.
摘要翻译：本文描述了通过IC的该部分的工作频率自动缩放由集成电路（IC）器件的一部分消耗的数字功率的估计的方法。该方法可以包括获得可以对应于IC的该部分使用的能量的量的能量值。可以通过以与IC的该部分的工作频率成比例的频率重复地产生累积能量值，获得能量值并将每个获得的能量值加到IC的该部分的能量值之和。可以在时间采样间隔对累积能量值进行采样，以产生IC的数字功率消耗的部分的估计，该部分由IC部分的工作频率自动缩放。

9. 发明申请

US20120053897A1 DETERMINING TRANSISTOR LEAKAGE FOR AN INTEGRATED CIRCUIT 有权
标题翻译：确定集成电路的晶体管漏电
公开(公告)号：US20120053897A1
公开(公告)日：2012-03-01
申请号：US12872916
申请日：2010-08-31
申请人： Samuel D. Naffziger
发明人： Samuel D. Naffziger
IPC分类号： G21C17/00 , G06F19/00 , G06F17/30
CPC分类号： G06F1/3206
摘要： Techniques are disclosed relating to determining power consumption of an integrated circuit. In one embodiment, an integrated circuit is disclosed that includes a power monitor unit configured to receive a temperature of the integrated circuit, and to determine an estimate of power consumed by transistor leakage of the integrated circuit based on the received temperature. In one embodiment, to determine the estimate, the power monitor unit is configured to multiply a base value and a scaling factor that is adjusted based on the received temperature. In some embodiments, the power monitor unit is configured to receive performance state information of the integrated circuit, and to determine an estimate of power consumed by transistor leakage of the integrated circuit based on the performance state information.
摘要翻译：公开了关于确定集成电路的功率消耗的技术。在一个实施例中，公开了一种集成电路，其包括被配置为接收集成电路的温度的功率监视器单元，并且基于接收的温度来确定集成电路的晶体管泄漏所消耗的功率的估计。在一个实施例中，为了确定估计，功率监视单元被配置为乘以基于接收温度调整的基值和缩放因子。在一些实施例中，功率监视器单元被配置为接收集成电路的性能状态信息，并且基于性能状态信息来确定集成电路的晶体管泄漏所消耗的功率的估计。

10. 发明授权

US08037445B2 System for and method of controlling a VLSI environment 有权
标题翻译：控制VLSI环境的系统和方法
公开(公告)号：US08037445B2
公开(公告)日：2011-10-11
申请号：US10644625
申请日：2003-08-20
申请人： Christopher A. Poirier , Samuel D. Naffziger , Christopher J. Bostak
发明人： Christopher A. Poirier , Samuel D. Naffziger , Christopher J. Bostak
IPC分类号： G06F17/50 , G06F11/22 , G06F1/26 , G06F1/22 , G06F11/00 , G01K1/08
CPC分类号： G01R31/2884 , H01L23/34 , H01L2924/0002 , H01L2924/00
摘要： An apparatus comprising an integrated circuit on a VLSI die, and an embedded micro-controller constructed on the VLSI die, the micro-controller adapted to monitor and control the VLSI environment to optimize the integrated circuit operation. Another embodiment of the invention is directed to a method for monitoring and controlling an integrated circuit comprising providing an embedded micro-controller on a same VLSI die as the integrated circuit, monitoring and controlling a VLSI environment of the integrated circuit with the embedded micro-controller.
摘要翻译：一种包括VLSI管芯上的集成电路和在VLSI管芯上构建的嵌入式微控制器的装置，该微控制器适用于监测和控制VLSI环境以优化集成电路操作。本发明的另一个实施例涉及一种用于监测和控制集成电路的方法，包括在与集成电路相同的VLSI管芯上提供嵌入式微控制器，利用嵌入式微控制器监视和控制集成电路的VLSI环境。

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