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51. 发明申请

US20150058688A1 SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS 审中-公开
标题翻译：用于共享多个通信协议之间的通信链路的系统和方法
公开(公告)号：US20150058688A1
公开(公告)日：2015-02-26
申请号：US14475894
申请日：2014-09-03
申请人： Texas Instruments Incorporated
发明人： Gary L. Swoboda
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/31705 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/318536 , G01R31/318544 , G01R31/318572
摘要： A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.
摘要翻译：描述了用于共享多个协议之间的通信链路的系统和方法。一种系统包括被配置为使用多个协议中的至少一个与其他系统交换信息的通信接口; 协议选择寄存器，其存储从所述多个协议之中选择协议以成为有效协议的值; 以及通信接口可访问的状态机，用于根据活动协议通过通信接口来控制信息交换的状态机。通信接口使用活动协议来交换信息，而多个协议的剩余协议保持不活动。状态机通过使通信接口根据活动协议进行操作的一系列状态进行排序，并在其余协议下被指定为惰性序列。

52. 发明授权

US08938651B2 Blocking the effects of scan chain testing upon a change in scan chain topology 有权
标题翻译：阻止扫描链测试对扫描链拓扑变化的影响
公开(公告)号：US08938651B2
公开(公告)日：2015-01-20
申请号：US14149139
申请日：2014-01-07
申请人： Texas Instruments Incorporated
发明人： Gary L. Swoboda , Robert A. McGowan
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/317 , G01R31/3185 , G06F11/22
CPC分类号： G01R31/31705 , G01R31/31713 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/3177 , G01R31/318533 , G01R31/318536 , G01R31/318538 , G01R31/318544 , G01R31/318555 , G01R31/318572 , G01R31/318597 , G06F11/2236
摘要： A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.
摘要翻译：系统包括多个组件，耦合到组件的扫描链选择逻辑，以及覆盖耦合到扫描链选择逻辑的选择逻辑。扫描链选择逻辑在主计算机的指导下，将各种组件选择为扫描链的成员。覆盖选择逻辑检测扫描链中的变化，从而阻止整个扫描链的进行。

53. 发明申请

US20140122953A1 BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY 审中-公开
标题翻译：屏蔽SCAN链拓扑变化的扫描链测试的影响
公开(公告)号：US20140122953A1
公开(公告)日：2014-05-01
申请号：US14149139
申请日：2014-01-07
申请人： Texas Instruments Incorporated
发明人： Gary L. Swoboda , Robert A. McGowan
IPC分类号： G01R31/3177
CPC分类号： G01R31/31705 , G01R31/31713 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/3177 , G01R31/318533 , G01R31/318536 , G01R31/318538 , G01R31/318544 , G01R31/318555 , G01R31/318572 , G01R31/318597 , G06F11/2236
摘要： A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.
摘要翻译：系统包括多个组件，耦合到组件的扫描链选择逻辑，以及覆盖耦合到扫描链选择逻辑的选择逻辑。扫描链选择逻辑在主计算机的指导下，将各种组件选择为扫描链的成员。覆盖选择逻辑检测扫描链中的变化，从而阻止整个扫描链的进行。

54. 发明申请

US20140068361A1 OFFLINE AT START UP OF A POWERED ON DEVICE 有权
标题翻译：开机启动时离线
公开(公告)号：US20140068361A1
公开(公告)日：2014-03-06
申请号：US14075092
申请日：2013-11-08
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Gary L. Swoboda
IPC分类号： G01R31/317
CPC分类号： G01R31/3177 , G01R31/317 , G06F1/12 , G06F1/3206 , G06F11/221 , G06F11/2284 , G06F11/267 , H04L7/046
摘要： A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.
摘要翻译：一种方法包括一种系统，该系统包括耦合到根据主机设备和所有远程设备在系统操作期间跟随的状态图主动操作的第一远程设备的主机设备。该方法还包括在主机设备和第一远程设备根据状态图主动操作时加电第二远程设备。第二个远程设备确定是初始化为标准协议还是高级协议。当确定初始化为高级协议时，第二远程设备然后等待同步点序列。

55. 发明授权

US08656234B2 Test port connected to master output of override selection logic 有权
标题翻译：测试端口连接到主输出的覆盖选择逻辑
公开(公告)号：US08656234B2
公开(公告)日：2014-02-18
申请号：US13859968
申请日：2013-04-10
申请人： Texas Instruments Incorporated
发明人： Gary L. Swoboda , Robert A. McGowan
IPC分类号： G01R31/28
CPC分类号： G01R31/31705 , G01R31/31713 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/3177 , G01R31/318533 , G01R31/318536 , G01R31/318538 , G01R31/318544 , G01R31/318555 , G01R31/318572 , G01R31/318597 , G06F11/2236
摘要： A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.
摘要翻译：系统包括多个组件，耦合到组件的扫描链选择逻辑，以及覆盖耦合到扫描链选择逻辑的选择逻辑。扫描链选择逻辑在主计算机的指导下，将各种组件选择为扫描链的成员。覆盖选择逻辑检测扫描链中的变化，从而阻止整个扫描链的进行。

56. 发明申请

US20140040523A1 MINIMIZING THE AMOUNT OF TIME STAMP INFORMATION REPORTED WITH INSTRUMENTATION DATA 有权
标题翻译：最小化用仪器数据报告的时间戳信息
公开(公告)号：US20140040523A1
公开(公告)日：2014-02-06
申请号：US14044478
申请日：2013-10-02
申请人： Texas Instruments Incorporated
发明人： Gary L. Swoboda
IPC分类号： G06F13/40
CPC分类号： G01R31/31725 , G01R31/31703 , G01R31/3177 , G06F11/0757 , G06F13/40 , G06F21/6245 , H04L9/3297
摘要： This invention is time stamping subsystem of an electronic apparatus. A time stamp generator generates a multibit time stamp value including a predetermined number of least significant bits overlapping a predetermined number of most significant bits. Each client receives the least significant bits. Each client associates captured data with a corresponding set of the least significant bits in a message. A central scheduling unit associates most significant bits of the time stamp value with the least significant bits of the message. This associating compares overlap bits of the most significant bits and least significant bits. The most significant bits are decremented until the overlap bits are equal.
摘要翻译：本发明是电子设备的时间戳子系统。时间戳发生器产生包括与预定数量的最高有效位重叠的预定数量的最低有效位的多位时间戳值。每个客户端接收最低有效位。每个客户端将捕获的数据与消息中的对应的最低有效位集合相关联。中央调度单元将时间戳值的最高有效位与消息的最低有效位相关联。该关联比较了最高有效位和最低有效位的重叠位。最高有效位递减直到重叠位相等。

57. 发明申请

US20130311841A1 SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS 有权
公开(公告)号：US20130311841A1
公开(公告)日：2013-11-21
申请号：US13948373
申请日：2013-07-23
申请人： Texas Instruments Incorporated
发明人： Gary L. Swoboda
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/31701 , G01R31/31713 , G01R31/31723 , G01R31/31727 , G01R31/318533 , G01R31/318538 , G01R31/318544 , G06F11/22 , G06F11/267 , G06F11/27 , G06F11/36 , G06F11/3656 , G06F2201/88 , H04L43/50
摘要： Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

58. 发明授权

US08589746B2 Bidirectional clock, data, and control to functional and test circuitry 有权
标题翻译：双向时钟，数据和控制功能和测试电路
公开(公告)号：US08589746B2
公开(公告)日：2013-11-19
申请号：US13693535
申请日：2012-12-04
申请人： Texas Instruments Incorporated
发明人： Gary L. Swoboda
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/3177 , G01R31/31705 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/318536 , G01R31/318544 , G01R31/318572
摘要： A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.
摘要翻译：描述了用于共享多个协议之间的通信链路的系统和方法。一种系统包括被配置为使用多个协议中的至少一个与其他系统交换信息的通信接口; 协议选择寄存器，其存储从所述多个协议之中选择协议以成为有效协议的值; 以及通信接口可访问的状态机，用于根据活动协议通过通信接口来控制信息交换的状态机。通信接口使用活动协议来交换信息，而多个协议的剩余协议保持不活动。状态机通过使通信接口根据活动协议进行操作的一系列状态进行排序，并在其余协议下被指定为惰性序列。

59. 发明申请

US20130179743A1 SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS 有权
公开(公告)号：US20130179743A1
公开(公告)日：2013-07-11
申请号：US13693535
申请日：2012-12-04
申请人： Texas Instruments Incorporated
发明人： Gary L. Swoboda
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/31705 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/318536 , G01R31/318544 , G01R31/318572
摘要： A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.

60. 发明申请

US20130179701A1 SEPARATE DEBUG POWER MANAGEMENT 审中-公开
标题翻译：独立调试电源管理
公开(公告)号：US20130179701A1
公开(公告)日：2013-07-11
申请号：US13738677
申请日：2013-01-10
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Gary L. Swoboda
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/3203
摘要： The power consumption of embedded debug functions in ultra low power SoC sytems is minimized by seggregating the debug logic into separate power domains, and allocating separate power pins to the debug power sources. Debug power may be supplied from an external power source, from the system power source or from a functional communication interface such as USB, JTAG or cJTAG.
摘要翻译：通过将调试逻辑分离为单独的电源域，并将分离的电源引脚分配给调试电源，可以将超低功耗SoC系统中嵌入式调试功能的功耗降至最低。调试电源可以从外部电源，从系统电源或功能通信接口（如USB，JTAG或cJTAG）提供。

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