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1. 发明授权

US10003421B2 Radio analysis apparatus and method 有权
公开(公告)号：US10003421B2
公开(公告)日：2018-06-19
申请号：US15633001
申请日：2017-06-26
申请人： FUJITSU LIMITED
发明人： Tatsuya Kikuzuki
IPC分类号： H04L7/02 , H04B17/391 , H04B1/10 , H04B17/345 , H04B17/364 , G01S3/74 , H01Q3/26 , G01S3/32
CPC分类号： H04B17/391 , G01S3/32 , G01S3/74 , H01Q3/26 , H04B1/1027 , H04B17/345 , H04B17/364 , H04L1/004 , H04L7/02 , H04L7/046 , H04L27/186 , H04L27/2003
摘要： A radio analysis apparatus includes: a processor that calculates a modulation index of a radio signal generated by performing frequency shift keying on a baseband signal, based on phase shift amounts of the radio signal; and a memory that holds information in which bit patterns of the baseband signal are associated with correction values for correcting the phase shift amounts that have dropped by band limitation on the baseband signal. The processor restores the bit patterns of the baseband signal based on the phase shift amounts of the radio signal, corrects the phase shift amounts of the radio signal by using the correction values corresponding to the restored bit patterns, and calculates the modulation index based on the corrected phase shift amounts.

2. 发明授权

US09565041B2 Adaptive equalization using correlation of edge samples with data patterns 有权
标题翻译：使用边缘样本与数据模式相关的自适应均衡
公开(公告)号：US09565041B2
公开(公告)日：2017-02-07
申请号：US14702966
申请日：2015-05-04
申请人： Rambus Inc.
发明人： Robert E. Palmer
IPC分类号： G01N21/00 , H04L27/01 , H04L7/04 , H04L25/06 , H04L25/03
CPC分类号： H04L27/01 , H04L7/041 , H04L7/046 , H04L25/03006 , H04L25/03273 , H04L25/069
摘要： An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.
摘要翻译：集成接收机支持自适应接收均衡。使用从参考时钟信号导出的边缘和数据时钟信号对输入比特流进行采样。相位检测器确定边沿和数据时钟信号是否与输入数据同相，而一些时钟恢复电路根据需要调整边沿和数据时钟信号，使其相位与输入数据相匹配。接收机采用用于恢复边缘和数据时钟信号的边缘和数据样本，以记录一个或多个所选数据模式的过零点的位置。可以从易于产生最大定时误差的那些中选择图案或图案。然后可以调整均衡设置以使所选数据模式的过零点与恢复的边沿时钟信号对齐。

3. 发明申请

US20150256368A1 BI-PHASE COMMUNICATION DEMODULATION TECHNIQUES 审中-公开
标题翻译：双相通信解调技术
公开(公告)号：US20150256368A1
公开(公告)日：2015-09-10
申请号：US14665554
申请日：2015-03-23
申请人： Texas Instruments Incorporated
发明人： Eric Gregory Oettinger
IPC分类号： H04L25/49 , H04L27/22 , H02J7/02 , H04L7/04
CPC分类号： H04L25/4904 , H02J7/025 , H02J50/10 , H04L7/042 , H04L7/046 , H04L27/22
摘要： One aspect of the present invention includes a bi-phase communication receiver system. The system includes an analog-to-digital converter (ADC) configured to sample a bi-phase modulation signal to generate digital samples of the bi-phase modulation signal. The system also includes a bi-phase signal decoder configured to decode the bi-phase modulation signal based on the digital samples. The system further includes a preamble detector comprising a digital filter configured to evaluate the digital samples to generate an output and to detect a preamble of the bi-phase modulation signal for decoding the bi-phase modulation signal based on the output.
摘要翻译：本发明的一个方面包括双相通信接收机系统。该系统包括被配置为对双相调制信号进行采样以生成双相调制信号的数字采样的模数转换器（ADC）。该系统还包括双相信号解码器，其被配置为基于数字样本对双相调制信号进行解码。该系统还包括前导码检测器，其包括数字滤波器，该数字滤波器被配置为评估数字采样以产生输出并且检测用于基于输出对双相调制信号进行解码的双相调制信号的前导码。

4. 发明授权

US08934582B2 Method and apparatus for detecting a set up signal used for data communication over a communication network 有权
标题翻译：用于检测通过通信网络进行数据通信的建立信号的方法和装置
公开(公告)号：US08934582B2
公开(公告)日：2015-01-13
申请号：US12988832
申请日：2008-05-19
申请人： Adrian Susan
发明人： Adrian Susan
IPC分类号： H04L27/06 , H04Q1/457
CPC分类号： H04L43/50 , H04L7/046 , H04Q1/457
摘要： A method of detecting a set up signal having a predetermined frequency and used for data transmissions over a communication network comprises comparing an energy level of a filtered received signal with a first predetermined value and providing a first detect signal, comparing an energy level of a component of the received signal at a predetermined frequency with a second predetermined value and providing a second detect signal. In addition, an autocorrelation function is performed on the received signal to discriminate between the set up signal and other signals in the received signal, and a check signal is provided when the autocorrelation function identifies the set up signal. The set up signal in the received signal is detected in response to the first and the second detect signals and the check signal. A method of detecting phase reversals in the set up signal is also disclosed.
摘要翻译：一种检测具有预定频率并用于通过通信网络进行数据传输的建立信号的方法，包括将经滤波的接收信号的能级与第一预定值进行比较，并提供第一检测信号，比较组件以预定频率具有第二预定值并提供第二检测信号。此外，对接收信号执行自相关函数以区分设置信号和接收信号中的其他信号，并且当自相关函数识别建立信号时，提供校验信号。响应于第一和第二检测信号和检查信号检测接收信号中的建立信号。还公开了一种在建立信号中检测相位反转的方法。

5. 发明授权

US08897410B2 Device for receiving a digital signal 有权
标题翻译：用于接收数字信号的装置
公开(公告)号：US08897410B2
公开(公告)日：2014-11-25
申请号：US13590278
申请日：2012-08-21
申请人： Pascal Cadic
发明人： Pascal Cadic
IPC分类号： H04L7/00 , H04L7/04
CPC分类号： H04L7/0079 , H04L7/042 , H04L7/046
摘要： The present invention concerns the field of digital signal receivers provided with means of synchronisation with the transmitter and more particularly digital synchronisation means. The invention describes a synchronisation method solely based on the measurement of the frame time and the bit time in accumulators. These measurements are used to adjust the sampling clock of the receiver.
摘要翻译：本发明涉及提供有与发射机同步的装置的数字信号接收机的领域，更具体地说是数字同步装置。本发明仅在累加器中基于帧时间和比特时间的测量来描述同步方法。这些测量用于调整接收机的采样时钟。

6. 发明授权

US08855249B2 Preamble detection at low signal-to-noise levels 有权
标题翻译：低信噪比下的前导码检测
公开(公告)号：US08855249B2
公开(公告)日：2014-10-07
申请号：US13331303
申请日：2011-12-20
申请人： Jozsef G. Nemeth
发明人： Jozsef G. Nemeth
IPC分类号： H03D1/00 , H04B1/7077 , H04L7/04
CPC分类号： H04B1/7077 , H04L7/046
摘要： A preamble detector has a correlator outputting for every sample position of the preamble part of an incoming sampled signal stream a score and associated class value; and a multiple cluster unit receiving the class and score output values from the correlator, wherein a first cluster receives output values from the correlator and the following clusters are coupled in series such that each cluster receives output values from the correlator and a preceding cluster and wherein the output values of the correlator and a cluster are processed such that an n-th cluster of the multiple cluster unit, with n>1, accumulates the highest score values of n score values with matching class values.
摘要翻译：前导码检测器具有相关器，用于对输入的采样信号流的前导码部分的每个采样位置输出一个分数和相关联的类值; 以及多个集群单元，从所述相关器接收所述类别和得分输出值，其中第一集群从所述相关器接收输出值，并且所述后续集群被串联耦合，使得每个集群从所述相关器和先前集群接收输出值，并且其中处理相关器和群集的输出值，使得具有n> 1的多个簇单元的第n个群集累积具有匹配类值的n个得分值的最高得分值。

7. 发明授权

US08607088B2 Synchronizing remote devices with synchronization sequence on JTAG control lead 有权
标题翻译：在JTAG控制引线上同步具有同步序列的远程设备
公开(公告)号：US08607088B2
公开(公告)日：2013-12-10
申请号：US13226058
申请日：2011-09-06
申请人： Gary L. Swoboda
发明人： Gary L. Swoboda
IPC分类号： G06F1/04
CPC分类号： G01R31/3177 , G01R31/317 , G06F1/12 , G06F1/3206 , G06F11/221 , G06F11/2284 , G06F11/267 , H04L7/046
摘要： A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.
摘要翻译：一种方法包括一种系统，该系统包括耦合到根据主机设备和所有远程设备在系统操作期间跟随的状态图主动操作的第一远程设备的主机设备。该方法还包括在主机设备和第一远程设备根据状态图主动操作时加电第二远程设备。第二个远程设备确定是初始化为标准协议还是高级协议。当确定初始化为高级协议时，第二远程设备然后等待同步点序列。

8. 发明申请

US20130243107A1 BAUD RATE TIMING RECOVERY FOR NYQUIST PATTERNS IN A COMMUNICATION SYSTEM 审中-公开
标题翻译：通信系统中NYQUIC模式的波特率时间恢复
公开(公告)号：US20130243107A1
公开(公告)日：2013-09-19
申请号：US13422259
申请日：2012-03-16
申请人： Erik V. Chmelar , Choshu Ito
发明人： Erik V. Chmelar , Choshu Ito
IPC分类号： H04L27/06 , H04L27/04
CPC分类号： H04L7/033 , H04L7/046 , H04L25/03057
摘要： Described embodiments recover timing data from a received signal. An analog-to-digital converter (ADC) generates a value for each sample of the signal at a sample phase. A phase detector selects a window of n received bit samples, where n is a positive integer. If the bit window includes any Nyquist patterns, the phase detector enables a bang-bang trap. The bang-bang-trap iteratively, for each bit transition between a first consecutive bit and a second consecutive bit in the Nyquist patterns, samples the received signal at a zero crossing between the first and second consecutive bits and determines the polarity of the bit transition. Based on the polarity of the bit transition and the sample value at the zero crossing, the bang-bang trap determines whether the sample phase of the bit sample for the second consecutive bit is correct. If the sample phase is incorrect, the bang-bang trap adjusts the sample phase.
摘要翻译：所描述的实施例从接收到的信号中恢复定时数据。模拟数字转换器（ADC）在样本阶段产生每个信号样本的值。相位检测器选择n个接收位样本的窗口，其中n是正整数。如果位窗口包括任何奈奎斯特图案，则相位检测器能够进行爆炸陷阱。迭代地，对于奈奎斯特图案中的第一连续位和第二连续位之间的每个位转换，对第一和第二连续位之间的零交叉处的接收信号进行采样，并确定位转换的极性。基于位过渡的极性和过零点处的采样值，爆炸阱确定第二个连续位的位采样的采样相位是否正确。如果样品相不正确，则爆炸阱会调整样品相。

9. 发明授权

US08458505B2 Adapter and scan test logic synchronizing from idle state 有权
标题翻译：适配器和扫描测试逻辑从空闲状态同步
公开(公告)号：US08458505B2
公开(公告)日：2013-06-04
申请号：US13489641
申请日：2012-06-06
申请人： Gary L. Swoboda
发明人： Gary L. Swoboda
IPC分类号： G06F1/04
CPC分类号： G01R31/3177 , G01R31/317 , G06F1/12 , G06F1/3206 , G06F11/221 , G06F11/2284 , G06F11/267 , H04L7/046
摘要： A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.
摘要翻译：一种方法包括一种系统，该系统包括耦合到根据主机设备和所有远程设备在系统操作期间跟随的状态图主动操作的第一远程设备的主机设备。该方法还包括在主机设备和第一远程设备根据状态图主动操作时加电第二远程设备。第二个远程设备等待同步点序列。在检测到同步点序列时，第二远程设备实现预定的特征集并将其自身与公共点处的状态图同步为主机设备和第一远程设备。

10. 发明授权

US08416903B1 Signal edge detection circuitry and methods 有权
标题翻译：信号边缘检测电路和方法
公开(公告)号：US08416903B1
公开(公告)日：2013-04-09
申请号：US13097252
申请日：2011-04-29
申请人： John Oh , Samson Tam , Curt Wortman , Jean Luc Berube
发明人： John Oh , Samson Tam , Curt Wortman , Jean Luc Berube
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03K5/1534 , H03K5/26 , H03M9/00 , H04L7/0037 , H04L7/046
摘要： Double data rate (“DDR”) circuitry or the like is modified or enhanced to include edge detection capability. During edge detection mode the circuitry is supplied with serial training data that includes successive pairs of equal-valued bits. Several, differently-phased, candidate clock signals are used one after another in order of increasing phase to clock the DDR circuitry. Adjacent bits in the training data that should be equal-valued are captured by the DDR circuitry and compared. Any candidate clock signal that causes the bits thus compared to be unequal is flagged as having phase close to edges in the data. The approximate phase of data edges is thereby indicated by the phase (or phases) of the candidate clock signal (or signals) causing the bits compared as described above to be unequal.
摘要翻译：双数据速率（DDR）电路等被修改或增强以包括边缘检测能力。在边缘检测模式期间，电路被提供有包括连续的等位位对的串行训练数据。多个不同阶段的候选时钟信号按照逐渐增加的相位顺序逐个使用以对DDR电路进行时钟。训练数据中相邻位应该是等值的由DDR电路捕获并进行比较。导致这样比较的位不相等的任何候选时钟信号被标记为具有接近数据边缘的相位。因此，数据边缘的大致相位由候选时钟信号（或信号）的相位（或相位）指示，使得如上所述比较的比特不相等。

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