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51. 发明授权

US09019787B2 Semiconductor device having hierarchical bit line structure 有权
标题翻译：具有分层位线结构的半导体器件
公开(公告)号：US09019787B2
公开(公告)日：2015-04-28
申请号：US13888707
申请日：2013-05-07
申请人： PS4 Luxco S.A.R.L.
发明人： Yasuhiro Matsumoto , Noriaki Mochida , Takeshi Ohgami , Daiki Izawa
IPC分类号： G11C7/00 , G11C5/06 , G11C11/4074 , G11C11/4094 , G11C11/4097 , G11C11/4099 , G11C7/18 , G11C29/00 , G11C29/06 , G11C29/12
CPC分类号： G11C5/063 , G11C7/18 , G11C11/4074 , G11C11/4094 , G11C11/4097 , G11C11/4099 , G11C29/006 , G11C29/06 , G11C2029/1204
摘要： A semiconductor device having hierarchical bit lines is disclosed, which comprises: a first global bit line; first and second local bit lines coupled in common to the first global bit line; first and second power lines; a first transistor coupled between the first local bit line and the first power line; a second transistor coupled between the second local bit line and the second power line; a third transistor coupled between the first and second power lines.
摘要翻译：公开了一种具有分层位线的半导体器件，其包括：第一全局位线; 第一和第二局部位线共同耦合到第一全局位线; 第一和第二电力线; 耦合在第一局部位线和第一电源线之间的第一晶体管; 耦合在所述第二局部位线和所述第二电源线之间的第二晶体管; 耦合在第一和第二电力线之间的第三晶体管。

52. 发明授权

US09001563B2 Semiconductor device and driving method thereof 有权
标题翻译：半导体装置及其驱动方法
公开(公告)号：US09001563B2
公开(公告)日：2015-04-07
申请号：US13455188
申请日：2012-04-25
申请人： Tomoaki Atsumi , Yoshiya Takewaki
发明人： Tomoaki Atsumi , Yoshiya Takewaki
IPC分类号： G11C11/24 , G11C11/404 , G11C11/401 , G11C11/4099 , H01L27/12 , H01L27/108
CPC分类号： G11C5/10 , G11C11/401 , G11C11/404 , G11C11/406 , G11C11/4091 , G11C11/4099 , H01L27/10873 , H01L27/10897 , H01L27/1218 , H01L27/1225
摘要： In a memory module including a memory cell array including memory cells arranged in matrix, each including a first transistor using an oxide semiconductor and a first capacitor; a reference cell including a p-channel third transistor, a second capacitor, and a second transistor using an oxide semiconductor; and a refresh timing detection circuit including a resistor and a comparator, wherein when a potential is supplied to the first capacitor through the first transistor, a potential is supplied to the second capacitor through the second transistor, wherein a drain current value of the third transistor is changed in accordance with the potential stored in the second capacitor, and wherein when the drain current value of the third transistor is higher than a given value, a refresh operation of the memory cell array and the reference cell are performed.
摘要翻译：在包括具有排列成矩阵的存储单元的存储单元阵列的存储器模块中，每个存储单元包括使用氧化物半导体的第一晶体管和第一电容器; 包括p沟道第三晶体管，第二电容器和使用氧化物半导体的第二晶体管的参考单元; 以及包括电阻器和比较器的刷新定时检测电路，其中当通过第一晶体管向第一电容器提供电位时，通过第二晶体管将电位提供给第二电容器，其中第三晶体管的漏极电流值根据存储在第二电容器中的电位而改变，并且当第三晶体管的漏极电流值高于给定值时，执行存储单元阵列和参考单元的刷新操作。

53. 发明申请

US20050278592A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20050278592A1
公开(公告)日：2005-12-15
申请号：US11002894
申请日：2004-12-03
申请人： Shinichi Yamada , Waichiro Fujieda , Shinichiroh Ikemasu
发明人： Shinichi Yamada , Waichiro Fujieda , Shinichiroh Ikemasu
IPC分类号： G01R31/28 , G11C5/00 , G11C7/02 , G11C7/14 , G11C11/401 , G11C11/4099 , G11C29/00 , G11C29/06 , G11C29/24
CPC分类号： G11C7/14 , G11C11/401 , G11C11/4099 , G11C29/24 , G11C29/50 , G11C2029/5006
摘要： First dummy memory cells connected to a first dummy signal line have the same shape and characteristics as those of a real memory cell. The first dummy memory cells are arranged to be adjacent to outermost real memory cells. A voltage setting circuit changes the voltage of the first dummy signal line from a first voltage to a second voltage in order to write test data onto the first dummy memory cell during a test mode. By writing data of a logic opposite to that of the test data onto the real memory cell adjacent to the first dummy memory cell by means of an operation control circuit, a leak failure that may occur between the first dummy memory cell and the real memory cell adjacent thereto can be checked.
摘要翻译：连接到第一虚拟信号线的第一虚拟存储器单元具有与实际存储单元相同的形状和特性。第一虚拟存储器单元布置成与最外面的真实存储单元相邻。电压设定电路将第一虚拟信号线的电压从第一电压改变为第二电压，以便在测试模式期间将测试数据写入第一虚拟存储器单元。通过使用操作控制电路将与测试数据的逻辑相反的逻辑的数据写入与第一虚拟存储单元相邻的实际存储单元上，可能发生在第一虚拟存储单元和实际存储单元之间的泄漏故障可以检查相邻的位置。

54. 发明申请

US20050249020A1 Multi-port memory device 有权
标题翻译：多端口存储设备
公开(公告)号：US20050249020A1
公开(公告)日：2005-11-10
申请号：US10877888
申请日：2004-06-25
申请人： Kyung-Whan Kim , Il-Ho Lee , Jae-Jin Lee
发明人： Kyung-Whan Kim , Il-Ho Lee , Jae-Jin Lee
IPC分类号： G11C11/407 , G11C5/06 , G11C7/10 , G11C8/00 , G11C8/16 , G11C11/401 , G11C11/409 , G11C11/4096 , G11C11/4099
CPC分类号： G11C11/4099 , G11C5/063 , G11C7/1048 , G11C7/1075 , G11C8/16 , G11C11/4096 , G11C2207/2227
摘要： A multi-port memory device capable of preventing the first high data failure at an initial data transmission on a global data bus line according to the present invention includes: a global data bus line including a plurality of bus lines; a plurality of data transmitting and receiving unit including transmitters/receivers, which use a current sensing, for exchanging data into the global data bus line, wherein the receiver in the data transmitting and receiving unit includes resistors for dividing a voltage level; and a variable reference voltage generator for generating reference voltage levels as a receiver reference voltage, by controlling the resistance of the resistors in the receiver, wherein the variable reference voltage generator generates a first reference voltage level in an active mode and generates a second reference voltage level in a standby mode and wherein the first reference voltage level is higher than the second reference voltage level.
摘要翻译：根据本发明的能够防止在全局数据总线上的初始数据传输时的第一高数据故障的多端口存储器件包括：包括多条总线的全局数据总线; 多个数据发送和接收单元，包括使用电流检测的发送器/接收器，用于将数据交换到全局数据总线中，其中数据发送和接收单元中的接收器包括用于分压电压电平的电阻器; 以及可变参考电压发生器，用于通过控制接收器中的电阻器的电阻来产生参考电压电平作为接收器参考电压，其中可变参考电压发生器在激活模式下产生第一参考电压电平并产生第二参考电压电平处于待机模式，并且其中第一参考电压电平高于第二参考电压电平。

55. 发明授权

US06912150B2 Reference current generator, and method of programming, adjusting and/or operating same 有权
公开(公告)号：US06912150B2
公开(公告)日：2005-06-28
申请号：US10840902
申请日：2004-05-07
申请人： Lionel Portman , Maher Kayal , Marc Pastre , Marija Blagojevic , Michel Declercq
发明人： Lionel Portman , Maher Kayal , Marc Pastre , Marija Blagojevic , Michel Declercq
IPC分类号： G11C7/14 , G11C11/4099 , G11C16/28 , G11C29/02 , G11C11/24
CPC分类号： G11C29/028 , G11C7/14 , G11C11/401 , G11C11/4099 , G11C16/28 , G11C29/02 , G11C29/12005 , G11C2029/5006 , G11C2211/4016
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is a technique and circuitry for reading data that is stored in memory cells. In one embodiment of this aspect, the present invention is a technique and circuitry for generating a reference current that is used, in conjunction with a sense amplifier, to read data that is stored in memory cells of a DRAM device. The technique and circuitry for generating a reference current may be implemented using an analog configuration, a digital configuration, and/or combinations of analog and digital configurations.

56. 发明授权

US06847540B2 Semiconductor memory device and control method thereof 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US06847540B2
公开(公告)日：2005-01-25
申请号：US10404153
申请日：2003-04-02
申请人： Yoshiharu Kato , Satoru Kawamoto
发明人： Yoshiharu Kato , Satoru Kawamoto
IPC分类号： G11C11/404 , G11C7/14 , G11C7/22 , G11C11/34 , G11C11/407 , G11C11/4074 , G11C11/4076 , G11C11/4099 , H01L21/8242 , H01L27/108 , G11C11/24
CPC分类号： G11C7/227 , G11C7/14 , G11C7/22 , G11C11/4074 , G11C11/4076 , G11C11/4099
摘要： A semiconductor memory device, in which a cell plate potential does not fluctuate even when the device state is changed from a state without stored charge in all charge storage nodes of the cell capacitors at power-on to an access operation state, comprises NMOS transistors M1 to Mk for connecting a line VPR as a feeder for a reference voltage VPR from a reference voltage generation circuit with a line VCP as a feeder for a reference voltage VCP from the reference voltage generation circuit in each of cell blocks B1 to Bk. Gate terminals of the NMOS transistors M1 to Mk are connected to a common signal φCPR. The signal φCPR outputs a positive logical level at a predetermined time after power-on. By providing the NMOS transistors M1 to Mk for short-circuiting the line VPR with the line VCP in each of the cell blocks B1 to Bk, both lines are short-circuited in each of the cell blocks B1 to Bk.
摘要翻译：即使当器件状态从电源电容器的所有电荷存储节点中的没有存储电荷的状态改变到接通操作状态时，单元板电位也不波动的半导体存储器件包括NMOS晶体管M1 到Mk，用于将来自参考电压生成电路的参考电压VPR的线路VPR作为用于参考电压VCP的馈线（用于参考电压VCP的馈线）的每个单元块B1至Bk中的参考电压产生电路连接。 NMOS晶体管M1至Mk的栅极端子连接到公共信号phiCPR。信号phiCPR在上电之后的预定时间输出正逻辑电平。通过在每个单元块B1至Bk中设置用于使线VPR与线VCP短路的NMOS晶体管M1至Mk，在每个单元块B1至Bk中两条线都短路。

57. 发明授权

US5831895A Dynamic cell plate sensing and equilibration in a memory device 失效
公开(公告)号：US5831895A
公开(公告)日：1998-11-03
申请号：US903541
申请日：1997-07-30
申请人： Troy A. Manning
发明人： Troy A. Manning
IPC分类号： G11C7/06 , G11C7/14 , G11C11/4074 , G11C11/4091 , G11C11/4099 , G11C11/24
CPC分类号： G11C11/4091 , G11C11/4074 , G11C11/4099 , G11C7/06 , G11C7/14
摘要： A memory device is described which uses dynamic digitline sensing where separate plate lines are provided for each digitline of a memory cell array. A voltage of the plate line is dynamic in that it changes during read operations to create a larger differential for sensing stored data. A method is described which uses either an inactive digitline or a simulation circuit to perform an equilibration operation. Thus, the memory uses an inactive digitline for equilibration which is not necessary for data sensing.

58. 发明授权

US5828609A Simulated DRAM memory bit line/bit line for circuit timing and voltage level tracking 失效
标题翻译：模拟DRAM存储器位线/位线用于电路定时和电压电平跟踪
公开(公告)号：US5828609A
公开(公告)日：1998-10-27
申请号：US760125
申请日：1996-12-03
申请人： Li-Chun Li , Lawrence C. Liu , Michael A. Murray
发明人： Li-Chun Li , Lawrence C. Liu , Michael A. Murray
IPC分类号： G11C7/06 , G11C11/4091 , G11C11/4099 , G11C7/00
CPC分类号： G11C11/4099 , G11C11/4091 , G11C7/065
摘要： The voltages on the high voltage rails of sense amplifiers in dynamic random access memories are controlled during turn-on of the sense amplifiers to remain approximately at the voltage of the voltage source internal to the integrated circuit chip by connecting a voltage source external to the chip to the high voltage rails until the voltages on the rails equal the voltage from the chip's internal voltage source at which time the external voltage source is disconnected.
摘要翻译：在感测放大器的导通期间，动态随机存取存储器中的高电压轨上的电压被控制，以通过连接芯片外部的电压源将其保持在集成电路芯片内部的电压源的大致电压直到电源轨上的电压等于芯片内部电压源的电压，此时外部电压源断开。

59. 发明授权

US5652728A Dynamic memory 失效
标题翻译：动态内存
公开(公告)号：US5652728A
公开(公告)日：1997-07-29
申请号：US524930
申请日：1995-09-08
申请人： Shiro Hosotani , Minobu Yazawa , Kazuya Yamanaka
发明人： Shiro Hosotani , Minobu Yazawa , Kazuya Yamanaka
IPC分类号： G11C11/405 , G11C7/00 , G11C11/401 , G11C11/4099
CPC分类号： G11C11/4099
摘要： Dummy information of a third level, which is between first and second levels written in a plurality of memory cells, is written in a dummy memory cell from a source node through transistors. Thus, a potential difference is caused between a read bit line and a dummy read bit line in reading. A potential comparison circuit indicates the level of information read from any memory cell on the basis of the comparison result as to the potentials of the dummy read bit line and the read bit line. Thus, the read rate is increased, the read operation is stabilized and increase of the chip area is suppressed.
摘要翻译：写入多个存储单元的第一级和第二级之间的第三级的虚拟信息通过晶体管从源节点写入虚拟存储单元。因此，读取中的读取位线和虚拟读取位线之间产生电位差。潜在的比较电路根据关于虚拟读取位线和读取位线的电位的比较结果来指示从任何存储器单元读取的信息的电平。因此，读取速率增加，读取操作稳定，并且抑制了芯片面积的增加。

60. 发明授权

US5553027A Integrated semiconductor memory circuit and method for its operation 失效
标题翻译：集成半导体存储器电路及其操作方法
公开(公告)号：US5553027A
公开(公告)日：1996-09-03
申请号：US371829
申请日：1995-01-12
申请人： Thomas von der Ropp
发明人： Thomas von der Ropp
IPC分类号： G11C11/401 , G11C11/4099 , G11C7/00
CPC分类号： G11C11/4099
摘要： An integrated semiconductor memory circuit includes devices through which second electrodes of memory capacitors of dummy memory cells are to be acted upon with a precharging potential. The precharging potential has a value being 5 to 35% greater than a value of a bit line potential to which bit lines of the semiconductor memory circuit are to be precharged. A method for operating an integrated semiconductor memory circuit includes precharging the bit lines to the bit line potential, prior to a readout of data stored in memory cells, and applying the precharging potential to the second electrodes of the memory capacitors of the dummy memory cells, in the precharging of the bit lines.
摘要翻译：集成半导体存储器电路包括将以预充电电位对虚拟存储器单元的存储电容器的第二电极进行操作的器件。预充电电位的值比半导体存储器电路的位线被预充电的位线电位的值大5〜35％。一种用于操作集成半导体存储器电路的方法包括在读出存储在存储单元中的数据之前将位线预先充电到位线电位，以及将预充电电位施加到虚拟存储单元的存储电容器的第二电极，在预充电的位线。

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