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51. 发明申请

US20100078681A1 Integrated Circuit Including a Hetero-Interface and Self Adjusted Diffusion Method for Manufacturing the Same 失效
标题翻译：包含异构界面和自调制扩散方法的集成电路制造相同
公开(公告)号：US20100078681A1
公开(公告)日：2010-04-01
申请号：US12242137
申请日：2008-09-30
申请人： Henning Riechert , Walter Michael Weber
发明人： Henning Riechert , Walter Michael Weber
IPC分类号： H01L21/337 , H01L29/80
CPC分类号： H01L29/0665 , B82Y10/00 , H01L27/108 , H01L27/10852 , H01L27/10876 , H01L28/40 , H01L29/0673 , H01L29/165 , H01L29/267 , H01L29/42392 , H01L29/66825 , H01L29/7827 , H01L29/78642 , H01L29/78681 , H01L29/78687 , H01L29/78696 , H01L29/7881
摘要： An integrated circuit including a hetero-interface and a manufacturing method thereof is disclosed. One embodiment includes forming a hetero-structure including a hetero-interface at a junction between a first region and a second region, and, thereafter introducing a material into the first region and at least up to the hetero-interface, wherein a diffusion constant of the material is higher in the first region than in the second region.
摘要翻译：公开了一种包括异质界面的集成电路及其制造方法。一个实施方案包括在第一区域和第二区域之间的连接处形成包括异质界面的异质结构，然后将材料引入第一区域并且至少直到异质界面，其中扩散常数该材料在第一区域比在第二区域高。

52. 发明授权

US07687336B2 Method of manufacturing a MOSFET structure 失效
标题翻译：制造MOSFET结构的方法
公开(公告)号：US07687336B2
公开(公告)日：2010-03-30
申请号：US12058507
申请日：2008-03-28
申请人： James D. Beasom
发明人： James D. Beasom
IPC分类号： H01L21/337
CPC分类号： H01L29/0847 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/402 , H01L29/66659 , H01L29/735 , H01L29/7835 , H01L29/8611 , H01L2924/0002 , H03K17/941 , H01L2924/00
摘要： A method of forming a MOSFET is provided. The method comprises forming a relatively thin layer of dielectric on a substrate. Depositing a gate material layer on the relatively thin layer of dielectric. Removing portions of the gate material layer to form a first and second gate material regions of predetermined lateral lengths. Introducing a first conductivity type dopant in the substrate to form a top gate using first edges of the first and second gate material regions as masks, Introducing a second conductivity dopant of high dopant density in the substrate to form a drain region adjacent the surface of the substrate using a second edge of the second gate material region as a mask to form a first edge of the drain region, wherein a spaced distance between the top gate and the drain region is determined by the lateral length of the second gate material region.
摘要翻译：提供一种形成MOSFET的方法。该方法包括在衬底上形成相当薄的电介质层。在较薄的电介质层上沉积栅极材料层。去除栅极材料层的部分以形成具有预定横向长度的第一和第二栅极材料区域。在衬底中引入第一导电型掺杂剂，以使用第一和第二栅极材料区域的第一边缘作为掩模形成顶栅极;在衬底中引入高掺杂物密度的第二导电掺杂剂，以形成邻近使用第二栅极材料区域的第二边缘作为掩模以形成漏极区域的第一边缘的衬底，其中顶部栅极和漏极区域之间的间隔距离由第二栅极材料区域的横向长度确定。

53. 发明授权

US07645654B2 JFET with built in back gate in either SOI or bulk silicon 失效
标题翻译： JFET内置在SOI或体硅中的背栅
公开(公告)号：US07645654B2
公开(公告)日：2010-01-12
申请号：US12270964
申请日：2008-11-14
申请人： Madhukar B. Vora
发明人： Madhukar B. Vora
IPC分类号： H01L21/337
CPC分类号： H01L29/42316 , H01L29/1066 , H01L29/66901 , H01L29/808
摘要： A process for manufacturing a Junction Field-Effect Transistor, comprises doping a semiconductor material formed on an insulating substrate with impurities of a first conductivity type to form a well region. The process continues by implanting impurities of a second conductivity type into said well region to form a channel region, and by implanting impurities of the first conductivity type in said well region to form a back gate region. The process continues by forming a trench to expose at least one sidewall of said channel region, wherein the trench extends far enough along the sidewall to expose at least a portion of said back gate region. The process continues by depositing polysilicon to fill said trench along the at least one sidewall of said channel region and at least a portion of said back gate region, wherein at least a portion of the polysilicon will form a gate contact. The polysilicon is then doped with impurities of a first conductivity type. The process concludes by annealing the polysilicon to activate the doped impurities and to cause the doped impurities to diffuse along the at least one sidewall of said channel region so as to form a top gate region. The top gate region extends far enough to make electrical contact with said back gate region.
摘要翻译：一种用于制造结型场效应晶体管的工艺，包括用绝缘衬底上形成的具有第一导电类型杂质的半导体材料掺杂以形成阱区。该过程通过将第二导电类型的杂质注入到所述阱区中以形成沟道区，并且通过在所述阱区中注入第一导电类型的杂质以形成背栅区而继续。该过程通过形成沟槽以暴露所述沟道区域的至少一个侧壁而继续，其中沟槽沿着侧壁延伸足够远以露出所述背栅区域的至少一部分。该过程通过沉积多晶硅来沿着所述沟道区的至少一个侧壁和所述背栅区的至少一部分沉积多晶硅，其中多晶硅的至少一部分将形成栅极接触。然后，多晶硅掺杂有第一导电类型的杂质。该过程通过退火多晶硅来终止激活掺杂杂质并使掺杂的杂质沿着所述沟道区的至少一个侧壁扩散，从而形成顶栅区。顶栅区延伸得足够远以与所述背栅区电接触。

54. 发明授权

US07645651B2 LDMOS with channel stress 有权
标题翻译： LDMOS具有通道压力
公开(公告)号：US07645651B2
公开(公告)日：2010-01-12
申请号：US11951702
申请日：2007-12-06
申请人： Xiaoqiu Huang , Veeraraghavan Dhandapani , Bich-Yen Nguyen , Amanda M. Kroll , Daniel T. Pham
发明人： Xiaoqiu Huang , Veeraraghavan Dhandapani , Bich-Yen Nguyen , Amanda M. Kroll , Daniel T. Pham
IPC分类号： H01L21/00 , H01L21/84 , H01L21/337 , H01L21/8238 , H01L21/8236 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66659 , H01L29/7781
摘要： A method of forming a metal oxide semiconductor (MOS) device comprises defining an active area in an unstrained semiconductor layer structure, depositing a hard mask overlying the active area and a region outside of the active area, patterning the hard mask to expose the active area, selectively growing a strained semiconductor layer overlying the exposed active area, and forming a remainder of the MOS device. The active area includes a first doped region of first conductivity type and a second doped region of second conductivity type. The strained semiconductor layer provides a biaxially strained channel for the MOS device. During a portion of forming the remainder of the MOS device, dopant of the first conductivity type of the first doped region of the active area and dopant of the second conductivity type of the second doped region of the active area diffuses into overlying portions of the strained semiconductor layer to create a correspondingly doped strained semiconductor layer, thereby providing corresponding doping for the biaxially strained channel.
摘要翻译：一种形成金属氧化物半导体（MOS）器件的方法包括：在非限制性半导体层结构中限定有源区，沉积覆盖有源区的硬掩模和有源区外的区域，使硬掩模图形化以暴露有源区选择性地生长覆盖暴露的有源区的应变半导体层，以及形成MOS器件的其余部分。有源区包括第一导电类型的第一掺杂区和第二导电类型的第二掺杂区。应变半导体层为MOS器件提供双向应变通道。在形成MOS器件的其余部分的部分期间，有源区的第一掺杂区的第一导电类型的掺杂剂和有源区的第二掺杂区的第二导电类型的掺杂剂扩散到应变的上覆部分以产生相应掺杂的应变半导体层，从而为双轴应变通道提供相应的掺杂。

55. 发明授权

US07615425B2 Open source/drain junction field effect transistor 有权
标题翻译：开路/漏极结场效应晶体管
公开(公告)号：US07615425B2
公开(公告)日：2009-11-10
申请号：US11504412
申请日：2006-08-15
申请人： Joe R. Trogolo , Hiroshi Yasuda , Badih El-Kareh , Philipp Steinmann
发明人： Joe R. Trogolo , Hiroshi Yasuda , Badih El-Kareh , Philipp Steinmann
IPC分类号： H01L21/337
CPC分类号： H01L29/808 , H01L29/0607 , H01L29/66901
摘要： The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET) with an open drain, where the open drain allows the transistors to operate at higher voltages before experiencing gate leakage current. The open drain allows the voltage to be increased several fold without increasing the size of the transistors. Opening the drain essentially spreads equipotential lines of respective electric fields developed at the drains of the devices so that the local electric fields, and hence the impact ionization rates are reduced to redirect current below the surface of the transistors.
摘要翻译：本文的公开内容涉及具有开路漏极的n沟道结场效应晶体管（NJFET）和/或ap沟道结场效应晶体管（PJFET），其中开路漏极允许晶体管在经历栅极漏电流之前以更高的电压工作。开路漏极允许电压增加几倍，而不增加晶体管的尺寸。开放漏极基本上扩散了在器件的漏极处产生的相应电场的等势线，使得局部电场以及因此的冲击电离率被降低以将电流重新导向晶体管表面以下。

56. 发明授权

US07534670B2 Semiconductor device and manufacturing method of the same 有权
公开(公告)号：US07534670B2
公开(公告)日：2009-05-19
申请号：US11148288
申请日：2005-06-09
申请人： Osamu Nakamura , Masayuki Kajiwara , Shunpei Yamazaki , Hideto Ohnuma
发明人： Osamu Nakamura , Masayuki Kajiwara , Shunpei Yamazaki , Hideto Ohnuma
IPC分类号： H01L21/337
CPC分类号： H01L29/78675 , H01L21/3221 , H01L27/12 , H01L27/1277 , H01L29/32 , H01L29/42384 , H01L29/4908 , H01L29/66757 , H01L29/78663
摘要： Provided is a technique of effectively removing a metallic element that has catalytic action in terms of the crystallization of a semiconductor film and remains in a semiconductor film obtained using the metallic element. With the technique of the present invention, to remove a catalytic element used to crystallize a semiconductor film having an amorphous structure, gettering is completed by forming a region or a semiconductor film, to which a rare gas element is added, and by having the catalytic element move to the formed region or semiconductor film.

57. 发明申请

US20090101941A1 WRAPPED GATE JUNCTION FIELD EFFECT TRANSISTOR 有权
标题翻译：封装栅极连接场效应晶体管
公开(公告)号：US20090101941A1
公开(公告)日：2009-04-23
申请号：US11875190
申请日：2007-10-19
申请人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
发明人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/808 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/20 , H01L29/22 , H01L29/66901 , H01L29/66924
摘要： A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second conductivity type doping, which is the opposite of the first conductivity doping. Further, the at least one semiconductor channel vertically abuts a top gate region and at least one bottom gate region, both having the second conductivity type doping. The gate electrode, which comprises side gate region, the top gate region, and at least one bottom gate regions, wraps around each of the at least one semiconductor channel to provide tight control of the current, i.e., a low off-current, through the at least one semiconductor channel. By employing multiple channels, the JFET may provide a high on-current.
摘要翻译：提供具有至少一个具有第一导电类型掺杂的半导体沟道的封装的栅极结场效应晶体管（JFET）。所述至少一个半导体通道中的每一个的两个侧壁横向邻接具有第二导电类型掺杂的侧栅极区域，其与第一导电掺杂相反。此外，至少一个半导体沟道垂直邻接顶部栅极区域和至少一个具有第二导电类型掺杂的底部栅极区域。包括侧栅极区域的栅极电极，顶栅极区域和至少一个底栅极区域围绕至少一个半导体通道中的每一个环绕，以提供电流的严格控制，即，低截止电流，通过所述至少一个半导体通道。通过采用多个通道，JFET可以提供高导通电流。

58. 发明授权

US07510925B2 Method of manufacturing semiconductor device, and semiconductor device 有权
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：US07510925B2
公开(公告)日：2009-03-31
申请号：US11739792
申请日：2007-04-25
申请人： Yuki Miyanami
发明人： Yuki Miyanami
IPC分类号： H01L21/337 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/7834 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method of manufacturing a semiconductor device includes: the first step of forming a gate electrode over a silicon substrate, with a gate insulating film; and the second step of digging down a surface layer of the silicon substrate by etching conducted with the gate electrode as a mask. The method of manufacturing the semiconductor device further includes the third step of epitaxially growing, on the surface of the dug-down portion of the silicon substrate, a mixed crystal layer including silicon and atoms different in lattice constant from silicon so that the mixed crystal layer contains an impurity with such a concentration gradient that the impurity concentration increases along the direction from the silicon substrate side toward the surface of the mixed crystal layer.
摘要翻译：一种制造半导体器件的方法包括：第一步骤，在栅极绝缘膜上形成在硅衬底上的栅电极; 以及通过用栅电极作为掩模进行的蚀刻来挖掘硅衬底的表面层的第二步骤。制造半导体器件的方法还包括在硅衬底的下陷部分的表面上外延生长包含硅和晶格常数不同于硅的原子的混合晶体层的第三步骤，使得混合晶体层含有这样的浓度梯度的杂质，杂质浓度沿着从硅衬底侧朝向混晶层的表面的方向增加。

59. 发明申请

US20090075435A1 JFET With Built In Back Gate in Either SOI or Bulk Silicon 失效
标题翻译：具有内置背栅的JFET或SOI
公开(公告)号：US20090075435A1
公开(公告)日：2009-03-19
申请号：US12270964
申请日：2008-11-14
申请人： Madhukar B. Vora
发明人： Madhukar B. Vora
IPC分类号： H01L21/337
CPC分类号： H01L29/42316 , H01L29/1066 , H01L29/66901 , H01L29/808
摘要： A process for manufacturing a Junction Field-Effect Transistor, comprises doping a semiconductor material formed on an insulating substrate with impurities of a first conductivity type to form a well region. The process continues by implanting impurities of a second conductivity type into said well region to form a channel region, and by implanting impurities of the first conductivity type in said well region to form a back gate region. The process continues by forming a trench to expose at least one sidewall of said channel region, wherein the trench extends far enough along the sidewall to expose at least a portion of said back gate region. The process continues by depositing polysilicon to fill said trench along the at least one sidewall of said channel region and at least a portion of said back gate region, wherein at least a portion of the polysilicon will form a gate contact. The polysilicon is then doped with impurities of a first conductivity type. The process concludes by annealing the polysilicon to activate the doped impurities and to cause the doped impurities to diffuse along the at least one sidewall of said channel region so as to form a top gate region. The top gate region extends far enough to make electrical contact with said back gate region.
摘要翻译：一种用于制造结型场效应晶体管的工艺，包括用绝缘衬底上形成的具有第一导电类型杂质的半导体材料掺杂以形成阱区。该过程通过将第二导电类型的杂质注入到所述阱区中以形成沟道区，并且通过在所述阱区中注入第一导电类型的杂质以形成背栅区而继续。该过程通过形成沟槽以暴露所述沟道区域的至少一个侧壁而继续，其中沟槽沿着侧壁延伸足够远以露出所述背栅区域的至少一部分。该过程通过沉积多晶硅以沿着所述沟道区的至少一个侧壁和所述背栅区的至少一部分沉积所述沟槽继续，其中多晶硅的至少一部分将形成栅极接触。然后，多晶硅掺杂有第一导电类型的杂质。该过程通过退火多晶硅来终止激活掺杂杂质并使掺杂的杂质沿着所述沟道区的至少一个侧壁扩散，从而形成顶栅区。顶栅区延伸得足够远以与所述背栅区电接触。

60. 发明申请

US20090026501A1 ENHANCEMENT - DEPLETION SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING IT 审中-公开
标题翻译：增强型半导体结构及其制造方法
公开(公告)号：US20090026501A1
公开(公告)日：2009-01-29
申请号：US11722208
申请日：2005-12-13
申请人： Hassan Maher , Pierre Baudet
发明人： Hassan Maher , Pierre Baudet
IPC分类号： H01L21/337 , H01L29/778
CPC分类号： H01L27/095 , H01L27/0605 , H01L27/0883 , H01L29/7783
摘要： A ED-HEMT structure includes a buffer layer (4) including a doped layer (18), a channel layer (6), a barrier layer (8), and a second doped layer (20). An enhancement mode HEMT gate (12) is formed in a via extending through the second doped layer (20) and a depletion mode HEMT structure is formed over the second doped layer (20). The layer sequence allows the formation of both enhancement and depletion mode HEMTs in the same structure with good properties.
摘要翻译： ED-HEMT结构包括包括掺杂层（18），沟道层（6），势垒层（8）和第二掺杂层（20）的缓冲层（4）。增强型HEMT栅极（12）形成在延伸穿过第二掺杂层（20）的通孔中，并且在第二掺杂层（20）上形成耗尽型HEMT结构。层序列允许在相同结构中形成具有良好性质的增强和耗尽型HEMT。

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