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51. 发明授权

US09029962B1 Molded cavity substrate MEMS package fabrication method and structure 有权
标题翻译：成型腔基板MEMS封装制造方法和结构
公开(公告)号：US09029962B1
公开(公告)日：2015-05-12
申请号：US13272096
申请日：2011-10-12
申请人： Mahmoud Dreiza , Andrew Ballantine , Russell Scott Shumway
发明人： Mahmoud Dreiza , Andrew Ballantine , Russell Scott Shumway
IPC分类号： H01L21/00 , H01L27/04
CPC分类号： B81B7/007 , B81B2201/0257 , B81B2207/07 , B81B2207/095 , B81B2207/096 , B81C1/00301 , H01L24/29 , H01L24/48 , H01L24/49 , H01L24/97 , H01L27/04 , H01L2224/05554 , H01L2224/2919 , H01L2224/32225 , H01L2224/48111 , H01L2224/48137 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/10155 , H01L2924/1461 , H01L2924/15151 , H01L2924/16151 , H01L2924/16195 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/05599 , H01L2924/00012
摘要： A molded ring includes a molded cavity of a molded cavity substrate MEMS package. The molded ring is formed by molding a dielectric material directly upon a substrate. As molding is a relatively simple and low cost process, the molded ring and thus molded cavity are formed at a minimal cost. This, in turn, minimizes the cost of the molded cavity substrate MEMS package.
摘要翻译：模制环包括模制空腔衬底MEMS封装的模制腔。模制环通过将介电材料直接模制在基底上而形成。由于成型是相对简单和低成本的工艺，所以以最小的成本形成模制环和因此模制的空腔。这又降低了模制空腔衬底MEMS封装的成本。

52. 发明授权

US09029750B1 CMOS and CCD sensor R/O with high gain and no kTC noise 有权
标题翻译： CMOS和CCD传感器R / O具有高增益和无kTC噪声
公开(公告)号：US09029750B1
公开(公告)日：2015-05-12
申请号：US13196603
申请日：2011-08-02
申请人： Nathan Bluzer
发明人： Nathan Bluzer
IPC分类号： H01L27/04 , H01L29/78 , H01L27/02
CPC分类号： H01L27/04 , H01L27/0251 , H01L27/14603 , H01L27/14612 , H01L27/14812 , H04N5/363
摘要： A high sensitivity, high speed, and low noise, semiconductor non-destructive read-out (NDRO) device (700) for the conversion of a generated signal charge (110) into an output voltage having provisions for charge integration, charge transfer, and nondestructive charge read-out without kTC reset noise. The read-out device (700) includes charge sensing potential wells (520), a MOSFET having a gate (705), a source (145), and a drain (720), a feedback amplifier (305), a current generator (310), a reset gate (650), a reset drain (530), a multiplexer gate (820), and a pair of adjacent CCD transfer gates (750 and 760). CMOS detector pixels with this NDRO form a compact structure for integrating generated charge, and high sensitivity readout, without kTC reset noise. The NDRO in CCD devices provides a fast sensitive charge to voltage transducer without kTC reset noise. Connecting several NDRO stages in series (1000) provides multiple readout of a pixel to further improve sensitivity and performance of charge to voltage transduction.
摘要翻译：用于将产生的信号电荷（110）转换成具有用于电荷积分，电荷转移以及电荷积分的输出电压的高灵敏度，高灵敏度和低噪声半导体非破坏性读出（NDRO）器件（700）非破坏性电荷读出，无kTC复位噪声。读出装置（700）包括电荷感测势阱（520），具有栅极（705），源极（145）和漏极（720）的MOSFET，反馈放大器（305），电流发生器 310），复位栅极（650），复位漏极（530），多路复用器门（820）和一对相邻的CCD传输门（750和760）。具有这种NDRO的CMOS检测器像素形成了紧凑的结构，用于集成生成的电荷和高灵敏度读出，而没有kTC复位噪声。 CCD器件中的NDRO为电压传感器提供快速敏感的电荷，无需kTC复位噪声。串联连接多个NDRO级（1000）可提供多个像素读数，以进一步提高电压对电压传导的灵敏度和性能。

53. 发明授权

US08975726B2 POP structures and methods of forming the same 有权
标题翻译： POP结构及其形成方法
公开(公告)号：US08975726B2
公开(公告)日：2015-03-10
申请号：US13649941
申请日：2012-10-11
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hsu-Hsien Chen , Chih-Hua Chen , En-Hsiang Yeh , Monsen Liu , Chen-Shien Chen
IPC分类号： H01L27/04
CPC分类号： H01L21/76885 , H01L21/568 , H01L21/6835 , H01L23/5389 , H01L24/19 , H01L24/83 , H01L24/97 , H01L25/03 , H01L25/105 , H01L25/16 , H01L2221/68327 , H01L2221/6834 , H01L2221/68372 , H01L2224/12105 , H01L2224/16225 , H01L2224/73267 , H01L2224/97 , H01L2225/1035 , H01L2225/1058 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2224/82 , H01L2224/81 , H01L2924/00
摘要： A device includes a top package bonded to a bottom package. The bottom package includes a molding material, a device die molded in the molding material, a Through Assembly Via (TAV) penetrating through the molding material, and a redistribution line over the device die. The top package includes a discrete passive device packaged therein. The discrete passive device is electrically coupled to the redistribution line.
摘要翻译：一种装置包括结合到底部包装的顶部包装。底部包装包括模制材料，在模制材料中模制的模具，穿透模制材料的穿孔组件（TAV）以及穿过模具的再分配线。顶部封装包括封装在其中的分立无源器件。分立无源器件电耦合到再分配线。

54. 发明授权

US08946816B2 High frequency switching MOSFETs with low output capacitance using a depletable P-shield 有权
标题翻译：具有低输出电容的高频开关MOSFET，采用可消耗P型屏蔽
公开(公告)号：US08946816B2
公开(公告)日：2015-02-03
申请号：US14270228
申请日：2014-05-05
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Madhur Bobde , Hamza Yilmaz , Sik Lui , Daniel Ng
IPC分类号： H01L29/76 , H01L29/78 , H01L27/04 , H01L29/66 , H01L29/06 , H01L29/10 , H01L21/225 , H01L29/417 , H01L29/423 , H01L29/45
CPC分类号： H01L29/7813 , H01L21/2257 , H01L27/0251 , H01L27/04 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/456 , H01L29/47 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7808 , H01L29/7811
摘要： Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：本公开的方面描述了具有自对准源触点的高密度沟槽基功率MOSFET和用于制造这种器件的方法。源触点与间隔物自对准，并且有源器件可以具有两步栅极氧化物。下部可以具有比栅极氧化物的上部的厚度大的厚度。 MOSFET也可以在衬底的下部包括可消除的屏蔽。可消除的屏蔽可以被配置成使得在高排水偏压期间，屏蔽件基本上消耗掉。要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

55. 发明授权

US08912449B2 Thermal warp compensation IC package 有权
标题翻译：热翘曲补偿IC封装
公开(公告)号：US08912449B2
公开(公告)日：2014-12-16
申请号：US13728168
申请日：2012-12-27
申请人： Paul James Brown , Alex L. Chan
发明人： Paul James Brown , Alex L. Chan
IPC分类号： H05K1/03 , H05K1/00 , H05K7/20 , H01L21/58 , H01L27/04 , H01L23/498
CPC分类号： H01L27/04 , H01L23/49816 , H01L23/49822 , H01L24/80 , H01L2924/14 , H01L2924/15311 , H01L2924/3511 , H01L2924/00
摘要： An apparatus and method for temperature induced warpage compensation in an integrated circuit package is disclosed. The apparatus consists of bonded layers of material having different thermal coefficients of expansion. The bonded layers are bonded to the top of the integrated circuit package. By appropriate choice of temperature coefficients the layers of material can compensate for either convex or concave warpage. In some embodiments, the layers of material have apertures therein allowing compensation for more complex warpages. As well, in some embodiments the top layer of material does not have a planar cross-section. A method is also disclosed for manufacturing an integrated circuit package assembly. The apparatus and method provide an alternative to methods of dealing with IC package warpage known in the art.
摘要翻译：公开了一种用于集成电路封装中的温度诱导翘曲补偿的装置和方法。该装置由具有不同热膨胀系数的材料的粘合层组成。接合层结合到集成电路封装的顶部。通过温度系数的适当选择，材料层可以补偿凸起或凹形翘曲。在一些实施例中，材料层具有孔，其中允许补偿更复杂的翘曲。同样，在一些实施例中，顶层材料不具有平面横截面。还公开了一种用于制造集成电路封装组件的方法。该装置和方法提供了处理本领域已知的IC封装翘曲的方法的替代方案。

56. 发明授权

US08890284B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08890284B2
公开(公告)日：2014-11-18
申请号：US13774541
申请日：2013-02-22
申请人： Infineon Technologies AG
发明人： Thomas Kilger , Ulrich Wachter , Dominic Maier , Gottfried Beer
IPC分类号： H01L29/00 , H01L49/02 , H01L23/538 , H01L21/82 , H01L27/04
CPC分类号： H01L21/561 , H01L21/568 , H01L21/78 , H01L21/82 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/5384 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/25 , H01L24/82 , H01L25/50 , H01L27/04 , H01L28/00 , H01L2224/04105 , H01L2224/12105 , H01L2224/16145 , H01L2224/16225 , H01L2224/24137 , H01L2224/2518 , H01L2224/73267 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/1461 , H01L2924/15311 , H01L2924/19105 , H01L2924/00
摘要： A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.
摘要翻译：多个半导体芯片各自包括与第一主面相对的第一主面和第二主面。在半导体芯片的第二主面上施加第一封装层。在第一半导体芯片的第一主面上施加电布线层。将第二封装层施加在电布线层上。第一封装层的厚度和第一半导体芯片的厚度减小。可以将该结构单个化以获得多个半导体器件。

57. 发明授权

US08890276B2 Three-dimensional integrated structure capable of detecting a temperature rise 有权
标题翻译：能够检测温升的三维一体化结构
公开(公告)号：US08890276B2
公开(公告)日：2014-11-18
申请号：US13934683
申请日：2013-07-03
申请人： STMicroelectronics (Crolles 2) SAS
发明人： Laurent-Luc Chapelon
IPC分类号： H01L31/058 , H01L27/04 , H01L21/66 , G01K5/56 , H01L23/00
CPC分类号： H01L27/04 , G01K5/56 , H01L22/34 , H01L24/05 , H01L24/08 , H01L24/80 , H01L2224/05546 , H01L2224/05547 , H01L2224/05571 , H01L2224/0603 , H01L2224/06102 , H01L2224/08057 , H01L2224/08111 , H01L2224/08121 , H01L2224/08147 , H01L2224/80012 , H01L2224/80097 , H01L2224/80141 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/80986 , H01L2924/00014 , H01L2224/05552
摘要： A three-dimensional integrated structure is formed from a first integrated circuit with a first cavity filled with a first conductive material and a second integrated circuit with a second cavity filled with a second conductive material, the second cavity facing the first cavity. The filled first cavity forms a first element and the filled second cavity forms a second element, the first and second elements separated from each other by a cavity. The first and second conductive materials have different thermal expansion coefficients. A contact detection circuit is electrically connected to the filled first and second cavities, and is operable to sense electrical contact between the first and second conductive materials in response to a change in temperature.
摘要翻译：三维集成结构由具有填充有第一导电材料的第一空腔的第一集成电路和具有填充有第二导电材料的第二空腔的第二集成电路形成，第二空腔面对第一空腔。填充的第一空腔形成第一元件，并且填充的第二空腔形成第二元件，第一元件和第二元件通过空腔彼此分离。第一和第二导电材料具有不同的热膨胀系数。接触检测电路电连接到填充的第一和第二空腔，并且可操作以响应于温度变化来感测第一和第二导电材料之间的电接触。

58. 发明授权

US08890106B2 Hybrid circuit of nitride-based transistor and memristor 有权
标题翻译：氮化物晶体管和忆阻器的混合电路
公开(公告)号：US08890106B2
公开(公告)日：2014-11-18
申请号：US13718689
申请日：2012-12-18
申请人： Hewlett-Packard Development Company, L.P.
发明人： Jianhua Yang , Gilberto Medeiros Ribeiro , Byung-Joon Choi , Stanley Williams
IPC分类号： H01L29/02 , H01L27/04 , H01L21/77
CPC分类号： H01L21/77 , G11C13/0007 , G11C13/003 , G11C2213/32 , G11C2213/34 , G11C2213/79 , H01L27/0605 , H01L27/0738 , H01L27/2436 , H01L29/2003 , H01L29/7787 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/16
摘要： A hybrid circuit comprises a nitride-based transistor portion and a memristor portion. The transistor includes a source and a drain and a gate for controlling conductance of a channel region between the source and the drain. The memristor includes a first electrode and a second electrode separated by an active switching region. The source or drain of the transistor forms one of the electrodes of the memristor.
摘要翻译：混合电路包括氮化物基晶体管部分和忆阻器部分。晶体管包括源极和漏极以及用于控制源极和漏极之间的沟道区域的电导的栅极。忆阻器包括由有源开关区域分开的第一电极和第二电极。晶体管的源极或漏极形成忆阻器的电极之一。

59. 发明授权

US08836047B2 Reducing defect rate during deposition of a channel semiconductor alloy into an in situ recessed active region 有权
标题翻译：在将沟道半导体合金沉积到原位凹入的有源区域中降低缺陷率
公开(公告)号：US08836047B2
公开(公告)日：2014-09-16
申请号：US13421394
申请日：2012-03-15
申请人： Stephan-Detlef Kronholz , Peter Javorka , Maciej Wiatr
发明人： Stephan-Detlef Kronholz , Peter Javorka , Maciej Wiatr
IPC分类号： H01L27/04 , H01L21/8238 , H01L21/84 , H01L21/8234 , H01L21/762 , H01L27/12
CPC分类号： H01L21/84 , H01L21/76283 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： When forming sophisticated high-k metal gate electrode structures on the basis of a threshold voltage adjusting semiconductor alloy, a highly efficient in situ process technique may be applied in order to form a recess in dedicated active regions and refilling the recess with a semiconductor alloy. In order to reduce or avoid etch-related irregularities during the recessing of the active regions, the degree of aluminum contamination during the previous processing, in particular during the formation of the trench isolation regions, may be controlled.
摘要翻译：当基于阈值电压调节半导体合金形成复杂的高k金属栅电极结构时，可以应用高效的原位工艺技术，以便在专用有源区域中形成凹槽并用半导体合金再填充凹槽。为了在活性区域的凹陷期间减少或避免蚀刻相关的不规则性，可以控制在先前处理期间，特别是在形成沟槽隔离区域期间的铝污染程度。

60. 发明授权

US08835977B2 TVS with low capacitance and forward voltage drop with depleted SCR as steering diode 有权
标题翻译： TVS具有低电容和正向压降，耗尽SCR作为转向二极管
公开(公告)号：US08835977B2
公开(公告)日：2014-09-16
申请号：US13720140
申请日：2012-12-19
申请人： Madhur Bobde , Lingpeng Guan , Anup Bhalla , Limin Weng
发明人： Madhur Bobde , Lingpeng Guan , Anup Bhalla , Limin Weng
IPC分类号： H01L29/866 , H01L27/04 , H01L27/02 , H01L27/08
CPC分类号： H01L27/0259 , H01L27/0255 , H01L27/0262 , H01L27/0814 , H01L29/866 , H01L29/87
摘要： A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further includes a region above the buried dopant region further comprising a top dopant layer of a second conductivity type and a top contact region of a second conductivity type which act in combination with the epitaxial layer and the buried dopant region to form a plurality of interfacing PN junctions constituting a SCR acting as a steering diode to function with the Zener diode for suppressing a transient voltage.
摘要翻译：一种设置在第一导电类型的半导体衬底上的瞬态电压抑制（TVS）器件。 TVS包括第二导电类型的掩埋掺杂区域，其被布置和包围在第一导电类型的外延层中，其中掩埋掺杂剂区域横向延伸并且具有与外延层的下面部分接合的延伸的底部接合区域，从而构成用于TVS器件的齐纳二极管。 TVS器件还包括掩埋掺杂剂区域上方的区域，还包括第二导电类型的顶部掺杂剂层和第二导电类型的顶部接触区域，其与外延层和掩埋掺杂剂区域结合起来以形成多个连接构成SCR作为转向二极管的PN结与用于抑制瞬态电压的齐纳二极管起作用的PN结。

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