专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10896968B2 Device structure and manufacturing method using HDP deposited source-body implant block 有权
公开(公告)号：US10896968B2
公开(公告)日：2021-01-19
申请号：US15499487
申请日：2017-04-27
申请人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K. Lui
发明人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K. Lui
IPC分类号： H01L29/423 , H01L29/06 , H01L29/40
摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

2. 发明申请

US20170148910A1 TERMINATION DESIGN FOR HIGH VOLTAGE DEVICE 审中-公开
公开(公告)号：US20170148910A1
公开(公告)日：2017-05-25
申请号：US15425235
申请日：2017-02-06
申请人： Lingpeng Guan , Anup Bhalla , Hamza Yilmaz
发明人： Lingpeng Guan , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/78 , H01L29/40 , H01L29/10 , H01L29/66 , H01L29/06
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0623 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/404 , H01L29/407 , H01L29/66712 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

3. 发明授权

US09620498B2 Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection 有权
公开(公告)号：US09620498B2
公开(公告)日：2017-04-11
申请号：US14341789
申请日：2014-07-26
申请人： Yi Su , Anup Bhalla , Daniel Ng
发明人： Yi Su , Anup Bhalla , Daniel Ng
IPC分类号： H01L27/02 , H01L27/06
CPC分类号： H01L27/0255 , H01L27/0629
摘要： A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped-well that is disposed below and engulfing the U-shaped bend.

4. 发明授权

US09324858B2 Trench-gated MIS devices 有权
标题翻译：沟通门槛MIS设备
公开(公告)号：US09324858B2
公开(公告)日：2016-04-26
申请号：US12917378
申请日：2010-11-01
申请人： Anup Bhalla , Dorman Pitzer , Jacek Korec , Xiaorong Shi , Sik Lui
发明人： Anup Bhalla , Dorman Pitzer , Jacek Korec , Xiaorong Shi , Sik Lui
IPC分类号： H01L29/76 , H01L29/78 , H01L21/8234 , H01L27/088 , H01L29/423 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/872
CPC分类号： H01L29/7813 , H01L21/823487 , H01L27/088 , H01L29/0661 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/66734 , H01L29/7803 , H01L29/7804 , H01L29/7806 , H01L29/7811 , H01L29/8725 , H01L2924/0002 , Y10S257/905 , H01L2924/00
摘要： In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.
摘要翻译：在沟槽栅极MIS器件中，沟槽内的栅极接触，从而不需要使栅极材料（通常为多晶硅）延伸到沟槽外部。这避免了沟槽上角处的应力问题。栅极金属和多晶硅之间的接触通常在位于器件的有源区域之外的栅极金属区域中形成。描述了用于形成栅极金属和多晶硅之间的接触的各种构造，包括其中沟槽在接触区域中变宽的实施例。由于在整个器件中多晶硅被回蚀到硅的顶表面之下，通常不需要多晶硅掩模，从而节省制造成本。

5. 发明申请

US20160027771A1 CONFIGURATION OF GATE TO DRAIN (GD) CLAMP AND ESD PROTECTION CIRCUIT FOR POWER DEVICE BREAKDOWN PROTECTION 审中-公开
标题翻译：闸门配置（GD）钳位和防静电保护电路，用于电源设备断开保护
公开(公告)号：US20160027771A1
公开(公告)日：2016-01-28
申请号：US14341789
申请日：2014-07-26
申请人： Yi Su , Anup Bhalla , Daniel Ng
发明人： Yi Su , Anup Bhalla , Daniel Ng
IPC分类号： H01L27/02 , H01L27/06
CPC分类号： H01L27/0255 , H01L27/0629
摘要： A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped-well that is disposed below and engulfing the U-shaped bend.
摘要翻译：一种半导体功率器件，其被支撑在半导体衬底上，该半导体衬底包括多个晶体管单元，每个晶体管单元具有源极和漏极，栅极用于控制在源极和漏极之间传输的电流。半导体还包括在栅极和漏极之间串联连接的栅极 - 漏极（GD）钳位端接器，还包括串联连接到硅二极管的多个背对背多晶硅二极管，包括半导体中的并行掺杂的列衬底，其中平行掺杂的柱具有预定的间隙。掺杂的柱还包括U形弯曲柱，其将平行掺杂的柱的端部连接在一起，深深的掺杂阱被设置在U形弯曲部的下方并且被吞噬。

6. 发明申请

US20160005809A1 CONFIGURATION AND METHOD TO GENERATE SADDLE JUNCTION ELECTRIC FIELD IN EDGE TERMINATION 审中-公开
公开(公告)号：US20160005809A1
公开(公告)日：2016-01-07
申请号：US14298537
申请日：2014-06-06
申请人： Madhur Bobde , Lingpeng Guan , Anup Bhalla , Hamza Yilmaz
发明人： Madhur Bobde , Lingpeng Guan , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/06 , H01L21/761
CPC分类号： H01L29/0634 , H01L21/26513 , H01L21/761 , H01L29/0615 , H01L29/0619 , H01L29/6609 , H01L29/861
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.

7. 发明授权

US09231050B1 Configuration and method to generate saddle junction electric field in edge termination 有权
公开(公告)号：US09231050B1
公开(公告)日：2016-01-05
申请号：US14298537
申请日：2014-06-06
申请人： Madhur Bobde , Lingping Guan , Anup Bhalla , Hamza Yilmaz
发明人： Madhur Bobde , Lingping Guan , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L27/088 , H01L29/06 , H01L21/761
CPC分类号： H01L29/0634 , H01L21/26513 , H01L21/761 , H01L29/0615 , H01L29/0619 , H01L29/6609 , H01L29/861
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.

8. 发明授权

US09059147B1 Junction barrier schottky (JBS) with floating islands 有权
标题翻译：交界面肖特基（JBS）与浮岛
公开(公告)号：US09059147B1
公开(公告)日：2015-06-16
申请号：US14222614
申请日：2014-03-22
申请人： Ji Pan , Anup Bhalla
发明人： Ji Pan , Anup Bhalla
IPC分类号： H01L29/47 , H01L29/872 , H01L29/78
CPC分类号： H01L29/47 , H01L29/0619 , H01L29/0623 , H01L29/0649 , H01L29/66143 , H01L29/7811 , H01L29/872
摘要： A Schottky diode includes a Schottky barrier and a plurality of dopant regions disposed near the Schottky barrier as floating islands to function as PN junctions for preventing a leakage current generated from a reverse voltage. At least a trench opened in a semiconductor substrate with a Schottky barrier material disposed therein constitutes the Schottky barrier. The Schottky barrier material may also be disposed on sidewalls of the trench for constituting the Schottky barrier. The trench may be filled with the Schottky barrier material composed of Ti/TiN or a tungsten metal disposed therein for constituting the Schottky barrier. The trench is opened in a N-type semiconductor substrate and the dopant regions includes P-doped regions disposed under the trench constitute the floating islands. The P-doped floating islands may be formed as vertical arrays under the bottom of the trench.
摘要翻译：肖特基二极管包括肖特基势垒和设置在肖特基势垒附近的多个掺杂剂区域，作为浮岛，用作用于防止从反向电压产生的漏电流的PN结。在其中设置有肖特基势垒材料的半导体衬底中开放的至少一个沟槽构成肖特基势垒。肖特基势垒材料也可以设置在用于构成肖特基势垒的沟槽的侧壁上。沟槽可以填充由设置在其中的用于构成肖特基势垒的Ti / TiN或其中的钨金属组成的肖特基势垒材料。沟槽在N型半导体衬底中打开，并且掺杂区包括设置在沟槽下方的P掺杂区构成浮岛。 P掺杂的浮岛可以在沟槽底部形成为垂直阵列。

9. 发明授权

US09024378B2 Device structure and manufacturing method using HDP deposited source-body implant block 有权
标题翻译：使用HDP沉积源体植入块的装置结构和制造方法
公开(公告)号：US09024378B2
公开(公告)日：2015-05-05
申请号：US13763644
申请日：2013-02-09
申请人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K Lui
发明人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K Lui
IPC分类号： H01L29/78 , H01L21/265 , H01L29/66
CPC分类号： H01L29/7827 , H01L21/265 , H01L21/2652 , H01L21/26586 , H01L21/266 , H01L29/0619 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813
摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
摘要翻译：本发明公开了一种半导体功率器件。沟槽半导体功率器件包括从半导体衬底的顶表面开口的沟槽栅极，被包围在设置在衬底底表面上的漏区以上的顶表面附近的体区中的源极区围绕。所述半导体功率器件还包括植入离子块，所述植入离子块设置在所述身体区域旁边的台面区域的上表面上，所述植入离子块具有基本上大于0.3微米的厚度，用于阻挡体注入离子和源离子进入台面区域从而可以减少用于制造半导体功率器件的掩模。

10. 发明授权

US08878292B2 Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method 有权
标题翻译：自对准开槽积分型场效应晶体管（AccuFET）结构及方法
公开(公告)号：US08878292B2
公开(公告)日：2014-11-04
申请号：US12074280
申请日：2008-03-02
申请人： François Hébert , Madhur Bobde , Anup Bhalla
发明人： François Hébert , Madhur Bobde , Anup Bhalla
IPC分类号： H01L29/739
CPC分类号： H01L29/7828 , H01L29/0619 , H01L29/0623 , H01L29/0847 , H01L29/41766 , H01L29/456 , H01L29/66666
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体功率器件。半导体功率器件包括沟槽栅极，每个沟槽栅极具有在由侧壁间隔物围绕的半导体衬底的顶表面之上延伸的伸出栅极段。半导体功率器件还包括与基本上平行于沟槽栅极的侧壁间隔开的开口的槽。粘贴门区段还包括由侧壁间隔物围绕的绝缘材料构成的盖。阻挡金属层覆盖盖的顶表面并且覆盖在侧壁间隔物上并在槽的顶表面上方延伸。这些槽填充有与栅极段相同的栅极材料，用作附加栅电极，用于提供向沟槽栅极延伸的耗尽层，借此栅极与沟槽栅极之间的漂移区域完全耗尽栅极 - 漏极电压Vgs = 0伏。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式