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51. 发明授权

US08748940B1 Semiconductor devices with germanium-rich active layers and doped transition layers 有权
标题翻译：具有富锗有源层和掺杂过渡层的半导体器件
公开(公告)号：US08748940B1
公开(公告)日：2014-06-10
申请号：US13717282
申请日：2012-12-17
申请人： Willy Rachmady , Van H. Le , Ravi Pillarisetty , Jessica S. Kachian , Marc C. French , Aaron A. Budrevich
发明人： Willy Rachmady , Van H. Le , Ravi Pillarisetty , Jessica S. Kachian , Marc C. French , Aaron A. Budrevich
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L21/20 , H01L21/36 , H01L29/66 , H01L29/06 , C23F1/30
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02584 , H01L21/30604 , H01L21/30608 , H01L21/3065 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/167 , H01L29/365 , H01L29/42392 , H01L29/511 , H01L29/66439 , H01L29/66477 , H01L29/66628 , H01L29/66742 , H01L29/775 , H01L29/7781 , H01L29/78 , H01L29/7848 , H01L29/785 , H01L29/786 , H01L29/78696 , Y02E10/50
摘要： Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.
摘要翻译：在那里制造的半导体器件堆叠和器件具有富锗器件层。富锗器件层设置在衬底之上，其中设置有p型掺杂Ge蚀刻抑制层（例如，p型SiGe），以在去除牺牲半导体层期间抑制富锗器件层的蚀刻 Si比设备层更丰富。随着在半导体膜堆叠中引入掩埋的p型掺杂半导体层，可以显着降低Ge在湿蚀刻剂（例如氢氧化物水溶液）中的溶解速率，从而提高蚀刻剂对Ge富集器件层的选择性。

52. 发明授权

US08731344B2 Method for manufacturing semiconductor optical modulator and semiconductor optical modulator 有权
标题翻译：制造半导体光调制器和半导体光调制器的方法
公开(公告)号：US08731344B2
公开(公告)日：2014-05-20
申请号：US13478280
申请日：2012-05-23
申请人： Hideki Yagi
发明人： Hideki Yagi
IPC分类号： G02B6/12 , G02B6/10 , G02F1/015 , H01L21/302 , B29D11/00 , B23B9/04 , H01L21/36
CPC分类号： G02F1/025 , G02F1/2257 , G02F2201/066
摘要： A method for manufacturing a semiconductor optical modulator includes forming a p-type semiconductor layer on a main surface of a p-type semiconductor substrate; forming a pair of stripe-shaped masks on the p-type semiconductor layer, the stripe-shaped masks extending in a first direction along the main surface of the p-type semiconductor substrate and being spaced apart from each other; simultaneously forming a hole and a pair of stripe structures extending in the first direction by etching the p-type semiconductor layer through the stripe-shaped masks, the pair of stripe structures defining the hole; after removing the stripe-shaped masks, forming a buried layer in the hole; forming a core layer on the buried layer and the stripe structures; and forming an upper cladding layer on the core layer. The buried layer is made of a semiconductor material with a lower optical absorption loss than that of the p-type semiconductor layer.
摘要翻译：一种制造半导体光调制器的方法包括在p型半导体衬底的主表面上形成p型半导体层; 在p型半导体层上形成一对条形掩模，所述条形掩模沿着所述p型半导体衬底的主表面沿第一方向延伸并且彼此间隔开; 同时形成通过蚀刻p型半导体层通过条形掩模在第一方向延伸的孔和一对条纹结构，所述一对条纹结构限定该孔; 在去除条形掩模之后，在孔中形成掩埋层; 在掩埋层和条纹结构上形成核心层; 以及在所述芯层上形成上包层。埋层由具有比p型半导体层低的光吸收损耗的半导体材料制成。

53. 发明授权

US08703551B2 Process flow to reduce hole defects in P-active regions and to reduce across-wafer threshold voltage scatter 有权
标题翻译：工艺流程可以减少P-活性区域中的空穴缺陷并减少跨晶圆阈值电压的散射
公开(公告)号：US08703551B2
公开(公告)日：2014-04-22
申请号：US13102680
申请日：2011-05-06
申请人： Stephan Kronholz , Andreas Ott
发明人： Stephan Kronholz , Andreas Ott
IPC分类号： H01L21/00 , H01L21/84 , H01L21/8228 , H01L21/8238 , H01L21/20 , H01L21/36 , H01L21/302
CPC分类号： H01L21/30608 , H01L21/823412 , H01L21/823807 , H01L21/84
摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises performing at least one etching process to reduce a thickness of a P-active region of a semiconducting substrate to thereby define a recessed P-active region, performing a process in a process chamber to selectively form an as-deposited layer of a semiconductor material on the recessed P-active region, wherein the step of performing the at least one etching process is performed outside of the process chamber, and performing an etching process in the process chamber to reduce a thickness of the as-deposited layer of semiconductor material.
摘要翻译：本文公开了形成半导体器件的方法。在一个示例中，该方法包括执行至少一个蚀刻工艺以减小半导体衬底的P活性区域的厚度，从而限定凹陷的P活性区域，在处理室中执行选择性地形成在凹陷的P活性区域上形成半导体材料的沉积层，其中执行所述至少一个蚀刻工艺的步骤在所述处理室的外部进行，并且在所述处理室中进行蚀刻处理以减小所述至少一个蚀刻工艺的厚度，半导体材料的沉积层。

54. 发明授权

US08697547B2 Method for manufacturing silicon epitaxial wafer 有权
标题翻译：硅外延片的制造方法
公开(公告)号：US08697547B2
公开(公告)日：2014-04-15
申请号：US13510336
申请日：2010-11-11
申请人： Tomosuke Yoshida
发明人： Tomosuke Yoshida
IPC分类号： H01L21/322 , H01L21/36 , H01L21/20
CPC分类号： C30B25/20 , C30B25/10 , C30B29/06 , H01L21/02381 , H01L21/02532 , H01L21/0262
摘要： A method for manufacturing a silicon epitaxial wafer, including vapor-phase growing a silicon single crystal thin film on a silicon single crystal substrate in a hydrogen atmosphere while supplying a source gas; and cooling a silicon epitaxial wafer having the formed silicon single crystal thin film by calculating a temperature at which a standard value or a process average value of concentration of an evaluation target impurity present in the silicon single crystal thin film coincides with solubility limit concentration of the evaluation target impurity and setting a cooling rate of the silicon epitaxial wafer after the film formation to be less than 20° C./sec in a temperature range of at least plus or minus 50° C. from the calculated temperature.
摘要翻译：一种制造硅外延晶片的方法，包括在氢气气氛中在硅单晶衬底上气相生长硅单晶薄膜，同时供应源气体; 并且通过计算存在于硅单晶薄膜中的评价对象杂质的浓度的标准值或处理平均值与所述硅单晶薄膜的溶解度极限浓度一致的温度，在成膜后将硅外延晶片的冷却速度从计算出的温度在至少±50℃的温度范围内设定为小于20℃/秒。

55. 发明授权

US08648351B2 Epitaxial substrate and method for manufacturing epitaxial substrate 失效
标题翻译：外延衬底和外延衬底的制造方法
公开(公告)号：US08648351B2
公开(公告)日：2014-02-11
申请号：US13644651
申请日：2012-10-04
申请人： NGK Insulators, Ltd.
发明人： Makoto Miyoshi , Shigeaki Sumiya , Mikiya Ichimura , Sota Maehara , Mitsuhiro Tanaka
IPC分类号： H01L21/36 , H01L29/15
CPC分类号： H01L29/155 , C30B25/183 , C30B29/403 , H01L21/02381 , H01L21/02458 , H01L21/02494 , H01L21/02507 , H01L21/02516 , H01L21/0254 , H01L21/02609 , H01L21/0262 , H01L29/045 , H01L29/1075 , H01L29/2003 , H01L29/7786 , H01L29/872
摘要： Provided is a crack-free epitaxial substrate having excellent breakdown voltage properties in which a silicon substrate is used as a base substrate thereof. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer including a plurality of composition modulation layers each formed of a first composition layer made of AlN and a second composition layer made of AlxGa1-xN (0≦x x(n) is satisfied, where n represents the number of laminations of each of the first and the second composition layer, and x(i) represents the value of x in i-th one of the second composition layers as counted from the base substrate side. Each of the second composition layers is formed so as to be in a coherent state relative to the first composition layer.
摘要翻译：本发明提供一种无硅外延基板，其具有优良的击穿电压特性，其中使用硅基板作为其基底。外延衬底包括：（111）单晶Si衬底和包括多个组成调制层的缓冲层，每个组成调制层由由AlN制成的第一组成层和由Al x Ga 1-x N（0≤x<1）制成的第二组成层）交替层压。 x（1）> = x（2）> =的关系。。。满足= x（n-1）> = x（n）且x（1）> x（n），其中n表示第一和第二组合物层中的每一个的叠层数，x（i）表示从基底侧计数的第i组第2组合物层中的x的值。每个第二组合物层相对于第一组合物层形成为相干状态。

56. 发明授权

US08642453B2 Schottky barrier diode and method of forming a Schottky barrier diode 有权
标题翻译：肖特基势垒二极管和形成肖特基势垒二极管的方法
公开(公告)号：US08642453B2
公开(公告)日：2014-02-04
申请号：US13679357
申请日：2012-11-16
申请人： International Business Machines Corporation
发明人： Edward J. Nowak
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L29/872 , H01L29/66143
摘要： Disclosed is a silicon-on-insulator-based Schottky barrier diode with a low forward voltage that can be manufactured according to standard SOI process flow. An active silicon island is formed using an SOI wafer. One area of the island is heavily-doped with an n-type or p-type dopant, one area is lightly-doped with the same dopant, and an isolation structure is formed on the top surface above a junction between the two areas. A metal silicide region contacts the lightly-doped side of the island forming a Schottky barrier. Another discrete metal silicide region contacts the heavily-doped area of the island forming an electrode to the Schottky barrier (i.e., a Schottky barrier contact). The two metal silicide regions are isolated from each other by the isolation structure. Contacts to each of the discrete metal silicide regions allow a forward and/or a reverse bias to be applied to the Schottky barrier.
摘要翻译：公开了可以根据标准SOI工艺流程制造的具有低正向电压的基于硅绝缘体的肖特基势垒二极管。使用SOI晶片形成活性硅岛。该岛的一个区域被n型或p型掺杂物重掺杂，一个区域用相同的掺杂剂轻掺杂，并且在两个区域之间的结点上方的顶表面上形成隔离结构。金属硅化物区域接触形成肖特基势垒的岛的轻掺杂侧。另一个分立的金属硅化物区域接触形成与肖特基势垒（即，肖特基势垒接触）的电极的岛的重掺杂区域。两个金属硅化物区域通过隔离结构彼此隔离。与离散的金属硅化物区域中的每一个的接触允许将正向和/或反向偏压施加到肖特基势垒。

57. 发明授权

US08623747B1 Silicon, aluminum oxide, aluminum nitride template for optoelectronic and power devices 有权
标题翻译：硅，氧化铝，氮化铝模板用于光电和功率器件
公开(公告)号：US08623747B1
公开(公告)日：2014-01-07
申请号：US13717182
申请日：2012-12-17
申请人： Erdem Arkun , Michael Lebby , Andrew Clark
发明人： Erdem Arkun , Michael Lebby , Andrew Clark
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02381 , H01L21/02433 , H01L21/02488 , H01L21/0254 , H01L21/0262
摘要： A method of forming a template on a silicon substrate includes providing a single crystal silicon substrate. The method further includes forming an aluminum oxide coating on the surface of the silicon substrate, the aluminum oxide being substantially crystal lattice matched to the surface of the silicon substrate and epitaxially depositing a layer of aluminum nitride (AlN) on the aluminum oxide coating substantially crystal lattice matched to the surface of the aluminum nitride.
摘要翻译：在硅衬底上形成模板的方法包括提供单晶硅衬底。所述方法还包括在所述硅衬底的表面上形成氧化铝涂层，所述氧化铝与所述硅衬底的表面基本上晶格匹配并在所述氧化铝涂层上外延沉积氮化铝层（AlN）晶格与氮化铝的表面匹配。

58. 发明授权

US08617956B2 Method and structure for forming high-K/metal gate extremely thin semiconductor on insulator device 有权
公开(公告)号：US08617956B2
公开(公告)日：2013-12-31
申请号：US12859414
申请日：2010-08-19
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/78 , H01L21/36
CPC分类号： H01L29/0847 , H01L21/28114 , H01L29/165 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/78 , H01L29/7848
摘要： A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.

59. 发明授权

US08610119B2 Stability enhancements in metal oxide semiconductor thin film transistors 有权
标题翻译：金属氧化物半导体薄膜晶体管的稳定性增强
公开(公告)号：US08610119B2
公开(公告)日：2013-12-17
申请号：US13141118
申请日：2009-12-04
申请人： Steven D. Theiss , David H. Redinger
发明人： Steven D. Theiss , David H. Redinger
IPC分类号： H01L29/22 , H01L21/44 , H01L21/36
CPC分类号： H01L29/7869 , H01L29/4908 , H01L29/66969 , H01L29/78696
摘要： A plasma hydrogenated region in the dielectric layer of a semiconductor thin film transistor (TFT) structure improves the stability of the TFT. The TFT is a multilayer structure including an electrode, a dielectric layer disposed on the electrode, and a metal oxide semiconductor on the dielectric. Exposure of the dielectric layer to a hydrogen containing plasma prior to deposition of the semiconductor produces a plasma hydrogenated region at the semiconductor-dielectric interface. The plasma hydrogenated region incorporates hydrogen which decreases in concentration from semiconductor/dielectric interface into the bulk of one or both of the dielectric layer and the semiconductor layer.
摘要翻译：半导体薄膜晶体管（TFT）结构的电介质层中的等离子体氢化区域提高了TFT的稳定性。 TFT是包括电极，设置在电极上的电介质层和电介质上的金属氧化物半导体的多层结构。在沉积半导体之前，将介电层暴露于含氢等离子体在半导体介电界面处产生等离子体氢化区域。等离子体氢化区域包含从半导体/电介质界面到电介质层和半导体层中的一个或两个的本体的浓度降低的氢。

60. 发明申请

US20130316519A1 Techniques for Forming a Chalcogenide Thin Film Using Additive to a Liquid-Based Chalcogenide Precursor 审中-公开
标题翻译：用液态硫族化物前体添加剂形成硫族化物薄膜的技术
公开(公告)号：US20130316519A1
公开(公告)日：2013-11-28
申请号：US13479856
申请日：2012-05-24
申请人： David Brian Mitzi , Xiaofeng Qiu
发明人： David Brian Mitzi , Xiaofeng Qiu
IPC分类号： H01L21/36
CPC分类号： H01L21/02422 , H01L21/02425 , H01L21/02491 , H01L21/02557 , H01L21/0256 , H01L21/02568 , H01L21/02628 , H01L31/032
摘要： Techniques for enhancing energy conversion efficiency in chalcogenide-based photovoltaic devices by improved grain structure and film morphology through addition of urea into a liquid-based precursor are provided. In one aspect, a method of forming a chalcogenide film includes the following steps. Metal chalcogenides are contacted in a liquid medium to form a solution or a dispersion, wherein the metal chalcogenides include a Cu chalcogenide, an M1 and an M2 chalcogenide, and wherein M1 and M2 each include an element selected from the group consisting of: Ag, Mn, Mg, Fe, Co, Cd, Ni, Cr, Zn, Sn, In, Ga, Al, and Ge. At least one organic additive is contacted with the metal chalcogenides in the liquid medium. The solution or the dispersion is deposited onto a substrate to form a layer. The layer is annealed at a temperature, pressure and for a duration sufficient to form the chalcogenide film.
摘要翻译：提供了通过改进的颗粒结构和通过将尿素添加到基于液体的前体中的膜形态来提高硫族化物系光伏器件的能量转换效率的技术。一方面，形成硫族化物膜的方法包括以下步骤。金属硫族化物在液体介质中接触以形成溶液或分散体，其中金属硫族化物包括Cu硫族化物，M1和M2硫族化物，并且其中M1和M2各自包括选自以下的元素：Ag， Mn，Mg，Fe，Co，Cd，Ni，Cr，Zn，Sn，In，Ga，Al和Ge。至少一种有机添加剂与液体介质中的金属硫族化物接触。将溶液或分散体沉积在基底上以形成层。该层在温度，压力和足够长的时间内退火以形成硫族化物膜。

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