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61. 发明授权

US10230810B1 Storing packet data in mirror buffer 有权
公开(公告)号：US10230810B1
公开(公告)日：2019-03-12
申请号：US15161263
申请日：2016-05-22
申请人： Barefoot Networks, Inc.
发明人： Parag D. Bhide , Alain Loge , Chaitanya Kodeboyina , Anurag Agrawal
IPC分类号： H04L29/08 , H04L29/06
摘要： Some embodiments provide a method for a hardware forwarding element. Based on a set of characteristics of a packet, the method determines to copy a packet to a particular temporary storage of a set of temporary storages of the hardware forwarding element. Based on a property of the particular temporary storage, the method stores only a particular portion of the packet in the particular temporary storage. A same size portion of each packet copied to the particular temporary storage is stored in the particular temporary storage.

62. 发明申请

US20190058646A1 FAST DETECTION AND IDENTIFICATION OF LOST PACKETS 审中-公开
公开(公告)号：US20190058646A1
公开(公告)日：2019-02-21
申请号：US16108570
申请日：2018-08-22
申请人： Barefoot Networks, Inc.
发明人： Changhoon Kim , Minlan Yu , Yuliang Li
IPC分类号： H04L12/26
摘要： The invention provides a packet loss detection system that in near-real time detects packet loss and reports the identities of the lost packets. The identities of the lost packets are based on a set of packet-specific information that includes five-tuple flow information of the packet and other unique packet identifiers. A set of meters are placed at various vantage points in the network, each meter generates digests summarizing all the traffic passing through itself The digests are exported to a collector/analyzer, which decodes the digests and performs an analysis to detect packet losses and to determine the lost packets' identities. The collector compares between the traffic digests generated by all the meters surrounding the segment. Mismatches among the digests indicate packet losses. The collector restores the identifiers of the lost packets by further decoding the mismatches between the digests.

63. 发明申请

US20180337860A1 FAST ADJUSTING LOAD BALANCER 审中-公开
公开(公告)号：US20180337860A1
公开(公告)日：2018-11-22
申请号：US16049154
申请日：2018-07-30
申请人： Barefoot Networks, Inc.
发明人： Changhoon Kim , Patrick W. Bosshart
IPC分类号： H04L12/803 , H04L12/931 , H04L12/933 , H04L12/743 , H04L29/12
CPC分类号： H04L47/125 , H04L45/7453 , H04L49/10 , H04L49/354 , H04L61/20 , H04L61/2521
摘要： Some embodiments of the invention provide a load balancer for distributing packet flows that are addressed to a group of data compute nodes (DCNs) amongst the DCNs of the group. In some embodiments, the load balancer includes a connection data storage comprising several different destination network address translation (DNAT) tables. Each particular DNAT table is defined at a particular instance in time and stores the identity of a plurality DCNs that are part of the group at the particular instance in time. Each time a DCN is added to the group, the load balancer of some embodiments creates a new DNAT table in the connection data storage for processing new packet flows, while using previously created DNAT tables to process packets that are part of previously processed packet flows.

64. 发明授权

US10084687B1 Weighted-cost multi-pathing using range lookups 有权
公开(公告)号：US10084687B1
公开(公告)日：2018-09-25
申请号：US15382711
申请日：2016-12-18
申请人： Barefoot Networks, Inc.
发明人： Milad Sharif , Parag Bhide , Vasanth Kumar , Chaitanya Kodeboyina
IPC分类号： H04L12/50 , H04L12/729 , H04L12/707 , H04L12/751
CPC分类号： H04L45/125 , H04L45/02 , H04L45/24
摘要： A method of forwarding packets by a physical network switch is provided. The method assigns egress ports that connect the network switch to each particular next hop to a weighted-cost multipathing (WCMP) group associated with the particular next hop. The method assigns weights to each egress port in each WCMP group according to the capacity of each path that connects the egress port to the next hop associated with the WCMP group and normalizes the weights over a range of values. For each packet received at the network switch, the method identifies the WCMP group associated with a next hop destination of the packet. The method calculates a hash value of a set of fields in the packet header and uses the hash value to perform a range lookup in the identified WCMP group to select an egress port for forwarding the packet to the next hop.

65. 发明授权

US10078463B1 Dynamic memory reallocation for match-action packet processing 有权
公开(公告)号：US10078463B1
公开(公告)日：2018-09-18
申请号：US15784336
申请日：2017-10-16
申请人： Barefoot Networks, Inc.
发明人： Patrick Bosshart
IPC分类号： G06F12/00 , G06F3/06 , H04L12/741
CPC分类号： G06F3/0631 , H04L45/74
摘要： A pool of unit memories is provided in order to flexibly allocate memory capacity to implement various tables and/or logical memories such as those for implementing an OpenFlow switch. The pool is structured with routing resources for allowing flexible allocation and reallocation of memory capacity to the various tables. The unit memories and logical units in the pool are interconnected by a set of horizontal routing resources and a set of vertical routing resources.

66. 发明授权

US10050854B1 Packet generation-based bidirectional forwarding detection 有权
公开(公告)号：US10050854B1
公开(公告)日：2018-08-14
申请号：US15261941
申请日：2016-09-10
申请人： Barefoot Networks, Inc.
发明人： Steven Licking , Chaitanya Kodeboyina , Julianne Zhu , Changhoon Kim
IPC分类号： H04L12/26 , H04L12/935 , H04L12/743
摘要： A method of performing bidirectional forwarding detection (BFD) by a hardware forwarding element that includes a set of ingress pipelines and a set of egress pipelines. Each ingress pipeline includes a packet generator. A packet generator in a first pipeline periodically generates a pair of packets to monitor the health of a particular egress link. The pair includes a BFD transmit packet and a BFD dummy transmit packet. The method forwards each dummy BFD transmit packet to a first egress pipeline and increments a counter at the first egress pipeline. Each BFD packet is transmitted through the particular egress link to a network node. BFD packets received from the network node are forwarded to the first egress pipeline and the value of the counter is rest. The method marks the particular egress link as failed when the value of the counter exceeds a predetermined threshold.

67. 发明授权

US09880768B2 Dynamic memory reallocation for match-action packet processing 有权
公开(公告)号：US09880768B2
公开(公告)日：2018-01-30
申请号：US15007209
申请日：2016-01-27
申请人： Barefoot Networks, Inc.
发明人： Patrick Bosshart
IPC分类号： G06F12/00 , G06F3/06 , H04L12/741
CPC分类号： G06F3/0631 , H04L45/74
摘要： A pool of unit memories is provided in order to flexibly allocate memory capacity to implement various tables and/or logical memories such as those for implementing an OpenFlow switch. The pool is structured with routing resources for allowing flexible allocation and reallocation of memory capacity to the various tables. The unit memories and logical units in the pool are interconnected by a set of horizontal routing resources and a set of vertical routing resources.

68. 发明申请

US20170093987A1 DATA-PLANE STATEFUL PROCESSING UNITS IN PACKET PROCESSING PIPELINES 审中-公开
公开(公告)号：US20170093987A1
公开(公告)日：2017-03-30
申请号：US14864088
申请日：2015-09-24
申请人： Barefoot Networks, Inc.
发明人： Anirudh Sivaraman Kaushalram , Mihai Budiu , Changhoon Kim
IPC分类号： H04L29/08
摘要： A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.

69. 发明申请

US20160246535A1 Coding Scheme for Indirect Addressing of Multiple Action Memories 有权
标题翻译：多行动记忆的间接寻址编码方案
公开(公告)号：US20160246535A1
公开(公告)日：2016-08-25
申请号：US14968844
申请日：2015-12-14
申请人： Barefoot Networks, Inc.
发明人： Patrick Bosshart
IPC分类号： G06F3/06
CPC分类号： G06F3/0635 , G06F3/0604 , G06F3/0629 , G06F3/0631 , G06F3/0647 , G06F3/0665 , G06F3/067 , G06F3/0683 , G06F13/28 , H04L45/54 , H04L45/64
摘要： Some embodiments provide a method for configuring unit memories to implement first and second sets of entries, the second set of which references the first set. The method configures a first pool of unit memories to implement the first set. Each entry in the first set is located at a particular location in at least one of the memories of the first pool. The method configures a second pool of unit memories to implement the second set. Each entry in the second set includes a particular number of bits for indicating (i) an initial first-pool unit memory at which the first-set entry referenced by the second-set entry is found and (ii) a number of subsequent first-pool memories across which the first-set entry is divided. A number of bits required to identify a single first-pool memory is one fewer than the particular number of bits.
摘要翻译：一些实施例提供了一种用于配置单元存储器以实现第一和第二组条目的方法，其中第二组引用第一组。该方法配置第一个单元存储器池以实现第一组。第一组中的每个条目位于第一池的至少一个存储器中的特定位置。该方法配置第二个单元存储池以实现第二组。第二组中的每个条目包括特定数量的比特，用于指示（i）初始第一池单元存储器，在该初始第一池单元存储器中找到由第二组条目引用的第一组条目，以及（ii）第一组条目划分的池记忆。识别单个第一池存储器所需的位数比特定位数少一个。

70. 发明授权

US11469973B2 Data plane with heavy hitter detector 有权
公开(公告)号：US11469973B2
公开(公告)日：2022-10-11
申请号：US17042058
申请日：2019-03-08
申请人： Barefoot Networks, Inc.
发明人： Georgios Nikolaidis , Jeongkeun Lee , Changhoon Kim
IPC分类号： H04L43/026 , H04L47/32 , H04L41/142 , H04L45/16 , H04L45/00 , H04L45/64 , H04L45/7453 , H04L47/11 , H04L47/12 , H04L47/2441 , H04L47/2483 , H04L49/00 , H04L49/90 , H04L43/16
摘要： Some embodiments of the invention provide a data-plane forwarding circuit (data plane) that can be configured to identify large data message flows that it processes for forwarding in a network. In this document, large data message flows are referred to as heavy hitter flows. To perform its forwarding operations, the data plane includes several data message processing stages that are configured to process the data tuples associated with the data messages received by the data plane. In some embodiments, parts of the data plane message-processing stages are also configured to implement a heavy hitter detection (HHD) circuit. The operations of the data plane's message processing stages are configured by a control plane of the data plane's forwarding element in some embodiments.

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