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61. 发明申请

US20090012769A1 METHOD AND SYSTEM FOR LITHOGRAPHIC SIMULATION AND VERIFICATION 有权
标题翻译：用于光刻模拟和验证的方法和系统
公开(公告)号：US20090012769A1
公开(公告)日：2009-01-08
申请号：US11773118
申请日：2007-07-03
申请人： Fei Wang , William A. Stanton
发明人： Fei Wang , William A. Stanton
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Methods and systems for lithographic simulation and verification comprising a process in the frequency domain or in the spatial domain of calculating intensity at a location (x, y) for a number of defocus values. In addition, evaluating the intensity calculation result to determine if the intensity level will result in the mask pattern being written onto a wafer. The verification process may be calculated in the spatial domain or in the frequency domain. The calculations may be done such that full focus window calculations may be obtained by isolating the defocus parameter “z” in the calculations.
摘要翻译：用于光刻仿真和验证的方法和系统包括在多个离焦值的位置（x，y）处计算强度的频域或空间域中的过程。此外，评估强度计算结果以确定强度水平是否会导致掩模图案被写入晶片。验证过程可以在空间域或频域中计算。可以进行计算，使得可以通过在计算中隔离散焦参数“z”来获得全焦点窗口计算。

62. 发明申请

US20080221313A1 PROCESS FOR THE PREPARATION OF SUCRALOSE BY THE DEACYLATION OF TRICHLOROSUCROSE-6-ETHYL ESTER 有权
标题翻译：通过三氯蔗糖-6-乙酯脱水制备磺酰胺的方法
公开(公告)号：US20080221313A1
公开(公告)日：2008-09-11
申请号：US11746264
申请日：2007-05-09
申请人： Fei Wang , Haibing He , Jinshan Wu , Xin Yang , Yongzhu Yu , Zhisong Fan
发明人： Fei Wang , Haibing He , Jinshan Wu , Xin Yang , Yongzhu Yu , Zhisong Fan
IPC分类号： C07H1/00
CPC分类号： C07H1/00
摘要： The present invention discloses a process for the preparation of sucralose by the deacylation of trichlorosucrose-6-ethyl ester, wherein the deacylation reaction is performed in an alcohol solvent in the presence of organic base catalyst, so as to obtain sucralose.
摘要翻译：本发明公开了通过脱氯三氯蔗糖-6-乙基酯制备三氯半乳蔗糖的方法，其中脱醇反应在醇溶剂中，在有机碱催化剂存在下进行，以获得三氯蔗糖。

63. 发明申请

US20080192840A1 Smart video thumbnail 有权
标题翻译：智能视频缩略图
公开(公告)号：US20080192840A1
公开(公告)日：2008-08-14
申请号：US11704543
申请日：2007-02-09
申请人： Xian-Sheng Hua , Fei Wang , Zhike Kong , Shipeng Li , Waiman Lam , Zach Johnson , Mark Young , Aaron DeYonker , Mark Schwesinger
发明人： Xian-Sheng Hua , Fei Wang , Zhike Kong , Shipeng Li , Waiman Lam , Zach Johnson , Mark Young , Aaron DeYonker , Mark Schwesinger
IPC分类号： H04N11/04
CPC分类号： G06F17/30793 , G06F17/30802 , G06F17/30843 , G06K9/036 , G11B27/28 , H04N5/76 , H04N5/91 , H04N9/8227
摘要： Described herein is technology for, among other things, selecting a representative thumbnail from a video clip. The technology involves analyzing frames of the video clip to determine which frames are stable, the result of the analysis being a number of segments of stable frames. From the stable segments, a number of candidate segments are selected, where candidate segments are those segments determined to a degree of certainty to be program content. The representative thumbnail is then selected from among the frames of the candidate segments.
摘要翻译：这里描述的是用于从视频剪辑中选择代表性缩略图的技术。该技术涉及分析视频剪辑的帧以确定哪些帧是稳定的，分析的结果是稳定帧的多个段。从稳定段中，选择多个候选段，其中候选段是确定为程度内容的程度的那些段。然后从候选片段的帧中选择代表性缩略图。

64. 发明授权

US07349232B2 6F2 DRAM cell design with 3F-pitch folded digitline sense amplifier 有权
标题翻译： 6F2 DRAM单元设计，带3F间距折叠数字线读出放大器
公开(公告)号：US07349232B2
公开(公告)日：2008-03-25
申请号：US11376458
申请日：2006-03-15
申请人： Fei Wang , Anton P. Eppich
发明人： Fei Wang , Anton P. Eppich
IPC分类号： G11C5/06
CPC分类号： G11C11/4097 , G11C7/02 , G11C7/18 , H01L27/0207 , H01L27/10882
摘要： The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F2 is disclosed which has a plurality of dual bit active areas, each of the active areas having a substantially longitudinal axis, and a plurality of digitlines on a 3F-pitch arranged in a folded digitline architecture, wherein the active areas are positioned such that the longitudinal axis of the active areas is oriented at an angle with respect to a centerline of the digitlines.
摘要翻译：本发明一般涉及具有折叠数字线读出放大器的DRAM单元设计。在一个说明性实施例中，公开了具有多个具有6F 2的有效尺寸的多个存储单元的存储器阵列，其具有多个双位有源区域，每个有源区域具有基本上纵向的轴线以及以折叠的数字线结构布置的3F间距上的多个数字线，其中有源区域被定位成使得有源区域的纵向轴线相对于数字线的中心线成一定角度。

65. 发明申请

US20080063647A1 Antibodies against protective antigen and methods of use for passive immunization and treatment of anthrax 失效
标题翻译：针对保护性抗原的抗体和用于被动免疫和治疗炭疽的方法
公开(公告)号：US20080063647A1
公开(公告)日：2008-03-13
申请号：US11041318
申请日：2005-01-24
申请人： Phillip R. Morrow , Angray S. Kang , Fei Wang , Ivy Jiang , Ritsuko Sawada , Wolfgang Scholz , Jeanne Morrow
发明人： Phillip R. Morrow , Angray S. Kang , Fei Wang , Ivy Jiang , Ritsuko Sawada , Wolfgang Scholz , Jeanne Morrow
IPC分类号： A61K39/40 , C07K16/12
CPC分类号： C07K16/1278 , A61K39/40 , A61K2039/505 , C07K2317/21 , C07K2317/56 , C07K2317/76 , C07K2317/92 , A61K2300/00
摘要： A highly efficient method for generating human antibodies using recall technology is provided. In one aspect, human antibodies which are specific to the anthrax toxin are provided. In one aspect, human peripheral blood cells that have been pre-exposed to anthrax toxin are used in the SCID mouse model. This method results in high human antibody titers which are primarily of the IgG isotype and which contain antibodies of high specificity and affinity to desired antigens. The antibodies generated by this method can be used therapeutically and prophylactically for preventing or treating mammals exposed to anthrax. Thus, in one embodiment, a prophylactic or therapeutic agent used to counter the effects of anthrax toxin, released as a mechanism of bioterrorism, is provided. In one embodiment, a formulation and method for preventing and/or treating anthrax infection comprising a binding agent that prevents the assembly of the PA63 heptamer is also provided. Methods for diagnosis and methods to determine anthrax contamination are also described.
摘要翻译：提供了使用召回技术产生人抗体的高效方法。一方面，提供了对炭疽毒素特异性的人抗体。一方面，在SCID小鼠模型中使用预先暴露于炭疽毒素的人外周血细胞。该方法导致高的人抗体滴度，其主要是IgG同种型，并且其含有对所需抗原具有高特异性和亲和力的抗体。通过该方法产生的抗体可以治疗和预防用于预防或治疗暴露于炭疽的哺乳动物。因此，在一个实施方案中，提供了用作抵抗作为生物恐怖机制的机制释放的炭疽毒素的作用的预防或治疗剂。在一个实施方案中，还提供了用于预防和/或治疗炭疽感染的制剂和方法，其包含阻止PA 63七聚体组装的结合剂。还描述了诊断方法和确定炭疽污染的方法。

66. 发明申请

US20080032553A1 Electrical connector having improved shield 失效
标题翻译：具有改进屏蔽的电连接器
公开(公告)号：US20080032553A1
公开(公告)日：2008-02-07
申请号：US11888524
申请日：2007-08-01
申请人： Long-Fei Wang
发明人： Long-Fei Wang
IPC分类号： H01R13/648
CPC分类号： H01R13/506 , H01R13/6582 , H01R13/6594
摘要： An electrical connector (100) includes a lower shield (3), an insulative housing (1) assembled to the lower shield, a number of terminals (2) and a pair of upper shields (4). The lower shield has a bottom wall (33) and a pair of first side walls (32). Each first side wall has a pair of upper base portions (361) and a lower base portion (326) and defines a recess (325) between the upper base portions and the lower base portion. Each upper base portion has a projecting portion (363) extending outwardly therefrom through the recess for engaging with a protrusion (46) disposed on a top surface of the upper shield.
摘要翻译：电连接器（100）包括下屏蔽（3），组装到下屏蔽的绝缘壳体（1），多个端子（2）和一对上屏蔽件（4）。下屏蔽件具有底壁（33）和一对第一侧壁（32）。每个第一侧壁具有一对上基部（361）和下基部（326），并且在上基部和下基部之间限定凹部（325）。每个上基部具有从其向外延伸穿过凹部的突出部分（363），用于与设置在上屏蔽件的顶表面上的突起（46）接合。

67. 发明申请

US20080017776A1 Desk for reading and writing 失效
标题翻译：办公桌阅读和写作
公开(公告)号：US20080017776A1
公开(公告)日：2008-01-24
申请号：US11490828
申请日：2006-07-24
申请人： Yun-Fei Wang
发明人： Yun-Fei Wang
IPC分类号： A47B9/00 , A47B97/04
CPC分类号： A47B17/00 , A47B23/043
摘要： A desk for reading, writing, typing and painting is disclosed. The desk comprises a base plate, a deck, a long sliding track and a sliding positioning element. The base plate comprises a rotatable plate and a sliding hinge. The deck is secured to a tube of the sliding hinge. The long sliding track is attached to the sliding hinge and positioned over the rotatable plate. The sliding positioning element is adopted for positioning the sliding track and the deck.
摘要翻译：公开了一种用于阅读，写作，打字和绘画的书桌。桌子包括底板，甲板，长滑轨和滑动定位元件。基板包括可旋转板和滑动铰链。甲板固定在滑动铰链的管子上。长滑动轨道连接到滑动铰链并且定位在可旋转板上。滑动定位元件用于定位滑轨和甲板。

68. 发明授权

US07279410B1 Method for forming inlaid structures for IC interconnections 有权
标题翻译：用于形成IC互连的镶嵌结构的方法
公开(公告)号：US07279410B1
公开(公告)日：2007-10-09
申请号：US10379757
申请日：2003-03-05
申请人： Lynne A. Okada , Fei Wang , James Kai
发明人： Lynne A. Okada , Fei Wang , James Kai
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/311
CPC分类号： H01L21/76832 , H01L21/76802 , H01L21/76829
摘要： A method for forming an inlaid interconnect structure for ICs. The method includes forming an etch stop layer, opening a portion of the etch stop layer on an IC die, forming a dielectric layer and cap layer over the etch stop layer, forming a photoresist pattern, and etching the cap and dielectric to form an opening that is then filled with a conductive material (e.g., metal). The method may further include forming a barrier layer within the opening of the etch stop layer. According to another aspect of the invention, a first and second etch stop layer are formed over the substrate and the second etch stop layer is patterned to define two regions, wherein a second region having the first and second etch stop layers experiences a faster etch rate than the first region. The dielectric layer and cap layers are then deposited over both regions and two via or trench openings are formed therethrough in the regions, respectively. The first and second etch stop layers protect the underlying substrate from experiencing punchthrough during the via or trench formation. The etch stop layers are then removed in the openings and a conductive material is formed therein.
摘要翻译：一种用于形成用于IC的镶嵌互连结构的方法。该方法包括形成蚀刻停止层，在IC管芯上打开蚀刻停止层的一部分，在蚀刻停止层上形成介电层和覆盖层，形成光致抗蚀剂图案，以及蚀刻帽和电介质以形成开口然后用导电材料（例如金属）填充。该方法还可以包括在蚀刻停止层的开口内形成阻挡层。根据本发明的另一方面，在衬底上形成第一和第二蚀刻停止层，并且将第二蚀刻停止层图案化以限定两个区域，其中具有第一和第二蚀刻停止层的第二区域经历更快的蚀刻速率比第一个地区。然后将介电层和盖层沉积在两个区域上，并且分别在区域中形成两个通孔或沟槽开口。第一和第二蚀刻停止层在通孔或沟槽形成期间保护下面的衬底不经历穿透。然后在开口中去除蚀刻停止层，并在其中形成导电材料。

69. 发明授权

US07268418B2 Multi-chips stacked package 有权
标题翻译：多芯片堆叠包装
公开(公告)号：US07268418B2
公开(公告)日：2007-09-11
申请号：US10747128
申请日：2003-12-30
申请人： Sung-Fei Wang
发明人： Sung-Fei Wang
IPC分类号： H01L23/02 , H01L23/48
CPC分类号： H01L24/32 , H01L23/3128 , H01L24/33 , H01L24/48 , H01L24/83 , H01L25/0657 , H01L2224/05599 , H01L2224/2919 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/83139 , H01L2224/8314 , H01L2224/8319 , H01L2224/8385 , H01L2224/85399 , H01L2225/0651 , H01L2924/00014 , H01L2924/01013 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A multi-chips stacked package at least comprises a substrate, a lower chip, an upper chip, an adhesive layer, a supporting body and an encapsulation. The lower chip is disposed on the substrate and the upper chip is attached to the lower chip via the adhesive layer. In addition, the lower chip and the upper chip are electrically connected to the substrate via first electrically conductive wires and second electrically conductive wires respectively. Furthermore, the supporting body is disposed on the lower chip and at the periphery of the upper surface of the lower chip, and covered by the upper chip. The top of the supporting body is apart from the back surface of the upper chip with a distance. Accordingly, when the second electrically conductive wires are bonded the upper chip to the substrate with a larger bonding force to cause the upper chip to be tilted more, the supporting body will support the upper chip and prevent the upper chip from contacting the first electrically conductive wires.
摘要翻译：多芯片堆叠封装至少包括基板，下芯片，上芯片，粘合层，支撑体和封装。下芯片设置在基板上，并且上芯片通过粘合剂层附接到下芯片。此外，下芯片和上芯片分别经由第一导电线和第二导电线电连接到基板。此外，支撑体设置在下芯片的下芯片和下芯片的上表面的周边，并被上芯片覆盖。支撑体的顶部与上芯片的背面距离一定距离。因此，当第二导电线以更大的接合力将上部芯片接合到基板上以使上部芯片倾斜更多时，支撑体将支撑上部芯片，并防止上部芯片接触第一导电电线

70. 发明授权

US07256499B1 Ultra low dielectric constant integrated circuit system 有权
标题翻译：超低介电常数集成电路系统
公开(公告)号：US07256499B1
公开(公告)日：2007-08-14
申请号：US11230985
申请日：2005-09-19
申请人： Lu You , Fei Wang , Minh Quoc Tran , Lynne A. Okada
发明人： Lu You , Fei Wang , Minh Quoc Tran , Lynne A. Okada
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is provided including forming a porous ultra-low dielectric constant dielectric layer over a semiconductor substrate and forming an opening in the ultra-low dielectric constant dielectric layer. A dielectric liner is formed to line the opening to cover the pores in the ultra-low dielectric constant dielectric layer and a barrier layer is deposited to line the dielectric liner and conductor core is deposited to fill the opening over the barrier layer.
摘要翻译：提供了一种集成电路，包括在半导体衬底上形成多孔超低介电常数介电层，并在超低介电常数介电层中形成开口。形成电介质衬垫以使开口线对，以覆盖超低介电常数电介质层中的孔，并且沉积阻挡层以对电介质衬垫进行排列，并且沉积导体芯以填充阻挡层上的开口。

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