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    • 64. 发明申请
    • LIQUID CRYSTAL DISPLAY AND THIN FILM TRANSISTOR ARRAY PANEL THEREFOR
    • 液晶显示器和薄膜晶体管阵列
    • US20100149447A1
    • 2010-06-17
    • US12630249
    • 2009-12-03
    • Jung-Hee LEEYoon-Sung UMJong-Ho SONJae-Jin LYU
    • Jung-Hee LEEYoon-Sung UMJong-Ho SONJae-Jin LYU
    • G02F1/1343
    • G02F1/1368G02F1/13624G02F2001/134345H01L27/1255
    • A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer opposite the gate electrode; a data line formed on the gate insulating layer and including a first source electrode located on the semiconductor layer; first and second drain electrodes formed on the semiconductor layer, separated from each other and overlapping the gate electrode; a passivation layer formed on the data line and the first and second drain electrodes; and first and second pixel electrodes electrically connected to the first and second electrodes, respectively, wherein an overlapping area between the gate electrode and the first drain electrode is different from an overlapping area between the gate electrode and the second drain electrode.
    • 提供薄膜晶体管阵列面板,其包括:绝缘基板; 形成在所述基板上并包括栅电极的栅极线; 栅极绝缘层,形成在栅极线上; 形成在与栅电极相对的栅极绝缘层上的半导体层; 形成在所述栅绝缘层上并且包括位于所述半导体层上的第一源电极的数据线; 形成在半导体层上的第一和第二漏极彼此分离并与栅电极重叠; 形成在所述数据线和所述第一和第二漏电极上的钝化层; 以及分别与第一和第二电极电连接的第一和第二像素电极,其中栅电极和第一漏电极之间的重叠区域与栅电极和第二漏电极之间的重叠区域不同。
    • 69. 发明申请
    • THIN FILM TRANSISTOR ARRAY PANEL
    • 薄膜晶体管阵列
    • US20090310074A1
    • 2009-12-17
    • US12544871
    • 2009-08-20
    • Hyun-Wuk KimJae-Jin LyuYoon-Sung UmChang-Hun Lee
    • Hyun-Wuk KimJae-Jin LyuYoon-Sung UmChang-Hun Lee
    • G02F1/1343
    • G02F1/134309G02F1/136286G02F2001/134345
    • A thin film transistor array panel according to one embodiment of the invention comprises: first, second, and third pixel electrodes arranged sequentially, the second pixel electrode including first and second sub-pixel electrodes, the second pixel electrode occupying an area comprising a first area and a second area that is disposed closer to the third pixel electrode than the first area; first, second, and third thin film transistors connected to the first, the second, and the third pixel electrodes, respectively; first, second, and third gate lines connected to the first, the second, and the third thin film transistors, respectively; and a data line connected to the first, the second, and the third thin film transistors, wherein the second sub-pixel electrode is capacitively coupled to the third pixel electrode, and the second sub-pixel electrode is present in both the first and the second areas.
    • 根据本发明的一个实施例的薄膜晶体管阵列面板包括:顺序布置的第一,第二和第三像素电极,第二像素电极包括第一和第二子像素电极,第二像素电极占据包括第一区域 以及比所述第一区域更靠近所述第三像素电极设置的第二区域; 分别连接到第一,第二和第三像素电极的第一,第二和第三薄膜晶体管; 分别连接到第一,第二和第三薄膜晶体管的第一,第二和第三栅极线; 以及连接到第一,第二和第三薄膜晶体管的数据线,其中第二子像素电极电容耦合到第三像素电极,并且第二子像素电极存在于第一和第三薄膜晶体管的第一和第三薄膜晶体管中, 第二区。