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61. 发明授权

US07638406B2 Method of fabricating a high Q factor integrated circuit inductor 有权
标题翻译：制造高Q因子集成电路电感的方法
公开(公告)号：US07638406B2
公开(公告)日：2009-12-29
申请号：US11320375
申请日：2005-12-28
申请人： Daniel C. Edelstein , Panayotis C. Andricacos , John M. Cotte , Hariklia Deligianni , John H. Magerlein , Kevin S. Petrarca , Kenneth J. Stein , Richard P. Volant
发明人： Daniel C. Edelstein , Panayotis C. Andricacos , John M. Cotte , Hariklia Deligianni , John H. Magerlein , Kevin S. Petrarca , Kenneth J. Stein , Richard P. Volant
IPC分类号： H01L21/20
CPC分类号： H01L24/12 , H01L23/5227 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L27/08 , H01L28/10 , H01L2224/0401 , H01L2224/04042 , H01L2224/05007 , H01L2224/05014 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05084 , H01L2224/05555 , H01L2224/05557 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48644 , H01L2224/48724 , H01L2224/48744 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19042 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： A method of forming an inductor. The method includes: forming a dielectric layer on a substrate; forming a lower trench in the dielectric layer; forming a liner in the lower trench and on the dielectric layer; forming a Cu seed layer over the liner; forming a resist layer on the Cu seed layer; forming an upper trench in the resist layer; electroplating Cu to completely fill the lower trench and at least partially fill the upper trench; removing the resist layer; selectively forming a passivation layer on all exposed Cu surfaces; selectively removing the Cu seed layer from regions of the liner; and removing the thus exposed regions of the liner from the dielectric layer, wherein a top surface of the inductor extends above a top surface of the dielectric layer, the passivation layer remaining on regions of sidewalls of the inductor above the top surface of the dielectric layer.
摘要翻译：一种形成电感器的方法。该方法包括：在基板上形成电介质层; 在介电层中形成下沟槽; 在下沟槽和电介质层上形成衬垫; 在衬套上形成Cu籽晶层; 在Cu籽晶层上形成抗蚀剂层; 在抗蚀剂层中形成上沟槽; 电镀Cu以完全填充下沟槽并且至少部分地填充上沟槽; 去除抗蚀剂层; 在所有暴露的Cu表面上选择性地形成钝化层; 从所述衬垫的区域选择性地去除所述Cu籽晶层; 以及从所述电介质层去除所述衬垫的这样暴露的区域，其中所述电感器的顶表面延伸到所述电介质层的顶表面之上，所述钝化层保留在所述电介质的位于所述电介质层的顶表面之上的侧壁的区域上。

62. 发明申请

US20090239062A1 METHOD AND STRUCTURE OF INTEGRATED RHODIUM CONTACTS WITH COPPER INTERCONNECTS 有权
标题翻译：具有铜互联的集成式RHODIUM接触器的方法与结构
公开(公告)号：US20090239062A1
公开(公告)日：2009-09-24
申请号：US12053969
申请日：2008-03-24
申请人： John M. Cotte , Balasubramanian Haran , Christopher C. Parks , Xiaoyan Shao , Eva E. Simonyi
发明人： John M. Cotte , Balasubramanian Haran , Christopher C. Parks , Xiaoyan Shao , Eva E. Simonyi
IPC分类号： B32B9/04 , B05D5/12
CPC分类号： H01L21/76843 , H01L21/2885 , H01L21/76873 , H01L21/76879 , H01L23/485 , H01L23/53238 , H01L2924/0002 , Y10T428/26 , H01L2924/00
摘要： The present disclosure relates to a microelectronic structure and the manufacture of the microelectronic structure. Specifically, the disclosure relates to an interconnect barrier layer between a rhodium contact structure and a copper interconnect structure in a microelectronic structure. The microelectronic structure provides for low resistance in microelectronic devices.
摘要翻译：本公开涉及微电子结构和微电子结构的制造。具体地，本公开涉及在微电子结构中的铑接触结构和铜互连结构之间的互连势垒层。微电子结构在微电子器件中提供低电阻。

63. 发明申请

US20090032951A1 Small Area, Robust Silicon Via Structure and Process 有权
标题翻译：小面积，坚固的硅通过结构和工艺
公开(公告)号：US20090032951A1
公开(公告)日：2009-02-05
申请号：US11833112
申请日：2007-08-02
申请人： Paul S. Andry , John M. Cotte , John Ulrich Knickerbocker , Cornelia K. Tsang
发明人： Paul S. Andry , John M. Cotte , John Ulrich Knickerbocker , Cornelia K. Tsang
IPC分类号： H01L21/768 , H01L23/52
CPC分类号： H01L21/76898 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/80 , H01L24/94 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/16 , H01L2224/94 , H01L2924/0002 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H01L2224/11 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor structure includes: at least one silicon surface wherein the surface can be a substrate, wafer or other device. The structure further includes at least one electronic circuit formed on each side of the at least one surface; and at least one conductive high aspect ratio through silicon via running through the at least one surface. Each through silicon via is fabricated from at least one etch step and includes: at least one thermal oxide dielectric for coating at least some of a sidewall of the through silicon via for a later etch stop in fabrication of the through silicon via.
摘要翻译：半导体结构包括：至少一个硅表面，其中该表面可以是衬底，晶片或其它器件。该结构还包括形成在至少一个表面的每一侧上的至少一个电子电路; 以及通过硅穿过所述至少一个表面的至少一个导电高宽比。每个通过硅通孔由至少一个蚀刻步骤制造，并且包括：至少一个热氧化物电介质，用于涂覆通孔硅通孔的侧壁中的至少一些，用于随后的通孔硅制造中的蚀刻停止。

64. 发明授权

US07202764B2 Noble metal contacts for micro-electromechanical switches 有权
标题翻译：贵金属触点用于微机电开关
公开(公告)号：US07202764B2
公开(公告)日：2007-04-10
申请号：US10604278
申请日：2003-07-08
申请人： Hariklia Deligianni , Panayotis Andricacos , L. Paivikki Buchwalter , John M. Cotte , Christopher Jahnes , Mahadevaiyer Krishnan , John H. Magerlein , Kenneth Stein , Richard P. Volant , James A. Tornello , Jennifer Lund
发明人： Hariklia Deligianni , Panayotis Andricacos , L. Paivikki Buchwalter , John M. Cotte , Christopher Jahnes , Mahadevaiyer Krishnan , John H. Magerlein , Kenneth Stein , Richard P. Volant , James A. Tornello , Jennifer Lund
IPC分类号： H01H51/22
CPC分类号： H01H59/0009 , H01H2001/0052 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204
摘要： A semiconductor micro-electromechanical system (MEMS) switch provided with noble metal contacts that act as an oxygen barrier to copper electrodes is described. The MEMS switch is fully integrated into a CMOS semiconductor fabrication line. The integration techniques, materials and processes are fully compatible with copper chip metallization processes and are typically, a low cost and a low temperature process (below 400° C.). The MEMS switch includes: a movable beam within a cavity, the movable beam being anchored to a wall of the cavity at one or both ends of the beam; a first electrode embedded in the movable beam; and a second electrode embedded in an wall of the cavity and facing the first electrode, wherein the first and second electrodes are respectively capped by the noble metal contact.
摘要翻译：描述了提供有作为铜电极的氧阻隔的贵金属触点的半导体微机电系统（MEMS）开关。 MEMS开关完全集成到CMOS半导体制造线中。集成技术，材料和工艺完全兼容铜芯片金属化工艺，通常是低成本和低温工艺（低于400℃）。 MEMS开关包括：在空腔内的可移动光束，可移动光束在光束的一端或两端锚定到空腔的壁; 嵌入可移动光束中的第一电极; 以及第二电极，其嵌入在所述空腔的壁中并且面向所述第一电极，其中所述第一和第二电极分别被所述贵金属接触物覆盖。

65. 发明授权

US06900142B2 Inhibition of tin oxide formation in lead free interconnect formation 失效
标题翻译：在无铅互连形成中抑制氧化锡形成
公开(公告)号：US06900142B2
公开(公告)日：2005-05-31
申请号：US10604560
申请日：2003-07-30
申请人： Emanual I. Cooper , John M. Cotte , Lisa A. Fanti , David E. Eichstadt , Stephen J. Kilpatrick , Henry A. Nye, III , Donna S. Zupanski-Nielsen
发明人： Emanual I. Cooper , John M. Cotte , Lisa A. Fanti , David E. Eichstadt , Stephen J. Kilpatrick , Henry A. Nye, III , Donna S. Zupanski-Nielsen
IPC分类号： H01L21/302 , H01L21/44 , H01L21/461 , H01L21/60
CPC分类号： H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05147 , H01L2224/05171 , H01L2224/05572 , H01L2224/05647 , H01L2224/13099 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/00014
摘要： A method is provided for removing exposed seed layers in the fabrication of solder interconnects on electronic components such as semiconductor wafers without damaging the interconnects or underlying wafer substrate and with a high wafer yield. The solder interconnects are lead free or substantially lead free and typically contain Sn. An oxalic acid solution is used to contact the wafer after an etching step to remove part of the seed layer. The seed layer is typically a Cu containing layer with a lower barrier layer containing barrier metals such as Ti, Ta and W. The lower barrier layer remains after the etch and the oxalic acid solution inhibits the formation of Sn compounds on the barrier layer surface which compounds may mask the barrier layer and the barrier layer etchant resulting in incomplete barrier layer removal on the wafer surface. Any residual conductive barrier layer can cause shorts and other wafer problems and result in a lower wafer yield. An electroetch is preferred to remove the portion of the seed layer overlying the lower barrier layer.
摘要翻译：提供了一种在电子部件如半导体晶片制造焊料互连件中去除暴露的种子层的方法，而不会损坏互连或下面的晶片衬底并以高的晶片产量。焊料互连是无铅的或基本上无铅的，并且通常含有Sn。在蚀刻步骤之后，使用草酸溶液接触晶片以除去部分种子层。种子层通常是含Cu层，其具有包含阻挡金属如Ti，Ta和W的下阻挡层。在蚀刻后保留下阻挡层，并且草酸溶液抑制在阻挡层表面上形成Sn化合物化合物可以掩蔽阻挡层和阻挡层蚀刻剂，导致晶片表面上不完全的阻挡层去除。任何残留的导电阻挡层可能导致短路和其他晶片问题，并导致较低的晶圆产量。优选去除电子蚀刻以去除覆盖在下阻挡层上的种子层的部分。

66. 发明授权

US06613641B1 Production of metal insulator metal (MIM) structures using anodizing process 失效
公开(公告)号：US06613641B1
公开(公告)日：2003-09-02
申请号：US09764834
申请日：2001-01-17
申请人： Richard P. Volant , John M. Cotte , Kevin S. Petrarca , Kenneth J. Stein
发明人： Richard P. Volant , John M. Cotte , Kevin S. Petrarca , Kenneth J. Stein
IPC分类号： H01L218238
CPC分类号： H01L28/40 , H01L21/31687 , Y10S438/957
摘要： Metal-insulator-metal capacitor structures are formed in semiconductor substrates using an anodization procedure on deposited underlying metalization followed by deposition of the second metal and planarization by chemical-mechanical polishing or other procedures. The process is additive in character, as opposed to traditional subtractive etch processes for forming capacitor structures. In addition, the process can be used in damascene applications, and can be used to form a wide variety of capacitive structures while reducing the number of mask layers required for formation.

67. 发明授权

US6030728A High performance lithium polymer electrolyte battery 失效
标题翻译：高性能锂聚合物电解质电池
公开(公告)号：US6030728A
公开(公告)日：2000-02-29
申请号：US915134
申请日：1997-08-20
申请人： John M. Cotte , Madhav Datta
发明人： John M. Cotte , Madhav Datta
IPC分类号： H01M4/62 , H01M4/66 , H01M6/16 , H01M6/18 , H01M6/50
CPC分类号： H01M4/622 , H01M6/181 , H01M2006/5094 , H01M2300/004 , H01M4/661 , H01M6/164
摘要： A primary lithium battery particularly adapted for use in self-contained self-powered devices (SSPD) for mobile communication and computing products, such as radio frequency identification tags, PCMCIA cards, and smart cards. The battery utilizes a solid polymer electrolyte membrane that preferably has a polyacrylonitrile matrix. Performance of the electrolyte membrane is optimized by controlling the amount of aprotic organic solvents within the membrane within a prescribed range of ratios. The battery cathode is encapsulated within a polymeric matrix that eliminates the exposure hazard posed by lithium intercalation compounds used within the cathode. Use of stainless steel foil current collectors gives a high open circuit voltage of 3.8 volts and high cell capacity. A method of determining the optimum cathode thickness in the battery is also described. This provides a means of maximizing volumetric and gravimetric energy densities by using the optimum amount of cathode material. Batteries fabricated by using optimal materials can be operated under pulsed and dc discharge conditions over a temperature range between about -40 and +80.degree. C.
摘要翻译：特别适用于用于移动通信和计算产品（如射频识别标签，PCMCIA卡和智能卡）的自包含自供电设备（SSPD）中的主要锂电池。电池使用优选具有聚丙烯腈基质的固体聚合物电解质膜。通过在规定的比例范围内控制膜内非质子有机溶剂的量来优化电解质膜的性能。电池阴极被封装在聚合物基质内，消除了在阴极内使用的锂嵌入化合物引起的暴露危害。使用不锈钢箔集电器可提供3.8伏的高开路电压和高电池容量。还描述了确定电池中最佳阴极厚度的方法。这提供了通过使用最佳量的阴极材料来最大化体积和重量能量密度的方法。通过使用最佳材料制造的电池可在脉冲和直流放电条件下在约-40至+80℃的温度范围内运行。

68. 发明授权

US5989751A High energy density, flexible lithium primary batteries 失效
标题翻译：高能量密度，柔性锂一次电池
公开(公告)号：US5989751A
公开(公告)日：1999-11-23
申请号：US876786
申请日：1997-06-16
申请人： John M. Cotte , Madhav Datta
发明人： John M. Cotte , Madhav Datta
IPC分类号： H01M4/62 , H01M2/02 , H01M2/16 , H01M4/06 , H01M4/66 , H01M6/12 , H01M6/16 , H01M6/18 , H01M6/14 , H01M4/50 , H01M4/64
CPC分类号： H01M4/622 , H01M2/0212 , H01M4/06 , H01M6/16 , H01M2/1673 , H01M2300/0085 , H01M4/668 , H01M6/12 , H01M6/164 , H01M6/181 , H01M6/188
摘要： A primary lithium battery particularly adapted for use in self-contained self-powered devices (SSPD) for mobile communication and computing products, such as radio frequency identification tags, PCMCIA cards, and smart cards. The battery has a flexible and compact design which eliminates use of a separate electrolyte membrane by utilizing an electrolyte-bearing composite cathode that preferably has a polyacrylonitrile matrix. Performance of the battery is optimized by controlling the amount of aprotic organic solvents within the composite cathode within a prescribed range of ratios. In so doing, the performance characteristics of the battery closely approximate those having conventional liquid electrolytes without the safety concerns associated with liquid electrolyte leakage, and exhibit enhanced performance at sub-ambient temperatures. A further feature is that the composite cathode is encapsulated within a polymeric matrix that eliminates the exposure hazard posed by the lithium intercalation compounds used within the cathode. The battery is enclosed in a customized laminate stack for sealing and encapsulation. Alternative packaging embodiments are also disclosed.
摘要翻译：特别适用于用于移动通信和计算产品（如射频识别标签，PCMCIA卡和智能卡）的自包含自供电设备（SSPD）中的主要锂电池。电池具有灵活且紧凑的设计，通过利用优选具有聚丙烯腈基质的电解质负载复合阴极来消除使用单独的电解质膜。通过控制复合阴极内的非质子有机溶剂的量在规定的比例范围内来优化电池的性能。在这样做时，电池的性能特征与具有常规液体电解质的性能特征密切相关，而没有与液体电解质泄漏相关的安全考虑，并且在低于环境温度下表现出增强的性能。另一个特征是复合阴极被封装在聚合物基质内，消除了在阴极内使用的锂嵌入化合物引起的暴露危害。电池被封装在一个定制的叠层堆叠中，用于密封和封装。还公开了另外的包装实施例。

69. 发明授权

US08592932B2 Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers 有权
公开(公告)号：US08592932B2
公开(公告)日：2013-11-26
申请号：US13430195
申请日：2012-03-26
申请人： Paul S. Andry , John M. Cotte , John U. Knickerbocker , Cornelia K. Tsang
发明人： Paul S. Andry , John M. Cotte , John U. Knickerbocker , Cornelia K. Tsang
IPC分类号： H01L31/0203
CPC分类号： H01L21/6835 , H01L23/147 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L24/81 , H01L25/0655 , H01L25/0657 , H01L2221/68345 , H01L2224/16225 , H01L2224/81801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01077 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2924/00 , H01L2224/0401
摘要： Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.

70. 发明授权

US08524606B2 Chemical mechanical planarization with overburden mask 有权
标题翻译：化学机械平面化与上覆层掩模
公开(公告)号：US08524606B2
公开(公告)日：2013-09-03
申请号：US13012821
申请日：2011-01-25
申请人： Leslie Charns , John M. Cotte , Jason E. Cummings , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
发明人： Leslie Charns , John M. Cotte , Jason E. Cummings , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
IPC分类号： H01L21/311
CPC分类号： H01L21/31053 , H01L29/517 , H01L29/6653 , H01L29/66545
摘要： Planarization methods include depositing a mask material on top of an overburden layer on a semiconductor wafer. The mask material is planarized to remove the mask material from up areas of the overburden layer to expose the overburden layer without removing the mask material from down areas. The exposed overburden layer is wet etched and leaves a thickness remaining over an underlying layer. Remaining portions of the mask layer and the exposed portions of the overburden layer are planarized to expose the underlying layer.
摘要翻译：平面化方法包括在半导体晶片上的覆盖层顶部沉积掩模材料。将掩模材料平坦化以从覆盖层的上部区域去除掩模材料，以暴露覆盖层，而不从掩模材料向下区域移除。暴露的覆盖层被湿蚀刻并留下厚度保留在下层上。掩模层的剩余部分和覆盖层的暴露部分被平坦化以暴露下面的层。

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