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61. 发明申请

US20050270846A1 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20050270846A1
公开(公告)日：2005-12-08
申请号：US11197552
申请日：2005-08-05
申请人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
发明人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/105 , H01L27/115
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.
摘要翻译：选择栅极晶体管具有由第一级导电层和第二级导电层构成的选择栅电极。第一级导电层具有接触区域。第二级导电层的部分被去除，位于接触区域上方。在列方向上彼此相邻的两个相邻的选择栅电极被布置成使得一个选择栅电极的接触区域不与另一个选择栅电极的接触区域相对。一个选择栅电极在其与另一个选择栅电极的接触区域相对的部分中移除其第一和第二级导电层。

62. 发明申请

US20050181561A1 Nonvolatile semiconductor memory and manufacturing method thereof 失效
公开(公告)号：US20050181561A1
公开(公告)日：2005-08-18
申请号：US11100492
申请日：2005-04-07
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： H01L21/3205 , H01L21/76 , H01L21/762 , H01L21/8247 , H01L23/52 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/11526 , H01L21/76224 , H01L27/105 , H01L27/115 , H01L27/11529 , H01L27/11543
摘要： A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor substrate. The interlayer insulator has a wiring trench extending in a second direction intersecting the first direction. A first conductive material layer is provided at the cross-point of the active area and the wiring trench so that it is insulated from the active area. A second conductive material layer is provided in the wiring trench so that it is insulated from the first conductive material layer. A metal layer is provided in the wiring trench so that it is electrically in contact the second conductive material layer.

63. 发明授权

US06891246B2 Nonvolatile semiconductor memory and manufacturing method thereof 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US06891246B2
公开(公告)日：2005-05-10
申请号：US10178263
申请日：2002-06-25
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： H01L21/3205 , H01L21/76 , H01L21/762 , H01L21/8247 , H01L23/52 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/00
CPC分类号： H01L27/11526 , H01L21/76224 , H01L27/105 , H01L27/115 , H01L27/11529 , H01L27/11543
摘要： A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor substrate. The interlayer insulator has a wiring trench extending in a second direction intersecting the first direction. A first conductive material layer is provided at the cross-point of the active area and the wiring trench so that it is insulated from the active area. A second conductive material layer is provided in the wiring trench so that it is insulated from the first conductive material layer. A metal layer is provided in the wiring trench so that it is electrically in contact the second conductive material layer.
摘要翻译：非易失性半导体存储器包括设置在半导体衬底中的沟槽隔离和设置在半导体衬底上的层间绝缘体。沟槽隔离限定了在半导体衬底处沿第一方向延伸的有源区。层间绝缘体具有沿与第一方向相交的第二方向延伸的布线沟槽。第一导电材料层设置在有源区和布线沟槽的交叉点处，使其与有源区绝缘。第二导电材料层设置在布线沟槽中，使其与第一导电材料层绝缘。金属层设置在布线沟槽中，使其与第二导电材料层电接触。

64. 发明授权

US06828627B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06828627B2
公开(公告)日：2004-12-07
申请号：US10742952
申请日：2003-12-23
申请人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
发明人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
IPC分类号： H01L2972
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L29/42324
摘要： A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.
摘要翻译：半导体器件具有稳定的驱动力和高性能的可靠性。半导体器件具有至少一个晶体管，其具有形成在半导体衬底中的元件区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和在栅电极两侧的元件区域中的扩散层。该器件还具有形成为覆盖晶体管和扩散层的阻挡绝缘膜。从半导体衬底的表面到阻挡绝缘膜的高度大于栅极绝缘膜和栅电极之间的界面的表面的高度。

65. 发明授权

US06703669B1 Semiconductor device having serially connected memory cell transistors provided between two current terminals 有权
标题翻译：具有串联连接的存储单元晶体管的半导体器件设置在两个电流端子之间
公开(公告)号：US06703669B1
公开(公告)日：2004-03-09
申请号：US09714228
申请日：2000-11-17
申请人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
发明人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L29/42324
摘要： A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.
摘要翻译：半导体器件具有稳定的驱动力和高性能的可靠性。半导体器件具有至少一个晶体管，其具有形成在半导体衬底中的元件区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和在栅电极两侧的元件区域中的扩散层。该器件还具有形成为覆盖晶体管和扩散层的阻挡绝缘膜。从半导体衬底的表面到阻挡绝缘膜的高度大于栅极绝缘膜和栅电极之间的界面的表面的高度。

66. 发明授权

US06703658B2 Non-volatile semiconductor memory device and its manufacturing method 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US06703658B2
公开(公告)日：2004-03-09
申请号：US10429460
申请日：2003-05-05
申请人： Toshitake Yaegashi , Kazuhiro Shimizu , Seiichi Aritome
发明人： Toshitake Yaegashi , Kazuhiro Shimizu , Seiichi Aritome
IPC分类号： H01L27108
CPC分类号： H01L29/788 , G11C16/0416 , G11C16/0433 , G11C16/0483 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/11546 , Y10S257/908
摘要： In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.
摘要翻译：在非易失性半导体存储器件及其制造方法中，每个存储单元及其选择Tr具有与Vcc Tr相同的栅极绝缘膜。此外，Vpp Tr和Vcc Tr的栅极通过使用第一多晶硅层来实现。可以在第一多晶硅层上提供与第二多晶硅（形成控制栅极层）不同的诸如硅化物或金属的材料。利用上述特征，可以通过减小的步骤制造非易失性半导体存储器件并以可靠的方式高速运行。

67. 发明授权

US06680230B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06680230B2
公开(公告)日：2004-01-20
申请号：US10201111
申请日：2002-07-24
申请人： Norihisa Arai , Fumitaka Arai , Seiichi Aritome , Akira Shimizu , Riichiro Shirota
发明人： Norihisa Arai , Fumitaka Arai , Seiichi Aritome , Akira Shimizu , Riichiro Shirota
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A method of fabricating a semiconductor device which has a cell array with non-volatile memory transistors and a peripheral circuit including a first transistor and a second transistor as driven by a lower voltage than the first transistor is disclosed. The method includes the steps of forming over a semiconductor substrate a first gate dielectric film for use in the first transistor, selectively etching the first gate dielectric film in the cell array region to expose the substrate, forming over the exposed substrate a second gate dielectric film which is for use as a tunnel dielectric film of the memory transistors, forming a first gate electrode material film over the first and second gate dielectric films, selectively etching the first gate electrode material film and its underlying first gate dielectric film in the second transistor region, forming over the exposed substrate a third gate dielectric film which is for use in the second transistor, forming a second gate electrode material film over the third gate dielectric film, and forming gates of the respective transistors while letting the gates at least partly include the first and second gate electrode material films.
摘要翻译：公开了一种制造半导体器件的方法，该半导体器件具有具有非易失性存储晶体管的单元阵列和包括由比第一晶体管低的电压驱动的第一晶体管和第二晶体管的外围电路。该方法包括以下步骤：在半导体衬底上形成用于第一晶体管的第一栅极电介质膜，选择性地蚀刻电池阵列区域中的第一栅极电介质膜以暴露衬底，在暴露的衬底上形成第二栅极电介质膜其用作存储晶体管的隧道电介质膜，在第一和第二栅极电介质膜上形成第一栅电极材料膜，在第二晶体管区域中选择性地蚀刻第一栅电极材料膜及其下面的第一栅极电介质膜在暴露的衬底上形成用于第二晶体管的第三栅极电介质膜，在第三栅极电介质膜上形成第二栅电极材料膜，并且在使栅极至少部分地包括第一和第二栅电极材料膜。

68. 发明授权

US06495896B1 Semiconductor integrated circuit device with high and low voltage wells 失效
标题翻译：具有高低压井的半导体集成电路器件
公开(公告)号：US06495896B1
公开(公告)日：2002-12-17
申请号：US09407401
申请日：1999-09-28
申请人： Toshitake Yaegashi , Seiichi Aritome , Yuji Takeuchi , Kazuhiro Shimizu
发明人： Toshitake Yaegashi , Seiichi Aritome , Yuji Takeuchi , Kazuhiro Shimizu
IPC分类号： H01L2900
CPC分类号： H01L27/11526 , H01L21/761 , H01L21/823878 , H01L27/11531
摘要： A semiconductor integrated circuit device comprises an n-type well 8-1 formed in a p-type silicon substrate 1, an n-type well 8-2 formed so as to surround a part of the substrate 1, in which a p−-type well is formed, a p−-type well 15-1 formed in the substrate 1, a p−-type well 15-2 formed in a part of the substrate 1, which is surrounded by the n-type well, an embedded n-type well 12-1 formed below the p−-type well 15-1, and an n-type well 12-2 which is formed below the p−-type well 15-2 and which is connected to the n-type well 8-2. Thus, it is possible to provide a semiconductor integrated circuit device capable of suppressing the increase of the number of photolithography steps and reducing the manufacturing costs. Alternatively, low-voltage n-channel MOS transistors QN1, QN2 and low-voltage p-channel MOS transistors QP1, QP2 are formed in a p-type well 214 and n-type well 213 of a p−-type silicon substrate 211, respectively, and high-voltage n-channel MOS transistors QN3, QN4 are formed in the substrate 211. The p-type well 214, in which the transistors QN1, QN2 are formed, and the p-type element isolating layer 215 of the element isolating regions for the transistors QN3, QN4 are simultaneously formed by ion implantation using a resist mask by the lithography on a flat surface having no step. The p-type well 214 and the p-type element isolating layer 215 have the same depth from the substrate surface of the element regions and the same impurity density. Thus, it is possible to provide a semiconductor integrated circuit device capable of achieving good element isolation characteristics, and a method for producing the same.
摘要翻译：半导体集成电路器件包括形成在p型硅衬底1中的n型阱8-1，形成为围绕衬底1的一部分的n型阱8-2，其中p型形成良好的p型阱15-1，形成在衬底1中的p型阱15-1，形成在衬底1的被n型阱包围的部分中的p型阱15-2，嵌入 n型阱12-1形成在p型阱15-1的下方，n型阱12-2形成在p型阱15-2的下方，并与n型阱15-1连接。好8-2。因此，可以提供能够抑制光刻步骤数量增加并降低制造成本的半导体集成电路器件。或者，低电压n沟道MOS晶体管QN1，QN2和低压p沟道MOS 晶体管QP1，QP2分别形成在p型硅衬底211的p型阱214和n型阱213中，并且高压n沟道MOS晶体管QN3，QN4形成在衬底211中。其中形成晶体管QN1，QN2的p型阱214和用于晶体管QN3，QN4的元件隔离区的p型元件隔离层215同时通过使用光刻胶的抗蚀剂掩模的离子注入形成在没有台阶的平坦表面上。 p型阱214和p型元件隔离层215具有与元件区域的衬底表面相同的深度和相同的杂质密度。因此，可以提供能够实现良好元件隔离特性的半导体集成电路器件及其制造方法。

69. 发明授权

US06462373B2 Nonvolatile semiconductor memory device having tapered portion on side wall of charge accumulation layer 失效
标题翻译：非易失性半导体存储器件在电荷累积层的侧壁上具有锥形部分
公开(公告)号：US06462373B2
公开(公告)日：2002-10-08
申请号：US09725564
申请日：2000-11-30
申请人： Kazuhiro Shimizu , Riichiro Shirota , Naoki Koido , Seiichi Aritome , Hiroaki Tsunoda , Tadashi Iguchi , Kazuhito Narita , Kunihiro Terasaka , Hirohisa Iizuka
发明人： Kazuhiro Shimizu , Riichiro Shirota , Naoki Koido , Seiichi Aritome , Hiroaki Tsunoda , Tadashi Iguchi , Kazuhito Narita , Kunihiro Terasaka , Hirohisa Iizuka
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11534
摘要： In a nonvolatile semiconductor memory device, a charge accumulation layer is formed between adjacent two device isolation regions, at least a portion of the charge accumulation layer sandwiched with the device isolation regions has side walls each having a taper angle of 80 degrees or more and less than 90 degrees so that the charge accumulation layer at a lower end has a width wider than that at an upper end, a size of an opening of each of the device isolation regions is 0.25 &mgr;m or less, and a gate length of a memory cell is 0.2 &mgr;m or less.
摘要翻译：在非易失性半导体存储器件中，在相邻的两个器件隔离区域之间形成电荷累积层，夹在器件隔离区域的电荷累积层的至少一部分具有各自具有80度以上的锥角的侧壁使得下端的电荷累积层的宽度比上端的宽度宽，器件隔离区域的开口尺寸为0.25μm以下，存储单元的栅极长度为0.2μm以下。

70. 发明授权

US06342715B1 Nonvolatile semiconductor memory device 失效
公开(公告)号：US06342715B1
公开(公告)日：2002-01-29
申请号：US09097258
申请日：1998-06-15
申请人： Kazuhiro Shimizu , Seiichi Aritome , Toshiharu Watanabe , Kazuhito Narita
发明人： Kazuhiro Shimizu , Seiichi Aritome , Toshiharu Watanabe , Kazuhito Narita
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A nonvolatile semiconductor memory device comprises a semiconductor substrate, element isolating regions provided in the semiconductor substrate, first element regions, each of which is defined by two adjacent ones of the element isolating regions, and memory cell transistors formed in the element regions, wherein each of the memory cell transistors comprises a first gate insulating film formed on a corresponding one of the element isolating regions, a floating gate electrode formed on the gate insulating film, a second gate insulating film formed on the floating gate electrode, and a control electrode formed on the second gate insulating film and connected in common to a specific number of ones of the memory cell transistors to serve as a word line, and the floating gate includes a first conductive member with side faces in contact with side ends of the two adjacent ones of the element isolating regions and a second conductive member electrically connected to the first conductive member and formed so as to bridge a gap between the two adjacent ones of element isolating regions.

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