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1. 发明授权

US06833579B2 Conductive container structures having a dielectric cap 失效
标题翻译：具有电介质盖的导电容器结构
公开(公告)号：US06833579B2
公开(公告)日：2004-12-21
申请号：US09945497
申请日：2001-08-30
申请人： Gurtej Singh Sandhu , Alan R. Reinberg
发明人： Gurtej Singh Sandhu , Alan R. Reinberg
IPC分类号： H01L27108
CPC分类号： H01L28/90 , H01L27/10852 , H01L28/84 , H01L28/91 , Y10S257/906
摘要： Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.
摘要翻译：用于集成电路的集装箱结构及其制造方法。容器结构在导电容器的顶部上具有电介质盖，以通过隔离导电碎片穿过相邻容器结构顶部的桥接来降低容器与容器短路的风险。容器结构适用于并入这种存储单元的存储器单元和装置以及其它集成电路。

2. 发明授权

US06833575B2 Dopant barrier for doped glass in memory devices 有权
公开(公告)号：US06833575B2
公开(公告)日：2004-12-21
申请号：US10233279
申请日：2002-08-29
申请人： Kunal R. Parekh , Gurtej Singh Sandhu
发明人： Kunal R. Parekh , Gurtej Singh Sandhu
IPC分类号： H01L27108
CPC分类号： H01L21/76897 , H01L21/28247 , H01L21/3003 , H01L21/76832
摘要： A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes alumina and optionally a nitride, and has a layer thickness satisfying the high aspect ratio of the gaps between the surface structures, while adequately preventing dopants in doped glass layer from diffusing out of the doped glass layer to the surface structures and the substrate. Further, heavy water can be used during the formation of the alumina so that deuterium may be accomplished near the interface of surface structures and the substrate to enhance the performance of the device.

3. 发明授权

US06831319B2 Cell nitride nucleation on insulative layers and reduced corner leakage of container capacitors 失效
公开(公告)号：US06831319B2
公开(公告)日：2004-12-14
申请号：US10225913
申请日：2002-08-22
申请人： Lingyi A. Zheng
发明人： Lingyi A. Zheng
IPC分类号： H01L27108
CPC分类号： H01L28/40 , H01L21/3185 , H01L28/84 , H01L28/90
摘要： Methods of forming a uniform cell nitride dielectric layer over varying substrate materials such as an insulation material and a conductive or semiconductive material, methods of forming capacitors having a uniform nitride dielectric layer deposited onto varying substrate materials such as an insulation layer and overlying conductive or semiconductive electrode, and capacitors formed from such methods are provided. In one embodiment of forming a uniform cell nitride layer in a capacitor construction, a surface-modifying agent is implanted into exposed surfaces of an insulation layer of a capacitor container by low angle implantation to alter the surface properties of the insulation layer for enhanced nucleation of the depositing cell nitride material, preferably while rotating the substrate for adequate implantation of the modifying substance along the top corner portion of the container. The resulting cell nitride layer has a uniform thickness over the insulation layer and the lower electrode, thus eliminating punch-through and corner leakage problems. The capacitors are particularly useful in fabricating DRAM cells.

4. 发明授权

US06818940B2 Insulated gate bipolar transistor having trench gates of rectangular upper surfaces with different widths 有权
标题翻译：具有不同宽度的矩形上表面的沟槽栅极的绝缘栅双极晶体管
公开(公告)号：US06818940B2
公开(公告)日：2004-11-16
申请号：US10821956
申请日：2004-04-12
申请人： Tadashi Matsuda
发明人： Tadashi Matsuda
IPC分类号： H01L27108
CPC分类号： H01L29/0696 , H01L29/4238 , H01L29/7397
摘要： An insulated gate bipolar transistor includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on a top surface of the first semiconductor layer, a base layer of the first conductivity type formed on a top surface of the second semiconductor layer, a plurality of gate electrodes each of which is buried in a trench with a gate insulation film interposed therebetween, the trench being formed in the base layer to a depth reaching said second semiconductor layer from a surface of the base layer, each the gate electrode having an upper surface of a rectangular pattern with different widths in two orthogonal directions, the gate electrodes being disposed in a direction along a short side of the rectangular pattern, and emitter layers of the second conductivity type formed in the surface of the base layer to oppose both end portions of each the gate electrode in a direction along a long side of the rectangular pattern.
摘要翻译：绝缘栅双极晶体管包括第一导电类型的第一半导体层，形成在第一半导体层的顶表面上的第二导电类型的第二半导体层，形成在第一导电类型的顶表面上的第一导电类型的基极层所述第二半导体层，多个栅极，每个栅电极埋设在沟槽中，栅极绝缘膜插入其间，所述沟槽形成在所述基极层中，从所述基底层的表面到达所述第二半导体层的深度，每个栅电极具有在两个正交方向上具有不同宽度的矩形图案的上表面，栅电极沿着矩形图案的短边方向设置，并且第二导电类型的发射极层形成在所述基底层在沿所述矩形图案的长边的方向上与所述栅电极的两端部相对。

5. 发明授权

US06818937B2 Memory cell having a vertical transistor with buried source/drain and dual gates 失效
标题翻译：具有埋入源极/漏极和双栅极的垂直晶体管的存储单元
公开(公告)号：US06818937B2
公开(公告)日：2004-11-16
申请号：US10162942
申请日：2002-06-04
申请人： Wendell P. Noble , Leonard Forbes , Kie Y. Ahn
发明人： Wendell P. Noble , Leonard Forbes , Kie Y. Ahn
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10891
摘要： An integrated circuit and fabrication method includes a memory cell for a dynamic random access memory (DRAM). Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried first and second gates are provided for each access transistor on opposing sides of the pillars. Buried word lines extend in trenches orthogonal to the bit lines. The buried word lines interconnect ones of the first and second gates. In one embodiment, unitary gates are interposed and shared between adjacent pillars for gating the transistors therein. In another embodiment, separate split gates are interposed between and provided to the adjacent pillars for separately gating the transistors therein. In one embodiment, the memory cell has a surface area that is approximately 4 F2, where F is a minimum feature size. Bulk-semiconductor and semiconductor-on-insulator (SOI) embodiments are provided.
摘要翻译：集成电路和制造方法包括用于动态随机存取存储器（DRAM）的存储单元。垂直取向的存取晶体管形成在掩埋位线上的半导体柱上。在柱的相对侧上为每个存取晶体管提供被埋设的第一和第二栅极。掩埋字线在与位线正交的沟槽中延伸。掩埋字线将第一和第二栅极互连。在一个实施例中，单个门被插入并在相邻支柱之间共享，用于门控其中的晶体管。在另一个实施例中，单独的分离栅极介于并提供给相邻的柱之间，用于单独地将晶体管门控。在一个实施例中，存储器单元具有大约4F 2的表面积，其中F是最小特征尺寸。提供了体半导体和绝缘体上半导体（SOI））实施例。

6. 发明授权

US06818936B2 Scaled EEPROM cell by metal-insulator-metal (MIM) coupling 有权
标题翻译：金属绝缘体金属（MIM）耦合的可扩展EEPROM单元
公开(公告)号：US06818936B2
公开(公告)日：2004-11-16
申请号：US10288197
申请日：2002-11-05
申请人： Chrong Jun Lin , Hsin-Ming Chen
发明人： Chrong Jun Lin , Hsin-Ming Chen
IPC分类号： H01L27108
CPC分类号： H01L28/40 , H01L21/28273 , H01L28/91 , H01L29/42324 , H01L29/66825
摘要： A single-poly EEPROM cell is disclosed with a vertically formed metal-insulator-metal (MIM) coupling capacitor, which serves as a control gate in place of a laterally buried control gate thereby eliminating the problem of junction breakdown, and at the same time reducing the size of the cell substantially. A method of forming the single-poly cell is also disclosed. This is accomplished by forming a floating gate over a substrate with an intervening tunnel oxide and then the MIM capacitor over the floating gate with another intervening dielectric layer between the top metal and the lower metal of the capacitor where the latter metal is connected to the polysilicon floating gate.
摘要翻译：公开了具有垂直形成的金属 - 绝缘体 - 金属（MIM）耦合电容器的单聚电解质电池单元，其用作控制栅极以代替横向埋设的控制栅极，从而消除了结击穿的问题，并且同时基本上减小了细胞的大小。还公开了形成单多晶硅电池的方法。这是通过在衬底上形成具有中间隧道氧化物的浮动栅极，然后在浮动栅极上形成MIM电容器，在电容器的顶部金属和下部金属之间的另一个中间介电层，其中后者金属连接到多晶硅浮动门。

7. 发明授权

US06815746B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06815746B2
公开(公告)日：2004-11-09
申请号：US10268699
申请日：2002-10-11
申请人： Makoto Suzuki , Takafumi Kikuchi , Norihiko Sugita , Seiichi Shirakawa
发明人： Makoto Suzuki , Takafumi Kikuchi , Norihiko Sugita , Seiichi Shirakawa
IPC分类号： H01L27108
CPC分类号： H01L24/06 , B82Y10/00 , G11C11/005 , G11C2207/105 , H01L21/561 , H01L23/50 , H01L23/5386 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06565 , H01L2225/06568 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01055 , H01L2924/01058 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10161 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/30105 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides a small-sized and inexpensive semiconductor device wherein a synchronous dynamic random access memory and a flash memory are built in a single encapsulater. A flash memory chip and a synchronous dynamic random access memory chip (SDRAM chip) are fixed to a main surface of a wiring board in a parallel state, and another SDRAM chip is fixed onto the flash memory chip. Electrodes for the respective semiconductor chips are respectively exposed and these electrodes are connected to their corresponding electrodes of the wiring board. An encapsulater formed of an insulating resin is formed on the main surface side of the wiring board so as to cover wires. Since the encapsulater is formed by cutting a block encapsulater formed by block molding by dicing, the side faces of the encapsulater result in cut surfaces. Bump electrodes are provided on the back surface of the wiring board in an array fashion.
摘要翻译：本发明提供了一种小型且便宜的半导体器件，其中同步动态随机存取存储器和闪速存储器被构建在单个封装器中。闪存芯片和同步动态随机存取存储器芯片（SDRAM芯片）以并行状态固定到布线板的主表面，另一个SDRAM芯片固定到闪存芯片上。分别露出用于各个半导体芯片的电极，并且这些电极连接到其对应的布线板的电极。在布线板的主表面侧形成由绝缘树脂构成的封装体，以覆盖电线。由于密封剂是通过切割由块状模塑形成的块状密封剂形成的，因此密封剂的侧面产生切割面。凸起电极以阵列方式设置在布线板的背面上。

8. 发明授权

US06812493B2 Thin-film semiconductor element and method of producing same 失效
标题翻译：薄膜半导体元件及其制造方法
公开(公告)号：US06812493B2
公开(公告)日：2004-11-02
申请号：US10240648
申请日：2002-10-04
申请人： Mikio Nishio
发明人： Mikio Nishio
IPC分类号： H01L27108
CPC分类号： H01L29/66757 , G02F1/1368 , H01L27/124 , H01L27/3244 , H01L29/78621 , H01L29/78624
摘要： The present invention provides a thin film semiconductor element which is small in area with high on-current enough to be suitable for the power saving, miniaturization, and high definition display of a device. According to the present invention, an outer shape of a semiconductor thin film is processed and regions (a channel region, a source region, and a drain region) in the semiconductor thin film are formed by using, as masks, other element components such as a gate electrode. Specifically, ion-implanted regions are formed by implanting impurity ions into predetermined regions of the semiconductor thin film using, as a mask, the gate electrode overlapped on the thin film via an insulation film. Thereafter, the semiconductor is processed into a predetermined shape by etching using, as masks, previously formed element components such as the gate electrode.
摘要翻译：本发明提供一种薄膜半导体元件，其面积小，具有足够高的导通电流，以适合于器件的省电，小型化和高清晰度显示。根据本发明，对半导体薄膜的外形进行处理，并且通过使用其他元件组件作为掩模来形成半导体薄膜中的区域（沟道区域，源极区域和漏极区域）栅电极。具体地，通过使用绝缘膜将作为掩模的栅电极重叠在薄膜上的杂质离子注入到半导体薄膜的预定区域中，形成离子注入区域。此后，通过使用诸如栅电极的预先形成的元件组件作为掩模，通过蚀刻将半导体处理成预定形状。

9. 发明授权

US06809367B2 Device for interconnecting, in three dimensions, electronic components 有权
标题翻译：用于在三维方面互连电子元件的装置。
公开(公告)号：US06809367B2
公开(公告)日：2004-10-26
申请号：US10149789
申请日：2002-06-17
申请人： Christian Val
发明人： Christian Val
IPC分类号： H01L27108
CPC分类号： H01L25/50 , H01L23/5222 , H01L24/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/01047 , H01L2924/01056 , H01L2924/01058 , H01L2924/01061 , H01L2924/01074 , H01L2924/01082 , H01L2924/01087 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H05K1/0218 , H05K1/0231 , H05K1/184 , H05K1/185 , H05K3/045 , H05K3/403 , H05K2201/0715 , H05K2201/09181 , H05K2201/09645 , H05K2201/10643 , Y10T29/49146 , Y10T29/49165 , H01L2924/00
摘要： The invention relates to a device for interconnecting, in three dimensions, electronic components. In order to decrease the parasitic capacitances between the connections and shielding of the device, metallized grooves are cut in the block of stacked circuits, just clipping the connection to conductors of which are set back from the corresponding face of the block. The assembly is then encapsulated with resin and shielded by metallization. The invention is especially applicable to producing electronic systems in three dimensions with a small size.
摘要翻译：本发明涉及一种用于在三维中互连电子部件的装置。为了减小连接之间的寄生电容和器件的屏蔽，金属化的沟槽被切割在堆叠电路的块中，仅限制与导体相对应的块的相应面的连接。然后将组件用树脂包封并通过金属化屏蔽。本发明特别适用于制造具有小尺寸的三维电子系统。

10. 发明授权

US06806528B2 Phase-changeable memory devices having phase-changeable material regions with lateral contacts and methods of fabrication therefor 有权
标题翻译：具有具有侧向接触的相变材料区域的相变存储器件及其制造方法
公开(公告)号：US06806528B2
公开(公告)日：2004-10-19
申请号：US10647700
申请日：2003-08-25
申请人： Se-Ho Lee , Young-Nam Hwang
发明人： Se-Ho Lee , Young-Nam Hwang
IPC分类号： H01L27108
CPC分类号： H01L45/06 , H01L27/105 , H01L27/2436 , H01L45/1226 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： A phase-changeable memory device comprises a substrate and an access transistor formed in and/or on the substrate. Laterally spaced apart first and second conductive patterns are disposed on the substrate and have opposing sidewalls. A conductor electrically connects the first conductive region to a source/drain region of the access transistor. A phase-changeable material region is disposed between the first and second conductive patterns and contacts the opposing sidewalls of the first and second conductive patterns. Contact areas between the conductive patterns and the phase-changeable material region are preferably substantially smaller than contact areas at which the conductive patterns contact conductors (e.g., vias) connected thereto, such that high current densities may be developed in the phase-changeable material. Methods of fabricating such devices are also discussed.
摘要翻译：相变存储器件包括衬底和形成在衬底中和/或衬底上的存取晶体管。间隔开的第一和第二导电图案设置在基板上并且具有相对的侧壁。导体将第一导电区域电连接到存取晶体管的源极/漏极区域。相变材料区域设置在第一和第二导电图案之间并与第一和第二导电图案的相对的侧壁接触。导电图案和相变材料区域之间的接触面积优选地基本上小于导电图案与其连接的导体（例如，通孔）的接触面积，使得可在相变材料中形成高电流密度。还讨论了制造这种装置的方法。

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