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61. 发明申请

US20070293016A1 SEMICONDUCTOR STRUCTURE INCLUDING ISOLATION REGION WITH VARIABLE LINEWIDTH AND METHOD FOR FABRICATION THEROF 审中-公开
标题翻译：包括具有可变线性的分离区域的半导体结构及其制造方法
公开(公告)号：US20070293016A1
公开(公告)日：2007-12-20
申请号：US11424076
申请日：2006-06-14
申请人： Zhijiong Luo , Hung Y. Ng , Nivo Rovedo , Phung T. Nguyen , William C. Wille , Richard Lindsay , Zhao Lun , Yung Fu Chong , Siddhartha Panda
发明人： Zhijiong Luo , Hung Y. Ng , Nivo Rovedo , Phung T. Nguyen , William C. Wille , Richard Lindsay , Zhao Lun , Yung Fu Chong , Siddhartha Panda
IPC分类号： H01L21/76
CPC分类号： H01L21/823892 , H01L21/76218 , H01L21/76232 , H01L21/823878
摘要： A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within the doped region than within the epitaxial region. A method for fabricating the semiconductor structure provides for forming the doped region prior to the epitaxial region. The doped region may be formed with reduced well implant energy and reduced lateral straggle. The final isolation region with the variable linewidth provides a greater effective isolation depth than an actual trench isolation depth.
摘要翻译：半导体结构包括具有位于其中的掺杂区的基极半导体衬底和位于掺杂区上方的外延区。半导体结构还包括位于掺杂区和外延区的最后隔离区。最后的隔离区域在掺杂区域内具有比外延区域内更大的线宽。制造半导体结构的方法提供了在外延区之前形成掺杂区。掺杂区域可以形成为具有减少的良好注入能量和减小的横向分层。具有可变线宽的最终隔离区域提供比实际沟槽隔离深度更大的有效隔离深度。

62. 发明申请

US20070281413A1 N-CHANNEL MOSFETS COMPRISING DUAL STRESSORS, AND METHODS FOR FORMING THE SAME 有权
标题翻译：包含双重压力机的N沟道MOSFET及其形成方法
公开(公告)号：US20070281413A1
公开(公告)日：2007-12-06
申请号：US11840795
申请日：2007-08-17
申请人： Jinghong Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
发明人： Jinghong Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/324 , H01L21/823807 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S257/90
摘要： The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.
摘要翻译：本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。具体地说，n-FET包括第一和第二图案应力层，它们都包含碳取代和拉伸应力单晶半导体。第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

63. 发明申请

US20070205469A1 Integrated circuit isolation system 有权
标题翻译：集成电路隔离系统
公开(公告)号：US20070205469A1
公开(公告)日：2007-09-06
申请号：US11369239
申请日：2006-03-06
申请人： Yung Chong , Zhijiong Luo
发明人： Yung Chong , Zhijiong Luo
IPC分类号： H01L29/76
CPC分类号： H01L21/76232 , H01L21/823481
摘要： A method of manufacturing a self-aligned inverted T-shaped isolation structure. An integrated circuit isolation system including providing a substrate, forming a base insulator region in the substrate, and depositing an insulator column having a narrower width than the base insulator region on the base insulator region.
摘要翻译：一种制造自对准倒置T形隔离结构的方法。一种集成电路隔离系统，包括提供衬底，在所述衬底中形成基极绝缘体区域，以及沉积具有比所述基极绝缘体区域上的所述基底绝缘体区域窄的宽度的绝缘体柱。

64. 发明申请

US20060121662A1 METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES 有权
公开(公告)号：US20060121662A1
公开(公告)日：2006-06-08
申请号：US10904884
申请日：2004-12-02
申请人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , John Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James Nakos , An Steegen , Clement Wann
发明人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , John Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James Nakos , An Steegen , Clement Wann
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835
摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

65. 发明授权

US10096717B2 MOSFET and method for manufacturing the same 有权
公开(公告)号：US10096717B2
公开(公告)日：2018-10-09
申请号：US13510407
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/336 , H01L29/786 , H01L21/265 , H01L29/66 , H01L21/74
摘要： The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; and a channel region in the semiconductor layer and located between the source region and the drain region, wherein the MOSFET further comprises a back gate which is located in the semiconductor substrate and has a first doped region as a lower portion of the back gate and a second doped region as an upper portion of the back gate, and the second doped region of the back gate is self-aligned with the gate stack. The MOSFET can adjust a threshold voltage by changing doping type and doping concentration of the back gate.

66. 发明授权

US09583622B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09583622B2
公开(公告)日：2017-02-28
申请号：US14407263
申请日：2012-07-06
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin , Qingqing Liang
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin , Qingqing Liang
IPC分类号： H01L27/12 , H01L29/78 , H01L29/66 , H01L29/732 , H01L29/737 , H01L29/786 , H01L21/02 , H01L21/265 , H01L21/306 , H01L21/324 , H01L21/762 , H01L29/04 , H01L29/06 , H01L29/16 , H01L29/161
CPC分类号： H01L29/7849 , H01L21/0245 , H01L21/02513 , H01L21/265 , H01L21/30604 , H01L21/324 , H01L21/76224 , H01L21/76254 , H01L21/76283 , H01L29/04 , H01L29/0653 , H01L29/16 , H01L29/161 , H01L29/66242 , H01L29/66272 , H01L29/66568 , H01L29/66772 , H01L29/732 , H01L29/7371 , H01L29/78654
摘要： The present invention discloses a semiconductor structure and a method for manufacturing the same, which comprises providing a substrate, and forming a stress layer, a buried oxide layer, and an SOI layer on the substrate; forming a doped region of the stress layer arranged in a specific position in the stress layer; forming an oxide layer and a nitride layer on the SOI layer, and forming a first trench that etches the nitride layer, the oxide layer, the SOI layer, and the buried oxide layer, and stops on the upper surface of the stress layer, and exposes at least part of the doped region of the stress layer; forming a cavity by wet etching through the first trench to remove the doped region of the stress layer; forming a polycrystalline silicon region of the stress layer and a second trench by filling the cavity with polycrystalline silicon and etching back; forming an isolation region by filling the second trench. The semiconductor structure and the method for manufacturing the same disclosed in the present invention provide a favorable stress for the channel of the semiconductor device by introducing a stress layer and a stress induced zone set at specific positions depending on device type to help improving the performance of the semiconductor device.
摘要翻译：本发明公开了一种半导体结构及其制造方法，其特征在于，在基板上设置基板，形成应力层，埋入氧化物层，SOI层，在应力层中形成布置在特定位置的应力层的掺杂区域; 在所述SOI层上形成氧化物层和氮化物层，形成蚀刻所述氮化物层，所述氧化物层，所述SOI层和所述埋入氧化物层的第一沟槽，并停止在所述应力层的上表面上，以及暴露应力层的掺杂区域的至少一部分; 通过所述第一沟槽的湿蚀刻形成空腔以移除所述应力层的掺杂区域; 通过用多晶硅填充空腔并回蚀而形成应力层的多晶硅区域和第二沟槽; 通过填充第二沟槽形成隔离区域。在本发明中公开的半导体结构及其制造方法通过根据器件类型在特定位置引入应力层和应力诱导区域来为半导体器件的沟道提供有利的应力，以有助于提高半导体器件。

67. 发明授权

US09548317B2 FDSOI semiconductor structure and method for manufacturing the same 有权
标题翻译： FDSOI半导体结构及其制造方法
公开(公告)号：US09548317B2
公开(公告)日：2017-01-17
申请号：US14397586
申请日：2012-05-22
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/84 , H01L27/12 , H01L29/66 , H01L29/786 , H01L21/02 , H01L21/266 , H01L21/306 , H01L21/308 , H01L21/768 , H01L29/78 , H01L21/74 , H01L21/265 , H01L29/165
CPC分类号： H01L27/1203 , H01L21/02529 , H01L21/02532 , H01L21/2652 , H01L21/266 , H01L21/30604 , H01L21/3081 , H01L21/743 , H01L21/76897 , H01L21/84 , H01L29/165 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/78 , H01L29/78612 , H01L29/78648
摘要： The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate, which comprises upwards in order a base layer, a buried isolation layer, a buried ground layer, an ultra-thin insulating buried layer and a surface active layer; implementing ion implantation doping to the buried ground layer; forming a gate stack, sidewall spacers and source/drain regions on the substrate; forming a mask layer on the substrate that covers the gate stack and the source/drain regions, and etching the mask layer to expose the source region; etching the source region and the ultra-thin insulating buried layer under the source region to form an opening that exposes the buried ground layer; filling the opening through epitaxial process to form a contact plug for the buried ground layer. Accordingly, the present invention further provides a semiconductor structure. The present invention proposes formation of a buried ground layer contact plug, which then connects buried ground layer electrically to source region, thereby enhancing control capabilities of a semiconductor device over threshold voltages, suppressing short-channel effects and improving device performance; whereas no independent contact is required to build for the buried ground layer, which then saves device area and simplifies manufacturing process accordingly.
摘要翻译：本发明提供了一种制造半导体结构的方法，其包括以下步骤：提供基底，其基本层向上依次包括掩埋隔离层，埋地层，超薄绝缘掩埋层和表面活性层对埋地层进行离子注入掺杂; 在衬底上形成栅极堆叠，侧壁间隔物和源极/漏极区域; 在覆盖栅极堆叠和源极/漏极区域的衬底上形成掩模层，并蚀刻掩模层以暴露源极区域; 蚀刻源极区域下的源极区域和超薄绝缘掩埋层，形成暴露埋入地层的开口; 通过外延工艺填充开口以形成埋地层的接触塞。因此，本发明还提供一种半导体结构。本发明提出了一种掩埋地层接触塞的形成，其然后将掩埋地层电连接到源极区，从而提高半导体器件在阈值电压上的控制能力，抑制短沟道效应并提高器件性能; 而不需要独立的接触来构建埋地层，从而节省设备面积并相应地简化制造过程。

68. 发明授权

US09087691B2 Method for manufacturing graphene nano-ribbon, mosfet and method for manufacturing the same 有权
标题翻译：石墨烯纳米带的制造方法，其制造方法及其制造方法
公开(公告)号：US09087691B2
公开(公告)日：2015-07-21
申请号：US13510390
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/20 , H01L21/36 , H01L21/02 , H01L29/775 , H01L29/06 , H01L29/16 , H01L29/20 , H01L29/66 , H01L29/786 , B82Y10/00 , B82Y40/00 , B82Y30/00
CPC分类号： H01L21/0242 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/02422 , H01L21/02488 , H01L21/02491 , H01L21/02507 , H01L21/02527 , H01L21/02639 , H01L29/0673 , H01L29/1606 , H01L29/2003 , H01L29/66742 , H01L29/775 , H01L29/78684 , H01L29/78696
摘要： A MOSFET with a graphene nano-ribbon, and a method for manufacturing the same are provided. The MOSFET comprises an insulating substrate; and an oxide protection layer on the insulating substrate. At least one graphene nano-ribbon is embedded in the oxide protection layer and has a surface which is exposed at a side surface of the oxide protection layer. A channel region is provided in each of the at least one graphene nano-ribbon. A source region and a drain regions are provided in each of the at least one graphene nano-ribbon. The channel region is located between the source region and the drain region. A gate dielectric is positioned on the at least one graphene nano-ribbon. A gate conductor on the gate dielectric. A source and drain contacts contact the source region and the drain region respectively on the side surface of the oxide protection layer.
摘要翻译：提供了具有石墨烯纳米带的MOSFET及其制造方法。 MOSFET包括绝缘基板; 和绝缘基板上的氧化物保护层。至少一个石墨烯纳米带被嵌入在氧化物保护层中并且具有暴露在氧化物保护层的侧表面的表面。在所述至少一个石墨烯纳米带的每个中设置有沟道区。在所述至少一个石墨烯纳米带的每一个中设置源极区和漏极区。沟道区位于源区和漏区之间。栅电介质位于至少一个石墨烯纳米带上。栅极电介质上的栅极导体。源极和漏极触点分别在氧化物保护层的侧表面上接触源极区域和漏极区域。

69. 发明授权

US09048286B2 Substrate for integrated circuit and method for forming the same 有权
标题翻译：集成电路基板及其形成方法
公开(公告)号：US09048286B2
公开(公告)日：2015-06-02
申请号：US13159351
申请日：2011-06-13
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76232 , H01L21/7624 , H01L21/76283
摘要： The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer.
摘要翻译：本发明涉及IC的基板及其制造方法。该方法包括以下步骤：在体硅材料上形成硬掩模层; 蚀刻硬掩模层和体硅材料以形成用于至少一个沟槽的浅沟槽隔离的第一部分; 在所述至少一个沟槽的侧壁上形成电介质膜; 进一步蚀刻体硅材料以加深所述至少一个沟槽，以便形成所述至少一个沟槽的第二部分; 在沟槽的第二部分之间的体硅材料的部分和沟槽的第二部分和体硅衬底的侧表面之间的体硅材料的部分完全氧化或氮化; 在所述至少一个沟槽的第一和第二部分中填充介电材料; 并除去硬掩模层。

70. 发明授权

US09018739B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09018739B2
公开(公告)日：2015-04-28
申请号：US13060468
申请日：2010-09-25
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L29/04 , H01L29/78 , H01L29/10 , H01L29/165 , H01L29/49 , H01L29/51 , H01L29/66
CPC分类号： H01L29/7834 , H01L29/045 , H01L29/105 , H01L29/1054 , H01L29/1083 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/66651
摘要： The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate; a first semiconductor layer on the semiconductor substrate; a second semiconductor layer surrounding the first semiconductor layer; a high k dielectric layer and a gate conductor formed on the first semiconductor layer; source/drain regions formed in the second semiconductor layer, wherein the second semiconductor layer has a slant sidewall in contact with the first semiconductor layer. The semiconductor device has an increased output current, an increased operating speed, and a reduced power consumption due to the channel region of high mobility.
摘要翻译：本申请公开了一种半导体器件及其制造方法。半导体器件包括半导体衬底; 半导体衬底上的第一半导体层; 围绕所述第一半导体层的第二半导体层; 形成在第一半导体层上的高k电介质层和栅极导体; 形成在第二半导体层中的源/漏区，其中第二半导体层具有与第一半导体层接触的倾斜侧壁。半导体器件具有增加的输出电流，增加的操作速度以及由于高移动性的沟道区域而导致的功率消耗降低。

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