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61. 发明申请

US20140108688A1 Fabric Delivered Interrupts 有权
标题翻译：织物交付中断
公开(公告)号：US20140108688A1
公开(公告)日：2014-04-17
申请号：US13653151
申请日：2012-10-16
申请人： APPLE INC.
发明人： Manu Gulati , Erik P. Machnicki , Deniz Balkan
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F13/26 , Y02D10/14
摘要： In an embodiment, a system includes at least one peripheral device, an interrupt controller, a memory controller, at least one CPU, and an interrupt message circuit coupled to the peripheral device. The interrupt message circuit may be coupled to receive the interrupt signal from the peripheral device, and may be configured to generate an interrupt message for transmission on a communication fabric. In some embodiments, there may be multiple peripherals which have independent paths through the fabric for memory operations to the memory controller. Each such peripheral may be coupled to an instance of the interrupt message circuit. In an embodiment, the interrupt is level sensitive. The interrupt message circuit may be configured to transmit interrupt set messages an interrupt clear messages to the interrupt controller, to indicate the levels.
摘要翻译：在一个实施例中，系统包括耦合到外围设备的至少一个外围设备，中断控制器，存储器控制器，至少一个CPU以及中断消息电路。中断消息电路可以被耦合以从外围设备接收中断信号，并且可以被配置为生成用于在通信结构上传输的中断消息。在一些实施例中，可以存在多个外围设备，其具有通过该结构的独立路径，用于存储器操作到存储器控制器。每个这样的外设可以耦合到中断消息电路的一个实例。在一个实施例中，中断是电平敏感的。中断消息电路可以被配置为向中断控制器发送中断设置消息中断清除消息以指示电平。

62. 发明申请

US20140089682A1 Security Enclave Processor for a System on a Chip 有权
标题翻译：用于芯片系统的安全处理器
公开(公告)号：US20140089682A1
公开(公告)日：2014-03-27
申请号：US13626566
申请日：2012-09-25
申请人： APPLE INC.
发明人： Manu Gulati , Michael J. Smith , Shu-Yi Yu
IPC分类号： G06F21/00
CPC分类号： G06F21/72 , G06F21/575
摘要： An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory.
摘要翻译： SOC实现安全飞地处理器（SEP）。 SEP可以包括处理器和一个或多个安全外设。 SEP可以与SOC的其余部分隔离（例如SOC中的一个或多个中央处理单元（CPU），或SOC中的应用处理器（AP））。对SEP的访问可以由硬件严格控制。例如，描述了CPU / AP仅能访问SEP中的邮箱位置的机制。 CPU / AP可以向邮箱写入消息，SEP可以读取并响应。在一些实施例中，SEP可以包括以下一个或多个：使用包装密钥的安全密钥管理，引导和/或电源管理的SEP控制以及存储器中的单独的信任区域。

63. 发明申请

US20220058292A1 Unified Addressable Memory 有权
公开(公告)号：US20220058292A1
公开(公告)日：2022-02-24
申请号：US17469591
申请日：2021-09-08
申请人： Apple Inc.
发明人： Manu Gulati , Joseph Sokol, JR. , Jeffrey R. Wilcox , Bernard J. Semeria , Michael J. Smith
IPC分类号： G06F21/72 , G06F12/02 , G06F12/1027 , G06F12/14 , G06F21/78 , H04L9/08
摘要： In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

64. 发明授权

US11049503B2 Always-on audio control for mobile device 有权
公开(公告)号：US11049503B2
公开(公告)日：2021-06-29
申请号：US16786127
申请日：2020-02-10
申请人： Apple Inc.
发明人： Timothy J. Millet , Manu Gulati , Michael F. Culbert
IPC分类号： G10L15/22 , G10L15/28 , G06F3/16 , G06F1/3228 , G06F1/3287 , G06F1/32 , G10L15/08 , G10L25/48
摘要： In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

65. 发明授权

US10802968B2 Processor to memory with coherency bypass 有权
公开(公告)号：US10802968B2
公开(公告)日：2020-10-13
申请号：US14705506
申请日：2015-05-06
申请人： Apple Inc.
发明人： Sukalpa Biswas , Harshavardhan Kaushikkar , Munetoshi Fukami , Gurjeet S. Saund , Manu Gulati , Shinye Shiu
IPC分类号： G06F12/0815 , G06F12/0813 , G06F9/52
摘要： An apparatus for processing memory requests from a functional unit in a computing system is disclosed. The apparatus may include an interface that may be configured to receive a request from the functional. Circuitry may be configured initiate a speculative read access command to a memory in response to a determination that the received request is a request for data from the memory. The circuitry may be further configured to determine, in parallel with the speculative read access, if the speculative read will result in an ordering or coherence violation.

66. 发明申请

US20190378514A1 Always-On Audio Control for Mobile Device 审中-公开
公开(公告)号：US20190378514A1
公开(公告)日：2019-12-12
申请号：US16546574
申请日：2019-08-21
申请人： Apple Inc.
发明人： Timothy J. Millet , Manu Gulati , Michael F. Culbert
IPC分类号： G10L15/28 , G06F1/3228 , G06F1/3287 , G06F1/32 , G10L15/22 , G06F3/16
摘要： In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

67. 发明申请

US20190286519A1 Storing Address of Spare in Failed Memory Location 审中-公开
公开(公告)号：US20190286519A1
公开(公告)日：2019-09-19
申请号：US16405362
申请日：2019-05-07
申请人： Apple Inc.
发明人： Manu Gulati , Sukalpa Biswas , Jeffrey R. Wilcox , Farid Nemati
IPC分类号： G06F11/10 , G11C29/52
摘要： In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.

68. 发明授权

US10298511B2 Communication queue management system 有权
公开(公告)号：US10298511B2
公开(公告)日：2019-05-21
申请号：US15246046
申请日：2016-08-24
申请人： Apple Inc.
发明人： Manu Gulati , Christopher D. Shuler , Benjamin K. Dodge , Thejasvi M. Vijayaraj , Harshavardhan Kaushikkar , Yang Yang , Rong Z. Hu , Srinivasa R. Sridharan , Wolfgang H. Klingauf , Neeraj Parik
IPC分类号： H04W72/12 , H04L12/863 , G06F13/16 , G06F9/54 , H04L12/865
摘要： In some embodiments, a system includes a memory system, plurality of computing devices, and plurality of queues. The plurality of computing devices perform actions dependent on data stored at the memory device, where traffic between the plurality of computing devices and the memory device has at least a first priority level and a second priority level. The first priority level is higher than the second priority level. The plurality of queues pass data between the memory device and the plurality of computing devices. A particular queue allocates a first portion of the particular queue to traffic having the first priority level and allocates a second portion of the particular queue to traffic having the first priority level and to traffic having the second priority level.

69. 发明申请

US20180350369A1 Always-On Audio Control for Mobile Device 审中-公开
公开(公告)号：US20180350369A1
公开(公告)日：2018-12-06
申请号：US16101603
申请日：2018-08-13
申请人： Apple Inc.
发明人： Timothy J. Millet , Manu Gulati , Michael F. Culbert
IPC分类号： G10L15/28 , G06F3/16 , G06F1/32 , G10L15/22 , G10L25/48 , G10L15/08
CPC分类号： G10L15/28 , G06F1/32 , G06F1/3228 , G06F1/3287 , G06F3/165 , G10L15/22 , G10L25/48 , G10L2015/088 , Y02D10/171
摘要： In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

70. 发明申请

US20180313673A1 System on a Chip with Always-On Processor 审中-公开
公开(公告)号：US20180313673A1
公开(公告)日：2018-11-01
申请号：US16019087
申请日：2018-06-26
申请人： Apple Inc.
发明人： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
IPC分类号： G01D9/00 , G06F1/32 , G06F13/16
CPC分类号： G01D9/00 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F13/1689 , Y02D10/122 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

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