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61. 发明授权

US08225069B2 Control of on-die system fabric blocks 有权
标题翻译：管芯系统结构块的控制
公开(公告)号：US08225069B2
公开(公告)日：2012-07-17
申请号：US12415941
申请日：2009-03-31
申请人： Zhen Fang , Mahesh Wagh , Jasmin Ajanovic , Michael E Espig , Ravishankar Iyer
发明人： Zhen Fang , Mahesh Wagh , Jasmin Ajanovic , Michael E Espig , Ravishankar Iyer
IPC分类号： G06F12/00
CPC分类号： G06F12/1036 , G06F12/0292 , G06F12/0888 , G06F12/10 , G06F12/1027 , G06F2212/206
摘要： Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a user-level request and a logic circuitry (e.g., present in an OSF) may determine the physical address from the shadow address. Other embodiments are also disclosed.
摘要翻译：描述了用于控制片上系统结构（OSF）块的方法和装置。在一个实施例中，响应于用户级请求可以存储对应于物理地址的影子地址，并且逻辑电路（例如，存在于OSF中）可以从影子地址确定物理地址。还公开了其他实施例。

62. 发明申请

US20100332686A1 WRITE COMBINING PROTOCOL BETWEEN PROCESSORS AND CHIPSETS 有权
标题翻译：处理器和芯片之间的写组合协议
公开(公告)号：US20100332686A1
公开(公告)日：2010-12-30
申请号：US12689899
申请日：2010-01-19
申请人： Kenneth C. Creta , Aaron T. Spink , Lance E. Hacking , Sridhar Muthrasanallur , Jasmin Ajanovic
发明人： Kenneth C. Creta , Aaron T. Spink , Lance E. Hacking , Sridhar Muthrasanallur , Jasmin Ajanovic
IPC分类号： G06F3/00 , G06F12/08 , G06F5/00
CPC分类号： G06F13/4027
摘要： Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device without the need for proprietary software and specialized registers within the I/O device.
摘要翻译：处理写事务的系统和方法提供了根据I / O集线器和处理器之间的协议在输入/输出（I / O）集线器上组合写事务。与写入事务相关的数据可以刷新到I / O设备，而不需要I / O设备内的专有软件和专用寄存器。

63. 发明授权

US07849252B2 Providing a prefix for a packet header 有权
标题翻译：为数据包头提供前缀
公开(公告)号：US07849252B2
公开(公告)日：2010-12-07
申请号：US12156409
申请日：2008-05-30
申请人： Mahesh Wagh , Jasmin Ajanovic
发明人： Mahesh Wagh , Jasmin Ajanovic
IPC分类号： G06F13/00
CPC分类号： H04L69/22
摘要： In one embodiment, the present invention includes a method for generating a prefix header with an opcode field and a prefix specific field for a first packet to be transmitted from a transmitter, and transmitting the packet from the transmitter with the prefix header, which is followed by a header. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于产生具有操作码字段的前缀报头和用于要从发送器发送的第一分组的前缀特定字段的方法，并且从发送器发送具有跟随的前缀报头的分组通过标题描述和要求保护其他实施例。

64. 发明授权

US07676603B2 Write combining protocol between processors and chipsets 失效
标题翻译：在处理器和芯片组之间写入组合协议
公开(公告)号：US07676603B2
公开(公告)日：2010-03-09
申请号：US10828872
申请日：2004-04-20
申请人： Kenneth C. Creta , Aaron T. Spink , Lance E. Hacking , Sridhar Muthrasanallur , Jasmin Ajanovic
发明人： Kenneth C. Creta , Aaron T. Spink , Lance E. Hacking , Sridhar Muthrasanallur , Jasmin Ajanovic
IPC分类号： G06F3/00
CPC分类号： G06F13/4027
摘要： Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device without the need for proprietary software and specialized registers within the I/O device.
摘要翻译：处理写事务的系统和方法提供了根据I / O集线器和处理器之间的协议在输入/输出（I / O）集线器上组合写事务。与写入事务相关的数据可以刷新到I / O设备，而不需要I / O设备内的专有软件和专用寄存器。

65. 发明授权

US06976115B2 Peer-to-peer bus segment bridging 有权
标题翻译：点对点公交线路桥接
公开(公告)号：US06976115B2
公开(公告)日：2005-12-13
申请号：US10112344
申请日：2002-03-28
申请人： Kenneth Creta , Jasmin Ajanovic , Joseph Bennett
发明人： Kenneth Creta , Jasmin Ajanovic , Joseph Bennett
IPC分类号： G06F3/00 , G06F13/36 , G06F13/40
CPC分类号： G06F13/4031
摘要： A method and apparatus are described for facilitating proper ordering of peer-to-peer communications between bridged bus segments. According to one embodiment of the present invention a fence command is issued when a peer-to-peer communication between devices on separate bus segments connected on the same side of a bridge is detected. The fence command is inserted into a plurality of buffers in an I/O hub corresponding to the bus segments to force temporary ordering across all pipes of the I/O hub. The hub prohibits processing of subsequent commands from a buffer once a fence command has been read from that buffer until a corresponding fence command is read from all other buffers in the plurality of buffers therby assuring proper ordering of the peer-to-peer communication.
摘要翻译：描述了一种用于促进桥接总线段之间的对等通信的正确排序的方法和装置。根据本发明的一个实施例，当检测到连接在桥的同一侧上的分开的总线段上的设备之间的对等通信时，发出围栏命令。 fence命令插入到与总线段相对应的I / O集线器中的多个缓冲器中，以迫使临时排序I / O集线器的所有管道。一旦从该缓冲器读取了fence命令，则该中继器禁止处理来自缓冲器的后续命令，直到从多个缓冲器中的所有其他缓冲器读取相应的fence命令，从而确保对等通信的正确排序。

66. 发明授权

US06370624B1 Configurable page closing method and apparatus for multi-port host bridges 失效
标题翻译：用于多端口主机桥的可配置的页面关闭方法和装置
公开(公告)号：US06370624B1
公开(公告)日：2002-04-09
申请号：US09712010
申请日：2000-11-13
申请人： Jasmin Ajanovic , Michael W. Williams , Robert N. Murdoch
发明人： Jasmin Ajanovic , Michael W. Williams , Robert N. Murdoch
IPC分类号： G06F1200
CPC分类号： G06F12/0215
摘要： A page closing method and apparatus for multi-port host bridges. According to a method disclosed, a plurality of memory access commands are received from a plurality of command ports. A command is selected from one of the command ports to be the next memory access command executed. A number of pages of memory are closed in response to the command selected as the next memory access command. The number of pages closed is determined at least in part on which command port provides the next memory access command.
摘要翻译：一种用于多端口主机桥的页面关闭方法和装置。根据所公开的方法，从多个命令端口接收多个存储器访问命令。从命令端口之一中选择一个命令作为执行的下一个存储器访问命令。响应于作为下一个存储器访问命令选择的命令，多个页面的存储器被关闭。关闭的页数至少部分地由哪个命令端口提供下一个存储器访问命令确定。

67. 发明授权

US06199145B1 Configurable page closing method and apparatus for multi-port host bridges 失效
标题翻译：用于多端口主机桥的可配置的页面关闭方法和装置
公开(公告)号：US06199145B1
公开(公告)日：2001-03-06
申请号：US09032434
申请日：1998-02-27
申请人： Jasmin Ajanovic , Michael W. Williams , Robert N. Murdoch
发明人： Jasmin Ajanovic , Michael W. Williams , Robert N. Murdoch
IPC分类号： G06F1200
CPC分类号： G06F12/0215
摘要： A page closing method and apparatus for multi-port host bridges. According to a method disclosed, a plurality of memory access commands are received from a plurality of command ports. A command is selected from one of the command ports to be the next memory access command executed. A number of pages of memory are closed in response to the command selected as the next memory access command. The number of pages closed is determined at least in part on which command port provides the next memory access command.
摘要翻译：一种用于多端口主机桥的页面关闭方法和装置。根据所公开的方法，从多个命令端口接收多个存储器访问命令。从命令端口之一中选择一个命令作为执行的下一个存储器访问命令。响应于作为下一个存储器访问命令选择的命令，多个页面的存储器被关闭。关闭的页数至少部分地由哪个命令端口提供下一个存储器访问命令确定。

68. 发明授权

US6026455A Architecture and method for providing guaranteed access for a retrying bus master to a data transfer bridge connecting two buses in a computer system 失效
标题翻译：用于为重试总线主机向计算机系统中连接两条总线的数据传输桥提供有保障的访问的架构和方法
公开(公告)号：US6026455A
公开(公告)日：2000-02-15
申请号：US201817
申请日：1994-02-24
申请人： Nilesh Shah , James Coke , Jasmin Ajanovic , Dahmane Dahmani , Rajeev Prasad
发明人： Nilesh Shah , James Coke , Jasmin Ajanovic , Dahmane Dahmani , Rajeev Prasad
IPC分类号： G06F13/40 , G06F13/36
CPC分类号： G06F13/4031
摘要： A bridge circuit adapted to be associated with a PCI and a secondary bus circuits which bridge circuit includes circuitry for storing an indication that a particular PCI bus master has attempted an access of the secondary bus and has been forced to retry that access, circuitry for masking any retry until the bus is again available, and circuitry for providing an interval during which a retrying PCI bus master is guaranteed access to the secondary bus in favor of a bus master on the secondary bus after the bus is relinquished so that a sequence of retry operations causing a loss of bandwidth on the PCI bus is not generated.
摘要翻译：适于与PCI和辅助总线电路相关联的桥接电路，桥接电路包括用于存储特定PCI总线主机尝试访问辅助总线并已被迫重试该接入的指示的电路，用于屏蔽的电路任何重试直到总线再次可用，以及用于提供间隔时间的电路，在该间隔期间，重试PCI总线主机被保证访问辅助总线，有利于在总线被放弃之后辅助总线上的总线主机，使得重试次序不会产生导致PCI总线带宽损失的操作。

69. 发明授权

US5666556A Method and apparatus for redirecting register access requests wherein the register set is separate from a central processing unit 失效
标题翻译：用于重定向寄存器访问请求的方法和装置，其中寄存器集与中央处理单元分离
公开(公告)号：US5666556A
公开(公告)日：1997-09-09
申请号：US710572
申请日：1996-09-19
申请人： Narendra Khandekar , Jasmin Ajanovic
发明人： Narendra Khandekar , Jasmin Ajanovic
IPC分类号： G06F13/40 , G06F12/06
CPC分类号： G06F13/4027
摘要： A register address space is defined with a capacity large enough to accommodate substantial growth in the number of required registers. Unused register locations are reserved for future use. Access requests directed to reserved addresses are redirected to a physical register containing the same stored value that would be returned if a physical register were associated with the reserved address to which the access was originally directed. The physical register is separate from any central processing unit.
摘要翻译：寄存器地址空间被定义为具有足够大的容量以容纳所需寄存器的数量的显着增长。未使用的寄存器位置保留供将来使用。指向保留地址的访问请求被重定向到物理寄存器，该物理寄存器包含与物理寄存器与访问最初指向的保留地址相关联时返回的相同存储值。物理寄存器与任何中央处理单元分开。

70. 发明申请

US20130132683A1 PCI EXPRESS ENHANCEMENTS AND EXTENSIONS 审中-公开
公开(公告)号：US20130132683A1
公开(公告)日：2013-05-23
申请号：US13713614
申请日：2012-12-13
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

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