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    • 61. 发明授权
    • External bus arbitration technique for multicore DSP device
    • 多核DSP设备的外部总线仲裁技术
    • US07006521B2
    • 2006-02-28
    • US10007840
    • 2001-11-08
    • Duy Q. NguyenHarland Glenn HopkinsJay B. ReimerYi LuoTai H. NguyenKevin A. McGonagle
    • Duy Q. NguyenHarland Glenn HopkinsJay B. ReimerYi LuoTai H. NguyenKevin A. McGonagle
    • H04J3/02
    • G06F13/364
    • A digital signal processing system includes multiple processor subsystems, an external input/output port (XPORT), and an XPORT arbiter. The processor subsystems each include a processor core and a DMA controller. The XPORT arbiter arbitrates between the processor cores and between the DMA controllers, and further arbitrates between processor control or DMA control of the XPORT. Upon a request signal from a DMA controller, the XPORT arbiter asserts a hold signal to the processor cores. The processor cores respond by asserting a hold acknowledge signal. A processor core will delay the hold acknowledge signal until through with the XPORT. The arbiter, then asserts a grant signal to the DMA controller requesting access. The arbiter may assert a grant signal to a processor core requesting access. However, the processor core's access will be stalled as long as the hold signal is asserted.
    • 数字信号处理系统包括多个处理器子系统,外部输入/输出端口(XPORT)和XPORT仲裁器。 处理器子系统各自包括处理器核心和DMA控制器。 XPORT仲裁器在处理器内核和DMA控制器之间进行仲裁,并进一步对XPORT的处理器控制或DMA控制进行仲裁。 根据来自DMA控制器的请求信号,XPORT仲裁器向处理器核心发出保持信号。 处理器核心通过置位保持确认信号来响应。 处理器内核将延迟保持确认信号,直到通过XPORT。 仲裁器然后向DMA控制器发出授权信号请求访问。 仲裁器可以向请求访问的处理器核心断言授权信号。 但是,只要保持信号有效,处理器核心的访问将被停止。
    • 63. 发明授权
    • Multicore DSP device having shared program memory with conditional write protection
    • 具有具有条件写保护功能的共享程序存储器的多核DSP设备
    • US06895479B2
    • 2005-05-17
    • US10008515
    • 2001-11-08
    • Jay B. ReimerTai H. NguyenYi LuoHarland Glenn HopkinsDan K. BuiKevin A. McGonagle
    • Jay B. ReimerTai H. NguyenYi LuoHarland Glenn HopkinsDan K. BuiKevin A. McGonagle
    • G06F12/14G06F9/00G06F11/00G06F11/26G06F12/00G06F15/177
    • G06F12/1433G06F11/2242G06F12/1491
    • A multi-core digital signal processor is disclosed having a shared program memory with conditional write protection. In one embodiment, the digital signal processor includes a shared program memory, an emulation logic module, and multiple processor cores each coupled to the shared program memory by corresponding instruction buses. The emulation logic module preferably determines the operating modes of each of the processors, e.g., whether they are operating in a normal mode or an emulation mode. In the emulation mode, the emulation logic can alter the states of various processor hardware and the contents of various registers and memory. The instruction buses each include a read/write signal that, while their corresponding processor cores are in normal mode, is maintained in a read state. On the other hand, when the processor cores are in the emulation mode, the processor cores are allowed to determine the state of the instruction bus read/write signals. Each instruction bus read/write signal is preferably generated by a logic gate that prevents the processor core from affecting the read/write signal value in normal mode, but allows the processor core to determine the read/write signal value in emulation mode. In this manner, the logic gate prevents write operations to the shared program memory when the emulation logic de-asserts a signal indicative of emulation mode, and allows write operations to the shared program memory when the emulation logic asserts the signal indicative of emulation mode. The logic gate is preferably included in a bus interface module in each processor core.
    • 公开了具有具有条件写保护的共享程序存储器的多核数字信号处理器。 在一个实施例中,数字信号处理器包括共享程序存储器,仿真逻辑模块和多个处理器内核,每个核心通过相应的指令总线耦合到共享程序存储器。 仿真逻辑模块优选地确定每个处理器的操作模式,例如,它们是以正常模式还是仿真模式操作。 在仿真模式下,仿真逻辑可以改变各种处理器硬件的状态以及各种寄存器和存储器的内容。 指令总线各自包括读/写信号,其在相应的处理器核处于正常模式的同时被保持在读取状态。 另一方面,当处理器核心处于仿真模式时,允许处理器核心确定指令总线读/写信号的状态。 每个指令总线读/写信号优选地由逻辑门产生,该逻辑门防止处理器核在正常模式下影响读/写信号值,但允许处理器核确定仿真模式中的读/写信号值。 以这种方式,当仿真逻辑取消断言指示仿真模式的信号时,逻辑门防止对共享程序存储器的写操作,并且当仿真逻辑断言指示仿真模式的信号时,允许对共享程序存储器的写操作。 逻辑门优选地包括在每个处理器核心中的总线接口模块中。
    • 67. 发明授权
    • Abstract generating search method and system
    • 抽象生成搜索方法和系统
    • US09367605B2
    • 2016-06-14
    • US12937562
    • 2010-08-27
    • Yi Luo
    • Yi Luo
    • G06F17/30G06F7/00
    • G06F17/30675G06F17/30622G06F17/30657G06F17/30696G06F17/30719
    • The present disclosure provides an information search method and system applicable in an information search system wherein each document has corresponding forward index data to address the issue of low search efficiency suffered by existing information search techniques. In one aspect, the method may include: receiving an inquiry word and obtaining one or more keywords contained in the inquiry word by segmentation; searching one or more documents matching the one or more keywords and forward index data corresponding to the one or more documents through the information search system's inverted index data; and determining an abstract of each of the one or more documents according to a corresponding document's forward index data, and outputting the abstract and information of the one or more documents as a search result. The proposed techniques can increase efficiency of information search and, at the meantime, guarantee accuracy of the search to a certain extent.
    • 本公开提供了一种适用于信息搜索系统的信息搜索方法和系统,其中每个文档具有相应的前向索引数据,以解决现有信息搜索技术所遭受的低搜索效率的问题。 一方面,该方法可以包括:通过分割接收询问字并获得包含在查询字中的一个或多个关键字; 搜索与一个或多个关键字匹配的一个或多个文档,并通过信息搜索系统的反向索引数据转发与一个或多个文档相对应的索引数据; 以及根据相应文件的前向索引数据确定所述一个或多个文档中的每一个的摘要,并将所述一个或多个文档的抽象和信息作为搜索结果输出。 提出的技术可以提高信息搜索的效率,同时保证搜索的准确性在一定程度上。
    • 70. 发明授权
    • Method and device for pre-coding, and method and device for decoding
    • 用于预编码的方法和装置,以及用于解码的方法和装置
    • US08781021B2
    • 2014-07-15
    • US13525641
    • 2012-06-18
    • Hui ShenBin LiYi Luo
    • Hui ShenBin LiYi Luo
    • H04B15/00H04B7/04H04L25/03
    • H04B7/0413H04B7/0465H04L25/03343
    • The present invention relates to the field of wireless communications technologies, and discloses a method and device for pre-coding and a method and device for decoding. The present invention implements an interference alignment method with excellent performance, can effectively increase the capacity of a multi-user interference system and reduce the mutual interference among users, The method for pre-coding includes: calculating a pre-coding matrix for each transmitting end according to a sum of mean square errors of data vectors to be transmitted by each transmitting ends; and using the pre-coding matrix to pre-code the data to be transmitted by each transmitting end. The present invention has broad application prospects, for example, can be used in LTE and LTE-Advanced CoMP technology.
    • 本发明涉及无线通信技术领域,并且公开了一种用于预编码的方法和装置以及用于解码的方法和装置。 本发明实现了具有优异性能的干扰对准方法,可以有效提高多用户干扰系统的容量,减少用户间的相互干扰。预编码方法包括:为每个发送端计算预编码矩阵 根据每个发送端发送的数据向量的均方误差之和; 并且使用预编码矩阵对由每个发送端发送的数据进行预编码。 本发明具有广泛的应用前景,例如可用于LTE和LTE-Advanced CoMP技术。