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61. 发明申请

US20140239388A1 TERMINATION TRENCH FOR POWER MOSFET APPLICATIONS 有权
标题翻译：用于功率MOSFET应用的终止电源
公开(公告)号：US20140239388A1
公开(公告)日：2014-08-28
申请号：US13776523
申请日：2013-02-25
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Yeeheng Lee , Madhur Bobde , Daniel Calafut , Hamza Yilmaz , Xiaobin Wang , Ji Pan , Hong Chang , Jongoh Kim
IPC分类号： H01L27/088 , H01L21/82
CPC分类号： H01L29/66143 , H01L21/265 , H01L21/308 , H01L21/823475 , H01L21/823487 , H01L27/0251 , H01L27/0629 , H01L27/088 , H01L27/095 , H01L29/0619 , H01L29/0623 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/66257 , H01L29/66712 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7808 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/872
摘要： Aspects of the present disclosure describe a termination structure for a power MOSFET device. A termination trench may be formed into a semiconductor material and may encircle an active area of the MOSFET. The termination trench may comprise a first and second portion of conductive material. The first and second portions of conductive material are electrically isolated from each other. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：本发明的方面描述了功率MOSFET器件的端接结构。终端沟槽可以形成为半导体材料并且可以环绕MOSFET的有效区域。端接沟槽可以包括导电材料的第一和第二部分。导电材料的第一和第二部分彼此电绝缘。要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

62. 发明申请

US20140239382A1 HIGH FREQUENCY SWITCHING MOSFETS WITH LOW OUTPUT CAPACITANCE USING A DEPLETABLE P-SHIELD 有权
公开(公告)号：US20140239382A1
公开(公告)日：2014-08-28
申请号：US14270228
申请日：2014-05-05
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Madhur Bobde , Hamza Yilmaz , Sik Lui , Daniel Ng
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/2257 , H01L27/0251 , H01L27/04 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/456 , H01L29/47 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7808 , H01L29/7811
摘要： Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

63. 发明授权

US08803251B2 Termination of high voltage (HV) devices with new configurations and methods 有权
标题翻译：用新的配置和方法终止高压（HV）设备
公开(公告)号：US08803251B2
公开(公告)日：2014-08-12
申请号：US13135982
申请日：2011-07-19
申请人： Yeeheng Lee , Madhur Bobde , Yongping Ding , Jongoh Kim , Anup Bhalla
发明人： Yeeheng Lee , Madhur Bobde , Yongping Ding , Jongoh Kim , Anup Bhalla
IPC分类号： H01L29/06 , H01L21/76
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0623 , H01L29/0649 , H01L29/407 , H01L29/66734 , H01L29/7813
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在轻掺杂区域上并具有有源电池区域和边缘端接区域的重掺杂区域。边缘终止区域包括形成在重掺杂区域中的多个端接沟槽，其中端接沟槽衬有介电层并在其中填充有导电材料。边缘终端还包括多个掩埋保护环，其形成为紧邻端接沟槽的半导体衬底的轻掺杂区域中的掺杂区域。

64. 发明授权

US08802529B2 Semiconductor device with field threshold MOSFET for high voltage termination 有权
标题翻译：具有用于高电压端接的场阈值MOSFET的半导体器件
公开(公告)号：US08802529B2
公开(公告)日：2014-08-12
申请号：US13135985
申请日：2011-07-19
申请人： Hamza Yilmaz , Madhur Bobde
发明人： Hamza Yilmaz , Madhur Bobde
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L27/088 , H01L29/0619 , H01L29/0638 , H01L29/0878 , H01L29/404 , H01L29/7803 , H01L29/7811
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold voltage Vt of the P-channel MOSFET transistors, thereby optimizing the voltage blocked by each region.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在重掺杂层上并具有活性电池区域和边缘终止区域的轻掺杂层。边缘终止区域包括多个P沟道MOSFET。通过将栅极连接到漏电极，当施加的电压等于或大于P沟道MOSFET晶体管的阈值电压Vt时，在边缘终端上形成的P沟道MOSFET晶体管顺序导通，从而优化电压被每个地区封锁

65. 发明授权

US08785270B2 Integrating schottky diode into power MOSFET 有权
标题翻译：将肖特基二极管集成到功率MOSFET中
公开(公告)号：US08785270B2
公开(公告)日：2014-07-22
申请号：US13948988
申请日：2013-07-23
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Yi Su , Daniel Ng , Anup Bhalla , Hong Chang , Jongoh Kim , John Chen
IPC分类号： H01L27/06 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7801 , H01L21/26586 , H01L29/0623 , H01L29/0696 , H01L29/0891 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/47 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/78 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/782 , H01L29/872
摘要： A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.
摘要翻译：半导体器件包括多个沟槽，包括有源区域中的有源栅极沟槽和栅极流道/终止沟槽以及在有源区域外部的终止区域中的屏蔽电极拾取沟槽。栅极流道/终止沟槽包括限定位于有源区域之外的台面的一个或多个沟槽。在多个沟槽中形成第一导电区域。在限定台面的沟槽中形成中间介质区域和端接保护区域。在限定台面的沟槽部分中形成第二导电区域。第二导电区域通过中间介电区域与第一导电区域电隔离。对第二导电区域进行第一电接触，并且在屏蔽电极拾取沟槽中对第一导电区域进行第二电接触。在台面内形成一个或多个肖特基二极管。

66. 发明授权

US08779510B2 Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts 有权
标题翻译：采用自对准工艺制造的半导体功率器件和更可靠的电触点
公开(公告)号：US08779510B2
公开(公告)日：2014-07-15
申请号：US12802185
申请日：2010-06-01
申请人： Hamza Yilmaz , John Chen , Daniel Ng , Wenjun Li
发明人： Hamza Yilmaz , John Chen , Daniel Ng , Wenjun Li
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/47 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7808 , H01L29/7811 , H01L29/866 , H01L29/872 , H01L29/8725
摘要： This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.
摘要翻译：本发明公开了一种半导体功率器件，其包括设置在半导体衬底的顶表面附近的多个顶部电端子。顶部电气端子中的每一个包括在半导体衬底的顶表面附近形成为硅化物接触层的端子接触层。半导体功率器件的沟槽栅极从半导体衬底的顶表面打开，并且每个沟槽栅极包括被配置为硅化物接触层的硅化物层，硅化物层设置在略微低于半导体衬底的顶表面围绕沟槽栅极。

67. 发明申请

US20140193958A1 TERMINATION DESIGN FOR HIGH VOLTAGE DEVICE 有权
公开(公告)号：US20140193958A1
公开(公告)日：2014-07-10
申请号：US14206480
申请日：2014-03-12
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Lingpeng Guan , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/66 , H01L29/40
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0623 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/404 , H01L29/407 , H01L29/66712 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

68. 发明授权

US08772828B2 Trench poly ESD formation for trench MOS and SGT 有权
标题翻译：沟槽MOS和SGT的沟槽聚合物ESD形成
公开(公告)号：US08772828B2
公开(公告)日：2014-07-08
申请号：US13911871
申请日：2013-06-06
申请人： Hong Chang , John Chen
发明人： Hong Chang , John Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/7393 , H01L27/0259 , H01L29/7827
摘要： A semiconductor device includes a semiconductor material disposed in a trench with polysilicon lining at least the bottom of the trench. The semiconductor material includes differently doped regions configured as a PNP or NPN structure formed in the trench with differently doped regions located side by side across a width of the trench. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：半导体器件包括设置在具有至少沟槽底部的多晶硅衬底的沟槽中的半导体材料。半导体材料包括不同的掺杂区域，其被配置为在沟槽中形成的PNP或NPN结构，其中不同的掺杂区域跨越沟槽的宽度并排设置。要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

69. 发明授权

US08759908B2 Two-dimensional shielded gate transistor device and method of manufacture 有权
标题翻译：二维屏蔽晶体管器件及其制造方法
公开(公告)号：US08759908B2
公开(公告)日：2014-06-24
申请号：US13286733
申请日：2011-11-01
申请人： Sik Lui , Anup Bhalla , Daniel Ng
发明人： Sik Lui , Anup Bhalla , Daniel Ng
IPC分类号： H01L29/78
CPC分类号： H01L29/4238 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7813
摘要： A shielded gate transistor device may include one or more shield electrodes formed in a semiconductor substrate at a first level and one or more gate electrodes formed in the semiconductor substrate at a second level that is different from the first level. One or more portions of the one or more gate electrodes overlap one or more portions of the one or more shield electrodes. At least a portion of the gate electrodes is oriented non-parallel to the one or more shield electrodes. The shield electrodes are electrically insulated from the semiconductor substrate and the one or more gate electrodes are electrically insulated from the substrate and shield electrodes.
摘要翻译：屏蔽栅晶体管器件可以包括形成在第一电平的半导体衬底中的一个或多个屏蔽电极和形成在与第一电平不同的第二电平的半导体衬底中的一个或多个栅电极。一个或多个栅电极的一个或多个部分重叠一个或多个屏蔽电极的一个或多个部分。栅电极的至少一部分取向为不平行于一个或多个屏蔽电极。屏蔽电极与半导体衬底电绝缘，并且一个或多个栅电极与衬底和屏蔽电极电绝缘。

70. 发明申请

US20140167144A1 VERTICAL DMOS TRANSISTOR 有权
标题翻译：垂直DMOS晶体管
公开(公告)号：US20140167144A1
公开(公告)日：2014-06-19
申请号：US13720069
申请日：2012-12-19
申请人： ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
发明人： Hideaki Tsuchiko
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7802 , H01L21/265 , H01L21/30604 , H01L21/823418 , H01L21/823493 , H01L27/088 , H01L27/0922 , H01L27/0928 , H01L29/0653 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/66659 , H01L29/66712 , H01L29/66719 , H01L29/7809 , H01L29/7835
摘要： A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially overlapping the body region and insulated from the semiconductor body by a gate dielectric layer; a source diffusion region of a second conductivity type formed in the body region on a first side of the gate electrode; a trench formed in the semiconductor body on a second side, opposite the first side, of the gate electrode, the trench being lined with a sidewall dielectric layer; and a doped sidewall region of the second conductivity type formed in the semiconductor body along the sidewall of the trench where the doped sidewall region forms a vertical drain current path for the transistor.
摘要翻译：晶体管包括半导体本体; 形成在半导体本体中的第一导电类型的主体区域; 形成为与所述体区部分重叠并且与所述半导体本体绝缘的栅电极; 形成在所述栅电极的第一侧上的所述体区的第二导电类型的源极扩散区; 形成在所述半导体本体中的与所述栅极电极相对的第二侧上的沟槽，所述沟槽衬有侧壁电介质层; 以及沿着沟槽的侧壁形成在半导体主体中的第二导电类型的掺杂侧壁区域，其中掺杂侧壁区域形成晶体管的垂直漏极电流路径。

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