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61. 发明授权

US5532621A Output buffer circuit, input buffer circuit and bi-directional buffer circuit for plural voltage systems 失效
标题翻译：输出缓冲电路，输入缓冲电路和多电压系统的双向缓冲电路
公开(公告)号：US5532621A
公开(公告)日：1996-07-02
申请号：US360056
申请日：1994-12-20
申请人： Kenichiro Kobayashi , Hisaya Keida
发明人： Kenichiro Kobayashi , Hisaya Keida
IPC分类号： H01L27/04 , G05F1/46 , G05F3/24 , H01L21/822 , H01L27/00 , H03K5/02 , H03K19/003 , H03K19/0185 , H03K19/094 , H03K17/06
CPC分类号： G05F3/24 , G05F1/465 , H03K19/00315 , H03K19/018592
摘要： Bi-directional buffer circuit comprises a second P-channel transistor whose back gate is connected to a pad, a third P-channel transistor disposed between a gate of the second P-channel transistor and the pad with its back gate connected to the pad, and a first N-channel transistor and a fifth N-channel transistor whose gates are connected to a power source, so that an output buffer circuit, an input buffer circuit and a bi-directional buffer circuit can be produced without necessity of any additional processing step, wherein merely a single power source is incorporated, and a voltage higher than the source voltage is permitted to be applied to a common bus.
摘要翻译：双向缓冲电路包括：第二P沟道晶体管，其背栅极连接到焊盘;第三P沟道晶体管，设置在第二P沟道晶体管的栅极和焊盘之间，其背栅极连接到焊盘; 以及第一N沟道晶体管和第五N沟道晶体管，其栅极连接到电源，从而可以产生输出缓冲电路，输入缓冲电路和双向缓冲电路，而不需要任何额外的处理步骤，其中仅包括单个电源，并且允许高于源电压的电压施加到公共总线。

62. 发明授权

US5465057A Level conversion circuit for signal of ECL-level 失效
标题翻译： ECL级信号电平转换电路
公开(公告)号：US5465057A
公开(公告)日：1995-11-07
申请号：US231059
申请日：1994-04-22
申请人： Hiroyuki Takahashi
发明人： Hiroyuki Takahashi
IPC分类号： H03K5/02 , H03K19/0175
CPC分类号： H03K19/017518
摘要： A level conversion circuit for converting a first signal having a first amplitude into a second signal having a second amplitude that is larger than the first amplitude, includes a bipolar transistor supplied at a base thereof with the first signal, a first MOS transistor of a first channel type having a gate supplied with a bias voltage and a source-drain path connected between the emitter of the bipolar transistor and an output node from which the second signal is derived, and a second MOS transistor of a second channel type having a gate supplied with an inverted signal of the first signal and a source-drain path connected between the output node and a reference potential line. A PN junction diode is preferably inserted between the third transistor and the reference potential line.
摘要翻译：用于将具有第一幅度的第一信号转换为具有大于第一幅度的第二幅度的第二信号的电平转换电路包括在其基极处提供第一信号的双极晶体管，第一信号的第一MOS晶体管沟道型，具有提供有偏置电压的栅极和连接在双极晶体管的发射极和源于其的输出节点之间的源极 - 漏极路径，以及具有提供栅极的第二沟道型的第二MOS晶体管具有第一信号的反相信号和连接在输出节点和参考电位线之间的源极 - 漏极路径。 PN结二极管优选地插入在第三晶体管和参考电位线之间。

63. 发明授权

US5459428A Switch circuit for monolithic microwave integrated circuit device 失效
标题翻译：单片微波集成电路器件开关电路
公开(公告)号：US5459428A
公开(公告)日：1995-10-17
申请号：US359207
申请日：1994-12-19
申请人： Min-Gun Kim , Choong-Hwan Kim , In-Gab Hwang , Chang-Seok Lee , Hyung-Moo Park
发明人： Min-Gun Kim , Choong-Hwan Kim , In-Gab Hwang , Chang-Seok Lee , Hyung-Moo Park
IPC分类号： H03F3/72 , H03K5/02 , H03K17/687 , H03K17/16 , H03K5/22 , H03K9/08
CPC分类号： H03K5/023 , H03F3/72 , H03K17/687
摘要： Disclosed is a switch circuit which has a depletion mode n-channel MOSFET which can be used in a circuit allowing only a positive voltage to be supplied thereto, comprising a first D-FET having a gate for receiving an input signal, a drain for outputting an output signal and a source; a first resistor connected between the drain of the first D-FET and a positive voltage source to bias the drain of the first D-FET; a second D-FET having a gate connected to an intermittence controlling voltage source, a drain and a source connected to the positive voltage source and the source of the first D-FET 201, respectively; a second resistor connected between the gate of the second D-FET and a ground to bias the gate of the second D-FET; a constant-current source connected between each of the sources of the first and second D-FET and the ground; a bypass capacitor connected in parallel with the constant-current source and between the drain of the constant-current source and the ground to bypass an RF signal to the ground; and a third resistor connected between the gate of the first D-FET 201 and the ground to bias the gate of the first D-FET. Since the switch circuit can be operated only by a positive voltage without use of a negative voltage, it can be embodied with a general depletion mode n-channel MOSFET which can be fabricated by a relatively simple fabrication sequence and has a relatively simple structure in comparison with an enhancement mode n-channel MOSFET.
摘要翻译：公开了一种开关电路，其具有耗尽型n沟道MOSFET，其可用于仅允许向其提供正电压的电路，包括具有用于接收输入信号的栅极的第一D-FET，用于输出的漏极输出信号和源; 连接在第一D-FET的漏极和正电压源之间的第一电阻器，用于偏置第一D-FET的漏极; 具有连接到间歇控制电压源的栅极的第二D-FET，分别连接到正电压源和第一D-FET 201的源极的漏极和源极; 连接在第二D-FET的栅极和用于偏置第二D-FET的栅极的接地的第二电阻器; 连接在第一和第二D-FET的每个源极和地之间的恒流源; 旁路电容器与恒流源并联连接，并且在恒流源的漏极和地之间绕过RF信号到地面; 以及连接在第一D-FET201的栅极和接地之间的第三电阻器，用于偏置第一D-FET的栅极。由于开关电路只能通过正电压而不使用负电压工作，所以可以用通常的耗尽型n沟道MOSFET来实现，该沟道MOSFET可以通过相对简单的制造顺序制造，并且具有比较简单的结构具有增强型n沟道MOSFET。

64. 发明授权

US5430400A Driver circuits for IC tester 失效
标题翻译： IC测试仪的驱动电路
公开(公告)号：US5430400A
公开(公告)日：1995-07-04
申请号：US100975
申请日：1993-08-03
申请人： Richard F. Herlein , Sergio A. Sanielevici , Burnell G. West , David K. Cheung
发明人： Richard F. Herlein , Sergio A. Sanielevici , Burnell G. West , David K. Cheung
IPC分类号： G01R31/28 , G01R31/319 , H03K5/02 , H03K3/01 , H03K19/00
CPC分类号： G01R31/31924
摘要： Driver circuits are provided which also serve as termination and clamp in an IC tester. When it is to drive a port of a device under test (DUT) between two predetermined voltage levels, the driver's I/O terminal is switched between two predetermined voltage levels with an output impedance that matches the transmission line between the driver circuit and the DUT. When the DUT's port is supplying an output signal, the driver circuit can be programmed to provide one of two types of termination. If the DUT's port is specified as capable of driving the load, the transmission line between the driver circuit and the DUT is terminated by switching the driver circuit's I/O terminal to a predetermined voltage level with an impedance of Z.sub.0. If the DUT's port is not specified as being capable of driving such a termination load, the driver circuit functions like a Z-clamp circuit.
摘要翻译：提供驱动器电路，其也用作IC测试器中的终端和钳位。当在两个预定电压电平之间驱动被测设备（DUT）的端口时，驱动器的I / O端子在两个预定电压电平之间切换，其输出阻抗与驱动器电路和DUT之间的传输线匹配。当DUT的端口提供输出信号时，驱动器电路可以被编程为提供两种类型的终端之一。如果DUT的端口被指定为能够驱动负载，则通过将驱动器电路的I / O端子切换到具有Z0的阻抗的预定电压电平来终止驱动器电路和DUT之间的传输线。如果DUT的端口没有被指定为能够驱动这样的终端负载，则驱动电路的作用就像Z钳位电路。

65. 发明授权

US5378932A Level shifting circuit 失效
标题翻译：电平转换电路
公开(公告)号：US5378932A
公开(公告)日：1995-01-03
申请号：US50612
申请日：1993-04-22
申请人： Yasuhiro Shin , Tatsuya Kimura
发明人： Yasuhiro Shin , Tatsuya Kimura
IPC分类号： H03K5/02 , H03K3/356 , H03K19/0185 , H03K17/60
CPC分类号： H03K3/356113 , H03K3/356017
摘要： A level shifting circuit according to the present invention has first and second voltage terminals, first and second input terminals, an output terminal, a level converter circuit and an output circuit. The level converter includes first, second and third nodes, first, second, third and fourth transistors and an resistive element. The first transistor has a first electrode connected to the first voltage terminal, a second electrode connected to the first node and a control electrode connected to the first input terminal. The second transistor has a first electrode connected to the first voltage terminal, a second electrode connected to the second node and a control electrode connected to the second input terminal. The third transistor has a first electrode connected to the second voltage level, a second electrode connected to the first node and a control electrode connected to the second node. The resistive element connected between the second and third nodes. The fourth transistor has a first electrode connected to the second voltage level, a second electrode connected to the third node and a control electrode connected to the first node. The output circuit includes fifth and sixth transistors. The fifth transistor has a first electrode connected to the first voltage terminal, a second electrode connected to the output terminal and a control electrode connected to the second node. The sixth transistor has a first electrode connected to the second voltage terminal, a second electrode connected to the output terminal an a control electrode connected to the third node.
摘要翻译：根据本发明的电平移动电路具有第一和第二电压端子，第一和第二输入端子，输出端子，电平转换器电路和输出电路。电平转换器包括第一，第二和第三节点，第一，第二，第三和第四晶体管以及电阻元件。第一晶体管具有连接到第一电压端子的第一电极，连接到第一节点的第二电极和连接到第一输入端子的控制电极。第二晶体管具有连接到第一电压端子的第一电极，连接到第二节点的第二电极和连接到第二输入端子的控制电极。第三晶体管具有连接到第二电压电平的第一电极，连接到第一节点的第二电极和连接到第二节点的控制电极。连接在第二和第三节点之间的电阻元件。第四晶体管具有连接到第二电压电平的第一电极，连接到第三节点的第二电极和连接到第一节点的控制电极。输出电路包括第五和第六晶体管。第五晶体管具有连接到第一电压端子的第一电极，连接到输出端子的第二电极和连接到第二节点的控制电极。第六晶体管具有连接到第二电压端子的第一电极，连接到输出端子的第二电极和连接到第三节点的控制电极。

66. 发明授权

US5376845A Apparatus and method for ECL-like signal to CMOS signal conversion 失效
标题翻译：用于ECL类信号到CMOS信号转换的装置和方法
公开(公告)号：US5376845A
公开(公告)日：1994-12-27
申请号：US215166
申请日：1994-03-18
申请人： Kevin M. Ovens , Robert A. Helmick
发明人： Kevin M. Ovens , Robert A. Helmick
IPC分类号： H03K5/02 , H03K19/003 , H03K19/017 , H03K19/0175
CPC分类号： H03K19/017527 , H03K19/00369 , H03K19/01721 , H03K19/017518
摘要： In one aspect of the present invention, a converter is provided comprising a capacitive coupling arranged to receive said input signal to be converter, and a conversion circuitry coupled to the capacitive coupling to produce the converted output signal. A biasing circuit is further arranged to facilitate a fast transition in the converted output signal in response to an active transition in the input signal.
摘要翻译：在本发明的一个方面中，提供了一种转换器，其包括被布置为接收要转换器的所述输入信号的电容耦合器，以及耦合到所述电容耦合以产生转换的输出信号的转换电路。偏置电路还被布置成响应于输入信号中的有效转换而促进转换的输出信号中的快速转变。

67. 发明授权

US5371421A Low power BiMOS amplifier and ECL-CMOS level converter 失效
标题翻译：低功耗BiMOS放大器和ECL-CMOS电平转换器
公开(公告)号：US5371421A
公开(公告)日：1994-12-06
申请号：US29686
申请日：1993-03-11
申请人： Harufusa Kondoh , Atsushi Ohba
发明人： Harufusa Kondoh , Atsushi Ohba
IPC分类号： H03F3/45 , H03K5/02 , H03K19/01 , H03K19/0175 , H03K19/0185 , H03K19/08
CPC分类号： H03K3/021
摘要： A BiMOS amplifier device includes one stage which can function as both a level-shift and buffer stage and an amplifier stage. The amplifier includes first and second bipolar transistors having their bases connected to first and second input terminals, respectively, having their collectors connected to a point of first potential, and having their emitters connected to the sources of first and second MOS transistors, respectively. The drains of the first and second MOS transistors are connected through respective impedance means to a point of second potential. The gate of each of the MOS transistors is connected to the drain of the other MOS transistor. An output terminal is connected to the drain of at least one of the MOS transistors.
摘要翻译： BiMOS放大器装置包括一个可以起电平移位和缓冲级以及放大级的功能。放大器包括第一和第二双极晶体管，它们的基极分别连接到第一和第二输入端，它们的集电极分别连接到第一电位点，并且其发射极分别连接到第一和第二MOS晶体管的源极。第一和第二MOS晶体管的漏极通过相应的阻抗装置连接到第二电势点。每个MOS晶体管的栅极连接到另一个MOS晶体管的漏极。输出端连接到至少一个MOS晶体管的漏极。

68. 发明授权

US5347538A Transceiver for bidirectional link, integrated circuit including the transceiver, and application to communication between units of a system 失效
标题翻译：收发器用于双向链路，集成电路包括收发器，以及应用于系统单元之间的通信
公开(公告)号：US5347538A
公开(公告)日：1994-09-13
申请号：US843210
申请日：1992-02-28
申请人： Roland Marbot
发明人： Roland Marbot
IPC分类号： H03K5/02 , H04B1/58 , H04L5/14 , H04L29/00 , H04L29/12 , H04B1/38 , H04L5/16
CPC分类号： H04B1/58 , H03K5/026 , H04L5/1423
摘要： Transceiver for transmission over serial bi-directional links having a bi-directional amplifier including an impedance (R) for adaptation to the line and connected to it, a generator (G1) commanded for transmission and supplying the adaptation impedance (R) and the line in parallel, detection device (G2, r) for furnishing a measurement signal (V) representative of either the current circulating in the adaptation impedance (R) when the generator (G1) is active, or the sum of the current in the adaptation impedance (R) and a compensation value when the first generator (G1) is not active. The compensation value is determined so as to make the measurement signal (V) independent of the transmission state of the transceiver.
摘要翻译：用于通过串行双向链路传输的收发器，具有双向放大器，该双向放大器包括用于适应线路并连接到其上的阻抗（R），命令用于传输和提供自适应阻抗（R）的线路用于提供表示当发电机（G1）有效时在自适应阻抗（R）中循环的电流的测量信号（V）或适应阻抗中的电流之和的检测装置（G2，r）（R）和第一发生器（G1）不起作用时的补偿值。确定补偿值，使得测量信号（V）独立于收发器的传输状态。

69. 发明授权

US5331229A CMOS/ECL signal level converter 失效
标题翻译： CMOS / ECL信号电平转换器
公开(公告)号：US5331229A
公开(公告)日：1994-07-19
申请号：US869472
申请日：1992-04-15
申请人： Claude Barre
发明人： Claude Barre
IPC分类号： H03K5/02 , H03K19/00 , H03K19/003 , H03K19/0175 , H03K17/075
CPC分类号： H03K19/00376 , H03K19/0016 , H03K19/017527
摘要： A signal level converter for converting CMOS input signal levels to ECL output signal levels includes first and second transistors having emitters connected to each other. The collector of the first transistor is directly connected to a first supply voltage potential. A first resistor is connected between the collector of the second transistor and the first supply voltage potential. The base of the second transistor is connected to a reference potential. A third transistor has a collector connected to the emitters of the first and second transistors. A second resistor is connected between the emitter of the third transistor and a second supply voltage potential. The base of the third transistor is connected to a control potential. A fourth transistor has a collector connected to the first supply voltage potential and a base connected to the collector of the second transistor. An input signal terminal is connected to the base of the first transistor, and an output signal terminal is connected to the emitter of the fourth transistor. The first resistor is a controllable resistor being controlled for having a high resistance when current flowing through the collector-to-emitter path of the third transistor flows through the collector-to-emitter path of the second transistor, and having a low resistance when that current flows through the collector-to-emitter path of the first transistor.
摘要翻译：用于将CMOS输入信号电平转换为ECL输出信号电平的信号电平转换器包括具有彼此连接的发射极的第一和第二晶体管。第一晶体管的集电极直接连接到第一电源电压。第一电阻器连接在第二晶体管的集电极和第一电源电压之间。第二晶体管的基极连接到参考电位。第三晶体管具有连接到第一和第二晶体管的发射极的集电极。第二电阻器连接在第三晶体管的发射极和第二电源电压之间。第三晶体管的基极连接到控制电位。第四晶体管具有连接到第一电源电压电位的集电极和连接到第二晶体管的集电极的基极。输入信号端子连接到第一晶体管的基极，输出信号端子连接到第四晶体管的发射极。第一电阻器是可控电阻器，其被控制为当电流流过第三晶体管的集电极到发射极路径的电流流过第二晶体管的集电极到发射极路径时具有高电阻，并且当该电阻器具有低电阻时电流流过第一晶体管的集电极 - 发射极路径。

70. 发明授权

US5315449A Time code signal processing circuit for removing and restoring variation in slew rate 失效
标题翻译：用于去除和恢复压摆率变化的时间码信号处理电路
公开(公告)号：US5315449A
公开(公告)日：1994-05-24
申请号：US945113
申请日：1992-09-14
申请人： Birney D. Dayton , Thomas B. Crabb
发明人： Birney D. Dayton , Thomas B. Crabb
IPC分类号： G11B15/18 , G11B27/32 , H03F1/02 , H03K5/02 , H03K5/12 , G11B27/02 , G11B5/03 , G11B15/12
CPC分类号： H03K5/02 , G11B15/1875 , G11B27/323 , H03F1/0222 , H03F1/0261 , H03K5/12
摘要： A circuit for processing an input pulse signal of which the slew rate is dependent on pulse frequency comprises an amplifier (30; 78) for receiving the input pulse signal and generating an output pulse signal having transitions of which the slew rate is dependent on a bias current supplied to the amplifier, and a circuit (38-66; 82-108) for supplying bias current to the amplifier, the bias current being representative at least substantially of the frequency of occurrence of pulses in the input pulse signal.
摘要翻译：用于处理转换速率取决于脉冲频率的输入脉冲信号的电路包括用于接收输入脉冲信号并产生输出脉冲信号的放大器（30; 78），该输出脉冲信号具有转换速率取决于偏置的转换提供给放大器的电流和用于向放大器提供偏置电流的电路（38-66; 82-108），所述偏置电流至少基本上代表输入脉冲信号中脉冲的出现频率。

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