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61. 发明授权

US11316531B2 Parity puncturing device for fixed-length signaling information encoding, and parity puncturing method using same 有权
公开(公告)号：US11316531B2
公开(公告)日：2022-04-26
申请号：US17021025
申请日：2020-09-15
申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
发明人： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim
IPC分类号： H03M13/03 , H03M13/11 , H03M13/27 , H03M13/00 , H03M13/39 , H03M13/15 , H03M13/25 , H03M13/29
摘要： A parity puncturing apparatus and method for fixed length signaling information are disclosed. A parity puncturing apparatus according to an embodiment of the present invention includes memory configured to provide a parity bit string for parity puncturing for the parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, and a processor configured to puncture a number of bits corresponding to a final puncturing size from the rear side of the parity bit string.

62. 发明授权

US11309918B2 Memory system 有权
公开(公告)号：US11309918B2
公开(公告)日：2022-04-19
申请号：US17005282
申请日：2020-08-27
申请人： KIOXIA CORPORATION
发明人： Yuta Kumano , Hironori Uchikawa
IPC分类号： H03M13/00 , H03M13/15 , G06F11/07 , H03M13/11
摘要： A memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory stores a multidimensional error correction code in which each of a plurality of symbol groups is encoded by both a first component code and a second component code. The memory controller reads the error correction code from the nonvolatile memory, executes a first decoding process using the first component code and the second component code, and when the first decoding process fails, executes a second decoding process on an error symbol group. The second decoding process includes a process of selecting the positions of a plurality of symbols whose values included in the error symbol group are to be inverted according to a decision rule. The decision rule includes a rule for cyclically shifting a position selected for the second decoding process at to decide the position for the second decoding process at the next time.

63. 发明授权

US11307988B2 Configurable cache for multi-endpoint heterogeneous coherent system 有权
公开(公告)号：US11307988B2
公开(公告)日：2022-04-19
申请号：US16653263
申请日：2019-10-15
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Kai Chirca , Matthew David Pierson
IPC分类号： G06F12/084 , G06F12/0811 , G06F12/1009 , G06F12/0875 , G06F12/10 , G06F13/16 , G06F13/40 , G06F12/0855 , G06F12/06 , G06F12/0817 , G06F12/0831 , G06F13/12 , G06F3/06 , G06F12/0815 , H03M13/01 , H03M13/09 , H03M13/15 , H03M13/27 , G06F9/30 , G06F9/38 , G06F9/48 , G06F9/50 , G06F12/0891 , G06F12/0846 , G06F12/0862
摘要： A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.

64. 发明申请

US20220116056A1 BIT FLIPPING LOW-DENSITY PARITY-CHECK DECODERS WITH LOW ERROR FLOOR 有权
公开(公告)号：US20220116056A1
公开(公告)日：2022-04-14
申请号：US17066384
申请日：2020-10-08
申请人： Micron Technology, Inc.
发明人： Mustafa N. Kaynak , Sivagnanam Parthasarathy
IPC分类号： H03M13/11 , H03M13/15 , H03M13/29
摘要： A memory device having a Low-Density Parity-Check (LDPC) decoder that is energy efficient and has a low error floor. The decoder is configured to determine syndromes of bits in a codeword, select bits in the codeword based at least in part on the syndromes according to a first mode, and flip the selected bits in the codeword. The decoder can repeat the bit selection and flipping operations to iteratively improve the codeword and reduce parity violations. Further, the decoder can detect a pattern in parity violations of the codeword in its iterative bit flipping operations. In response, the decoder can change from the first mode to a second mode in bit selection for flipping. For example, the decoder can transmit from a dynamic syndrome mode to a static syndrome mode in response to the pattern of repeating a cycle of bit flipping iterations.

65. 发明授权

US11301387B2 Memory system configured with a synthesized logical block into which a plurality of data units forming an error correction frame are written 有权
公开(公告)号：US11301387B2
公开(公告)日：2022-04-12
申请号：US16704555
申请日：2019-12-05
申请人： KIOXIA Corporation
发明人： Hirokazu Takeuchi , Takahiro Miomo , Hiroyuki Yamaguchi , Hajime Yamazaki
IPC分类号： G11C29/52 , G06F12/0862 , G06F11/10 , G06F12/10 , G11C29/00 , G06F12/06 , G06F12/0868 , H03M13/15 , G11C29/04 , G11C29/44 , H03M13/27
摘要： A memory system includes a memory and a memory controller. The memory includes first and second parallel operation elements, each including a plurality of first and second storage regions, respectively, and first and second buffers, respectively. The memory controller performs operations on the memory based on first and second group information. The first group information defines first groups, each first group including one first storage region and one second storage region, and each second group including at least two first groups. The memory controller, in response to a host command targeting a first storage region, (i) acquires first data from the first buffer, and thereafter (ii) causes the memory to read out second data to the first buffer. The first storage region storing the first data and the second storage region storing the second data belong to different first groups and to the same second group.

66. 发明授权

US11296820B2 Signaling coding and modulation method and demodulation and decoding method and device 有权
公开(公告)号：US11296820B2
公开(公告)日：2022-04-05
申请号：US16748739
申请日：2020-01-21
申请人： Shanghai National Engineering Research Center of Digital Television Co., Ltd.
发明人： Wenjun Zhang , Yijun Shi , Dazhi He , Ge Huang , Hongliang Xu , Yao Wang
IPC分类号： H04L1/00 , H04N21/438 , H04N21/2383 , H03M13/11 , H03M13/15 , H03M13/00
摘要： Provided are a signaling coding and modulation method and a demodulation and decoding method and device, characterized in that the method comprises the steps of: extending signaling which has been subjected to first predetermined processing according to an extension pattern table to obtain an extended codeword, and conducting predetermined coding on the extended codeword to obtain a encoded codeword; conducting parity bit permutation on a parity bit portion in the encoded codeword and then splicing the permutated parity bits to the end of information bits in the encoded codeword, to obtain a permutated encoded codeword; according to the length of the signaling, punching the permutated encoded codeword according to a predetermined punching rule to obtain a punched encoded codeword; and conducting second predetermined processing on the punched encoded codeword to obtain a tuple sequence, which is used for mapping, and then mapping the tuple sequence.

67. 发明授权

US11296728B2 Interleaving and mapping method and deinterleaving and demapping method for LDPC codeword 有权
公开(公告)号：US11296728B2
公开(公告)日：2022-04-05
申请号：US17033795
申请日：2020-09-27
申请人： Shanghai National Engineering Research Center of Digital Television Co., Ltd.
发明人： Wenjun Zhang , Yijun Shi , Dazhi He , Yunfeng Guan , Yin Xu , Xufeng Guo
IPC分类号： H03M13/27 , H04L1/00 , H03M13/03 , H03M13/11 , H03M13/25 , H03M13/29 , H03M13/00 , H03M13/15 , H04L27/18 , H04L27/34
摘要： An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises: performing first bit interleaving on a parity bits part of the LDPC codeword to obtain interleaved parity bits; splicing an information bit part of the codeword and the interleaved parity bits into a codeword after the first bit interleaving; dividing the codeword after the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding permutation order (bit-swapping pattern) to form a codeword after second bit interleaving; dividing the codeword after the second bit interleaving into two parts, and writing the two parts into storage space in a column order respectively and reading the two parts from the storage space in a row order respectively to obtain a codeword after third bit interleaving.

68. 发明授权

US11294764B2 Method of correcting errors in a memory array and method of screening weak bits in the same 有权
公开(公告)号：US11294764B2
公开(公告)日：2022-04-05
申请号：US16786795
申请日：2020-02-10
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Yu-Der Chih , Chia-Fu Lee , Chien-Yin Liu , Yi-Chun Shih , Kuan-Chun Chen , Hsueh-Chih Yang , Shih-Lien Linus Lu
IPC分类号： G06F11/10 , H03M13/29 , H03M13/15 , H03M13/19 , G11C29/42
摘要： A method of screening weak bits in a memory array. The method includes storing a first set of data in a first memory array of the memory array, performing a first baking process on at least the first memory array or applying a first magnetic field to at least the first memory array, tracking an address of at least a first memory cell of a first set of memory cells of the first memory array, if the first memory cell of the first set of memory cells stores altered data, and at least one of replacing the first memory cell of the first set of memory cells storing the altered data with a corresponding memory cell in a second memory array of the memory array, or discarding the first memory cell of the first set of memory cells storing the altered data.

69. 发明申请

US20220094372A1 EFFICIENT ENCODING FOR NON-BINARY ERROR CORRECTION CODES 有权
公开(公告)号：US20220094372A1
公开(公告)日：2022-03-24
申请号：US17031066
申请日：2020-09-24
申请人： GYLICON LTD
发明人： Claudio Tocalli
IPC分类号： H03M13/11 , H03M13/15 , H03M13/27
摘要： A method for encoding information bits with a Q-ary linear error correction code defined over a binary-extension Galois field GF(2k), and defined by a quasi-cyclic parity-check matrix comprising: first, second and third circulant sub-matrices respectively comprising first, second and third circulants respectively having first, second and third shifts and being defined respectively by first, second and third parameters belonging to the Galois field GF(2k), said second parameter being the inverse of the first parameter, and the second shift being equal to a difference between a number of rows of each circulant and the first shift. The method comprises determining: a first set of parity-check bits according to a fourth circulant having a fourth shift equal to a difference between said number of rows and said first and third shifts and being defined by the multiplicative inverse of a fourth parameter given by a product between the first and third parameters, and to the second and third circulant sub-matrices, and a second set of parity-check bits according to the determined first set of parity-check bits and said first and second circulant sub-matrices.

70. 发明授权

US11283469B2 Integrated circuit 有权
公开(公告)号：US11283469B2
公开(公告)日：2022-03-22
申请号：US17103969
申请日：2020-11-25
申请人： Infineon Technologies AG
发明人： Wieland Fischer , Bernd Meyer
IPC分类号： H03M13/15
摘要： An integrated circuit for outputting a function value, comprising a pattern matching circuit, configured to compare an input value and multiple transformed versions of the input value with a specified bit pattern, wherein the transformed versions of the input value or the specified bit pattern are created by repeated application of a transformation to the input value or the specified bit pattern, wherein the function is invariant under the transformation or wherein an inverse transformation exists for the transformation, by means of which a change in the function values that is caused by the transformation of the input values can be reversed, a selection circuit configured to select a function value depending on the matching result of the pattern matching circuit and the input value, and an output circuit configured to output a function value for the input value based on the selected function value.

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