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71. 发明授权

US08519471B2 Vertical channel type nonvolatile memory device and method for fabricating the same 有权
标题翻译：垂直通道型非易失性存储器件及其制造方法
公开(公告)号：US08519471B2
公开(公告)日：2013-08-27
申请号：US12964233
申请日：2010-12-09
申请人： Seoung-Woo Kuk , Kang-Jae Lee
发明人： Seoung-Woo Kuk , Kang-Jae Lee
IPC分类号： H01L29/792
CPC分类号： H01L27/11551 , H01L27/11556 , H01L27/11578
摘要： A method for fabricating a vertical channel type nonvolatile memory device includes forming alternately a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, forming a trench having a plurality of recesses on a surface of the trench by etching the plurality of interlayer dielectric layers and a plurality of conductive layers, wherein the plurality of recesses are formed at a certain interval on the surface of the trench, forming a charge blocking layer over a plurality of surfaces of the plurality of recesses, forming a charge storage layer over the charge blocking layer for filling a plurality of the remaining recesses with a charge storage material, forming a tunnel dielectric layer to cover the charge storage layer, and forming a vertical channel layer by filling the remaining trench.
摘要翻译：一种用于制造垂直沟道型非易失性存储器件的方法包括在衬底上交替地形成多个层间电介质层和多个导电层，通过蚀刻多个中间层在沟槽的表面上形成具有多个凹槽的沟槽电介质层和多个导电层，其中所述多个凹槽在所述沟槽的表面上以一定间隔形成，在所述多个凹槽的多个表面上形成电荷阻挡层，在所述多个凹槽的上方形成电荷存储层电荷阻挡层，用于用电荷存储材料填充多个剩余的凹槽，形成隧道电介质层以覆盖电荷存储层，以及通过填充剩余的沟槽形成垂直沟道层。

72. 发明授权

US08519464B2 Non-volatile memory device and method for fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08519464B2
公开(公告)日：2013-08-27
申请号：US13159841
申请日：2011-06-14
申请人： Joo-Won Hwang
发明人： Joo-Won Hwang
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L21/28273
摘要： A non-volatile memory device includes a plurality of stacked patterns where a tunnel insulation layer, a floating gate, and a dielectric layer are sequentially stacked over a substrate, trenches formed in the substrate between the stacked patterns, an isolation layer gap-filling the trenches and space between the stacked patterns, and a control gate formed over the dielectric layer.
摘要翻译：非易失性存储器件包括多个堆叠图案，其中隧道绝缘层，浮动栅极和电介质层顺序地层叠在衬底上，在堆叠图案之间形成在衬底中的沟槽，隔离层间隙填充沟槽和堆叠图案之间的空间，以及形成在电介质层上的控制栅极。

73. 发明授权

US08519374B2 Resistive memory device and method for fabricating the same 有权
标题翻译：电阻式存储器件及其制造方法
公开(公告)号：US08519374B2
公开(公告)日：2013-08-27
申请号：US12979922
申请日：2010-12-28
申请人： Seok-Pyo Song , Yu-Jin Lee
发明人： Seok-Pyo Song , Yu-Jin Lee
IPC分类号： H01L29/02 , H01L29/41
CPC分类号： H01L45/1273 , G11C2213/52 , H01L27/2409 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/1253 , H01L45/16
摘要： A resistive memory device includes a lower electrode formed on a substrate, a resistive layer formed on the lower electrode, and an upper electrode on the resistive layer, wherein a lower portion of the upper electrode is narrower than an upper portion of the upper electrode.
摘要翻译：电阻式存储器件包括形成在衬底上的下电极，形成在下电极上的电阻层和电阻层上的上电极，其中上电极的下部比上电极的上部窄。

74. 发明授权

US08518610B2 Method for fabricating photomask 失效
标题翻译：光掩模的制造方法
公开(公告)号：US08518610B2
公开(公告)日：2013-08-27
申请号：US11955332
申请日：2007-12-12
申请人： Jun Sik Lee
发明人： Jun Sik Lee
IPC分类号： G03F1/26 , G03F1/32 , G03F1/48
CPC分类号： G03F1/26 , G03F1/54 , G03F1/68
摘要： Provided is a method for fabricating a photomask. The method includes the following processes. Light blocking patterns are formed on a mask substrate, and surface properties of the mask substrate on which the light blocking patterns are formed are changed into hydrophobicity. When the surface properties of the mask substrate are changed into the hydrophobicity, the mask substrate is treated using plasma gas. The plasma gas may be a gas mixture of trifluoromethane (CHF3), tetrafluoromethane (CF4), and hydrogen (H2).
摘要翻译：提供一种制造光掩模的方法。该方法包括以下过程。遮光图案形成在掩模基板上，其上形成有遮光图案的掩模基板的表面特性变为疏水性。当掩模基板的表面特性变为疏水性时，使用等离子体气体处理掩模基板。等离子体气体可以是三氟甲烷（CHF 3），四氟甲烷（CF 4）和氢气（H 2）的气体混合物。

75. 发明授权

US08513132B2 Method for fabricating metal pattern in semiconductor device 有权
标题翻译：在半导体器件中制造金属图案的方法
公开(公告)号：US08513132B2
公开(公告)日：2013-08-20
申请号：US13324419
申请日：2011-12-13
申请人： Mi-Na Ku
发明人： Mi-Na Ku
IPC分类号： H01L21/311 , H01L21/461 , H01L21/31 , H01L21/00
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/31116 , H01L21/32136 , H01L21/76885
摘要： A method for fabricating a metal pattern in a semiconductor device includes forming a metal layer over a substrate, forming a hard mask layer over the metal layer, forming a sacrifice pattern over the hard mask layer, forming a spacer pattern on sidewalks of the sacrifice pattern, removing the sacrifice pattern, forming a hard mask pattern by etching the hard mask layer using the spacer pattern as an etch barrier, forming an etching protection layer over the hard mask pattern and on sidewalks of the hard mask pattern, and forming the metal pattern by performing primary and secondary etching processes on the metal layer using the etching protection layer as an etch barrier.
摘要翻译：在半导体器件中制造金属图案的方法包括在衬底上形成金属层，在金属层上形成硬掩模层，在硬掩模层上形成牺牲图案，在牺牲图案的人行道上形成间隔图案去除牺牲图案，通过使用间隔图案作为蚀刻阻挡层蚀刻硬掩模层形成硬掩模图案，在硬掩模图案上方和硬掩模图案的人行道上形成蚀刻保护层，并且形成金属图案通过使用蚀刻保护层作为蚀刻屏障在金属层上进行初级和次级蚀刻工艺。

76. 发明授权

US08508272B2 Data output circuit and data output method thereof 失效
标题翻译：数据输出电路及其数据输出方法
公开(公告)号：US08508272B2
公开(公告)日：2013-08-13
申请号：US12778770
申请日：2010-05-12
申请人： Jin-Il Chung
发明人： Jin-Il Chung
IPC分类号： H03L7/00
CPC分类号： H03K5/04 , H03K5/1565 , H03L7/0816
摘要： A data output circuit and a data output method thereof are provided. The data output circuit includes a delay locked loop, a duty ratio correction block, and an output unit. The delay locked loop corrects a duty ratio of a first internal clock. The delay locked loop includes a correction enable signal output unit configured to output a correction enable signal when the operation of correcting the duty ratio of the first internal clock is completed. The duty ratio correction block corrects the duty ratio of the first internal clock by using a duty ratio detection signal in response to the correction enable signal, and outputs the corrected first internal clock as an output clock. The output unit detects a duty ratio of the output clock, generates the duty ratio detection signal to the duty ratio correction block, and outputs a data strobe signal in response to the output clock.
摘要翻译：提供数据输出电路及其数据输出方法。数据输出电路包括延迟锁定环，占空比校正块和输出单元。延迟锁定环校正第一个内部时钟的占空比。所述延迟锁定环路包括校正使能信号输出单元，被配置为当校正所述第一内部时钟的占空比的操作完成时，输出校正使能信号。占空比校正块通过响应于校正使能信号使用占空比检测信号来校正第一内部时钟的占空比，并输出校正后的第一内部时钟作为输出时钟。输出单元检测输出时钟的占空比，产生与占空比校正块的占空比检测信号，并响应于输出时钟输出数据选通信号。

77. 发明授权

US08503260B2 Semiconductor memory device, method of testing the same and system of testing the same 有权
标题翻译：半导体存储器件，测试方法与测试系统相同
公开(公告)号：US08503260B2
公开(公告)日：2013-08-06
申请号：US13104262
申请日：2011-05-10
申请人： Jeong-Tae Hwang , Jeong-Hun Lee
发明人： Jeong-Tae Hwang , Jeong-Hun Lee
IPC分类号： G11C29/00 , G11C8/00
CPC分类号： G11C29/28
摘要： A method of testing a semiconductor memory device comprises receiving a clock, addresses, commands, and data from a test device through channels, generating an internal bank address in response to the addresses and the commands, performing a multi-bit parallel test for each of a plurality of banks based on the addresses, the commands, the data, and the internal bank address, and providing the test device with a test result signal.
摘要翻译：一种测试半导体存储器件的方法包括通过通道从测试设备接收时钟，地址，命令和数据，响应于地址和命令产生内部存储体地址，对每一个执行多位并行测试基于地址，命令，数据和内部存储体地址的多个存储体，以及向测试装置提供测试结果信号。

78. 发明授权

US08499175B2 Semiconductor device and method for operating the same 有权
标题翻译：半导体装置及其操作方法
公开(公告)号：US08499175B2
公开(公告)日：2013-07-30
申请号：US12964096
申请日：2010-12-09
申请人： Choung-Ki Song
发明人： Choung-Ki Song
IPC分类号： G06F1/00 , G06F1/26 , G06F12/00 , G11C5/14
CPC分类号： G11C7/1045 , G11C5/148 , G11C7/1078 , G11C7/109 , G11C2207/2227
摘要： A semiconductor device includes a first buffer element configured to buffer a first mode signal inputted from the outside of the semiconductor device, and a second buffer element configured to buffer a second mode signal inputted from the outside by being enabled in response to an output signal of the first buffer element.
摘要翻译：半导体器件包括：第一缓冲元件，被配置为缓冲从半导体器件的外部输入的第一模式信号;以及第二缓冲器元件，被配置为缓冲从外部输入的第二模式信号，该第二模式信号响应于第一个缓冲区元素。

79. 发明授权

US08493135B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US08493135B2
公开(公告)日：2013-07-23
申请号：US13100991
申请日：2011-05-04
申请人： Jae-Boum Park
发明人： Jae-Boum Park
IPC分类号： G05F1/10
CPC分类号： H02M1/36 , H02M3/07 , H02M2001/0041
摘要： A semiconductor integrated circuit includes a pre-charge signal generator configured to pre-charge a plurality of oscillation signals to a certain voltage level in a pre-charge mode, wherein the pre-charge signal generator includes: a first storage unit for storing a first pre-charge oscillation signal in response to a reference oscillation signal, a feedback unit for feeding back a second pre-charge oscillation signal, a second storage unit for storing the second pre-charge oscillation signal corresponding to an output signal of the first storage unit in response to the reference oscillation signal, and a pre-charge signal output unit for outputting a pre-charge signal in response to the first pre-charge oscillation signal and the second pre-charge oscillation signal.
摘要翻译：半导体集成电路包括预充电信号发生器，其被配置为在预充电模式下将多个振荡信号预充电到一定电压电平，其中所述预充电信号发生器包括：第一存储单元，用于存储第一响应于参考振荡信号的预充电振荡信号，用于反馈第二预充电振荡信号的反馈单元，用于存储与第一存储单元的输出信号相对应的第二预充电振荡信号的第二存储单元响应于参考振荡信号，以及预充电信号输出单元，用于响应于第一预充电振荡信号和第二预充电振荡信号而输出预充电信号。

80. 发明授权

US08493133B2 Semiconductor memory apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US08493133B2
公开(公告)日：2013-07-23
申请号：US12495005
申请日：2009-06-30
申请人： Sang-Jin Byeon
发明人： Sang-Jin Byeon
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/575
摘要： A semiconductor memory apparatus that generates a voltage by performing a pumping operation in response to an oscillator signal includes a driving voltage detecting unit configured to control the cycle of the oscillator signal in accordance with the level of a driving voltage that is used to perform the pumping operation.
摘要翻译：通过响应振荡器信号进行泵浦动作而产生电压的半导体存储装置包括：驱动电压检测单元，被配置为根据用于执行泵浦的驱动电压的电平来控制振荡器信号的周期操作。

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