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71. 发明申请

US20070096255A1 HIGH RESISTANCE CMOS RESISTOR 审中-公开
标题翻译：高电阻CMOS电阻
公开(公告)号：US20070096255A1
公开(公告)日：2007-05-03
申请号：US11567349
申请日：2006-12-06
申请人： CHIH-FENG HUANG , TUO-HSIN CHIEN
发明人： CHIH-FENG HUANG , TUO-HSIN CHIEN
IPC分类号： H01L29/00
CPC分类号： H01L28/20 , H01L27/0629 , H01L27/0802
摘要： A high resistance CMOS resistor with a relatively small die size is provided. The CMOS resistor includes a p-field region disposed in a n-well of a substrate and a pair of p-type contact regions respectively disposed beside a field oxide layer in the n-well. The pair of p-type contact regions are respectively connected to two sides of the p-field region as a first ohmic contact and a second ohmic contact for the CMOS resistor. The CMOS resistor according to the present invention has a resistance of, for example, 10 kΩ-20 kΩ per square.
摘要翻译：提供了具有相对小的管芯尺寸的高电阻CMOS电阻器。 CMOS电阻器包括设置在衬底的n阱中的p场区域和分别设置在n阱中的场氧化物层旁边的一对p型接触区域。一对p型接触区域分别连接到p场区域的两侧作为第一欧姆接触和用于CMOS电阻器的第二欧姆接触。根据本发明的CMOS电阻器具有例如每平方10kOmega-20kOmega的电阻。

72. 发明授权

US07205201B2 CMOS compatible process with different-voltage devices 有权
标题翻译： CMOS兼容过程与不同电压器件
公开(公告)号：US07205201B2
公开(公告)日：2007-04-17
申请号：US10914943
申请日：2004-08-09
申请人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
发明人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
IPC分类号： H01L21/8234
CPC分类号： H01L21/823814 , H01L21/823857 , H01L21/823892
摘要： A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.
摘要翻译：一种制造不同电压装置的方法主要包括在高电压装置区域中形成至少一个高电压阱，在低电压装置区域中形成至少一个N阱，在低电压装置区域中形成至少一个P阱，高压器件区域中的源/漏极阱以及p型衬底中的隔离区中的隔离阱。通过调制离子掺杂分布来调整击穿电压。此外，调整注入导电离子的参数，以将导电离子注入到高电压器件区域和低电压器件区域中。在器件之间的隔离区域中形成的隔离阱用于在高电压器件区域上形成的分离器件和在低电压器件区域上形成的器件。 HV栅极氧化物层的厚度比用于调制高电压器件和低电压器件的阈值电压的LV栅极氧化物层的厚度厚。

73. 发明申请

US20070080672A1 High efficiency buck converter for both full load and light load operations 有权
标题翻译：高效率降压转换器，用于满载和轻载操作
公开(公告)号：US20070080672A1
公开(公告)日：2007-04-12
申请号：US11247209
申请日：2005-10-12
申请人： Ta-Yung Yang
发明人： Ta-Yung Yang
IPC分类号： G05F1/00
CPC分类号： H02M3/1588 , H02M2001/0032 , Y02B70/1466 , Y02B70/16
摘要： A high efficiency buck converter has power-saving means to improve the efficiency under both heavy load and light load conditions. A first circuit generates an oscillation signal and a power-saving signal in response to a feedback signal. In reference to the feedback signal and the oscillation signal, a second circuit generates switching signals to control switching devices. An off-time of the switching signal increases in response to a decrement of load. The power-saving signal turns off the switching devices and parts of control circuits of the buck converter during the off-time of the switching signal for saving power under light load conditions.
摘要翻译：高效率降压转换器具有节能手段，可以在重载和轻负载条件下提高效率。第一电路响应于反馈信号产生振荡信号和功率保存信号。参考反馈信号和振荡信号，第二电路产生开关信号以控制开关装置。切换信号的关闭时间响应于负载的减小而增加。省电信号在切换信号关闭时关闭降压转换器的开关器件和部分部件，以在轻负载条件下节省电力。

74. 发明授权

US07091710B2 Low dropout voltage regulator providing adaptive compensation 有权
标题翻译：低压差稳压器提供自适应补偿
公开(公告)号：US07091710B2
公开(公告)日：2006-08-15
申请号：US10838925
申请日：2004-05-03
申请人： Ta-yung Yang , Jenn-yu G. Lin , Chien-Liang Chen
发明人： Ta-yung Yang , Jenn-yu G. Lin , Chien-Liang Chen
IPC分类号： G05F1/40
CPC分类号： G05F1/575
摘要： A method and apparatus to dynamically modify internal compensation of a low dropout (LDO) voltage regulator is provided. The LDO voltage regulator includes an output pass transistor, an error amplifier, a bias transistor and a compensation network. The compensation network is connected between a gate and a drain of the output pass transistor to compensate for the feedback loop. The compensation network and the bias transistor generate pole-zero pairs to perform a maximum 45 degrees phase shift before reaching the crossover frequency in the LDO voltage regulator. Therefore a minimum 45 degrees phase margin is provided for the feedback loop in various load conditions. Furthermore, the pole-zero pairs produced in the LDO voltage regulator are adaptively adjusted according to load conditions, so that the bandwidth is optimized and faster transient response is achieved.
摘要翻译：提供了一种用于动态修改低压差（LDO）电压调节器的内部补偿的方法和装置。 LDO稳压器包括输出传输晶体管，误差放大器，偏置晶体管和补偿网络。补偿网络连接在输出传输晶体管的栅极和漏极之间，以补偿反馈环路。补偿网络和偏置晶体管产生极点对，以在LDO稳压器达到交越频率之前执行最大45度相移。因此，在各种负载条件下，为反馈回路提供最小45度的相位裕度。此外，LDO稳压器中产生的极点对根据负载条件进行自适应调整，从而优化带宽，实现更快的瞬态响应。

75. 发明授权

US06995428B2 High voltage LDMOS transistor having an isolated structure 有权
标题翻译：具有隔离结构的高压LDMOS晶体管
公开(公告)号：US06995428B2
公开(公告)日：2006-02-07
申请号：US10786703
申请日：2004-02-24
申请人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
发明人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
IPC分类号： H01L29/76
CPC分类号： H01L29/0634 , H01L29/0878 , H01L29/0886 , H01L29/42368 , H01L29/7816
摘要： A high voltage LDMOS transistor according to the present invention includes a P-field and divided P-fields in an extended drain region of a N-well. The P-field and divided P-fields form junction-fields in the N-well, in which a drift region is fully depleted before breakdown occurs. Therefore, a higher breakdown voltage is achieved and a higher doping density of the N-well is allowed. Higher doping density can effectively reduce the on-resistance of the LDMOS transistor. Furthermore, the N-well generated beneath a source diffusion region provides a low-impedance path for a source region, which restrict the transistor current flow in between a drain region and a source region.
摘要翻译：根据本发明的高电压LDMOS晶体管包括在N阱的扩展漏极区域中的P场和分割的P场。 P场和分割的P场在N阱中形成结场，其中漂移区在击穿之前被完全耗尽。因此，实现更高的击穿电压，并且允许N阱的较高的掺杂密度。较高的掺杂密度可以有效降低LDMOS晶体管的导通电阻。此外，在源极扩散区域之下产生的N阱为源极区域提供了低阻抗路径，其限制了漏极区域和源极区域之间的晶体管电流。

76. 发明授权

US06977824B1 Control circuit for controlling output current at the primary side of a power converter 有权
标题翻译：控制电路，用于控制功率转换器初级侧的输出电流
公开(公告)号：US06977824B1
公开(公告)日：2005-12-20
申请号：US10914802
申请日：2004-08-09
申请人： Ta-yung Yang , Guo-Kiang Hung
发明人： Ta-yung Yang , Guo-Kiang Hung
IPC分类号： H02M3/335
CPC分类号： H02M3/33507
摘要： A control circuit controlling output current at the primary side of a power converter is provided. A waveform detector generates a current-waveform signal. A discharge-time detector detects a discharge-time of a secondary side switching current. An oscillator generates an oscillation signal for determining the switching frequency of the switching signal. An integrator generates an integrated signal by integrating an average current signal with the discharge-time. The average current signal is generated in response to the current-waveform signal. The time constant of the integrator is correlated with the switching period of the switching signal, therefore the integrated signal is proportional to the output current. An error amplifier amplifies the integrated signal and provides a loop gain for output current control. A comparator controls the pulse width of the switching signal in reference to the output of the error amplifier. Therefore, the output current of the power converter can be regulated.
摘要翻译：提供控制电源转换器初级侧的输出电流的控制电路。波形检测器产生电流波形信号。放电时间检测器检测次级侧开关电流的放电时间。振荡器产生用于确定开关信号的开关频率的振荡信号。积分器通过将平均电流信号与放电时间进行积分来产生积分信号。响应于电流波形信号产生平均电流信号。积分器的时间常数与开关信号的开关周期相关，因此积分信号与输出电流成正比。误差放大器放大积分信号，并为输出电流控制提供环路增益。比较器参考误差放大器的输出控制开关信号的脉冲宽度。因此，可以调节功率转换器的输出电流。

77. 发明授权

US06952354B1 Single stage PFC power converter 有权
标题翻译：单级PFC功率转换器
公开(公告)号：US06952354B1
公开(公告)日：2005-10-04
申请号：US10859811
申请日：2004-06-03
申请人： Ta-yung Yang , Song-Yi Lin , Tso Min Chen
发明人： Ta-yung Yang , Song-Yi Lin , Tso Min Chen
IPC分类号： H02M1/00 , H02M1/42 , H02M3/335
CPC分类号： H02M1/4258 , H02M3/3353 , Y02B70/126 , Y02P80/112
摘要： A single stage PFC power converter is provided for performing a PFC function in a half-bridge flyback power converter. A high-side switch and a low-side switch periodically supply an input voltage to a primary winding of a transformer. When the high-side switch and low-side switch are switched off, the energy stored in the transformer will be transmitted to a secondary circuit and charged to a bulk capacitor. The bulk capacitor serves to recycle the energy and reduce the output ripple noise. A forward diode and a forward inductor serve to forward the energy of the bulk capacitor to the flowing path of the input voltage for performing PFC function.
摘要翻译：提供单级PFC功率转换器，用于在半桥反激式功率转换器中执行PFC功能。高侧开关和低侧开关周期性地向变压器的初级绕组提供输入电压。当高侧开关和低侧开关关闭时，存储在变压器中的能量将传输到次级电路并充电到大容量电容器。大容量电容器用于回收能量并减少输出纹波噪声。正向二极管和正向电感器用于将大容量电容器的能量转发到用于执行PFC功能的输入电压的流动路径。

78. 发明授权

US06873011B1 High voltage and low on-resistance LDMOS transistor having equalized capacitance 失效
标题翻译：具有均衡电容的高电压和低导通电阻LDMOS晶体管
公开(公告)号：US06873011B1
公开(公告)日：2005-03-29
申请号：US10786701
申请日：2004-02-24
申请人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
发明人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
IPC分类号： H01L29/06 , H01L29/78 , H01L29/94
CPC分类号： H01L29/7816 , H01L29/0623 , H01L29/0634 , H01L29/0696
摘要： A high voltage LDMOS transistor according to the present invention includes P-field blocks in the extended drain region of a N-well. The P-field blocks form the junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete the drift region before breakdown occurs. A higher breakdown voltage is therefore achieved and the N-well having a higher doping density is thus allowed. The higher doping density reduces the on-resistance of the transistor. Furthermore, the portion of the N-well generated beneath the source diffusion region produces a low-impedance path for the source region, which restricts the transistor current flow in between the drain region and the source region.
摘要翻译：根据本发明的高电压LDMOS晶体管包括N阱扩展漏极区中的P场区块。 P-场块形成N阱中的结场，用于均衡漏极区域和源极区域之间的寄生电容器的电容，并且在击穿之前完全耗尽漂移区域。因此实现更高的击穿电压，因此允许具有较高掺杂密度的N阱。较高的掺杂密度降低了晶体管的导通电阻。此外，在源极扩散区域之下产生的N阱的部分产生用于源极区域的低阻抗路径，其限制了漏极区域和源极区域之间的晶体管电流。

79. 发明授权

US06862194B2 Flyback power converter having a constant voltage and a constant current output under primary-side PWM control 失效
标题翻译：反激式功率转换器在初级侧PWM控制下具有恒定电压和恒定电流输出
公开(公告)号：US06862194B2
公开(公告)日：2005-03-01
申请号：US10465467
申请日：2003-06-18
申请人： Ta-yung Yang , Chern-Lin Chen , Jenn-yu G. Lin , Song-Yi Lin
发明人： Ta-yung Yang , Chern-Lin Chen , Jenn-yu G. Lin , Song-Yi Lin
IPC分类号： H02M3/335 , H02M7/04
CPC分类号： H02M3/33507 , H02M2001/0006
摘要： A primary-side flyback power converter supplies a constant voltage and a constant current output. To generate a well-regulated output voltage under varying load conditions, the power converter includes a PWM controller. The PWM controller generates a PWM signal to control a switching transistor in response to a flyback voltage detected from the first primary winding of the power supply transformer. To reduce power consumption, the flyback energy of the first primary winding is used as a DC power source for the PWM controller. The flyback voltage is sampled following a delay time to reduce interference from the inductance leakage of the transformer. To generate a more accurate DC output voltage, a bias current is pulled from the detection input to form a voltage drop across a detection resistor for compensating for the voltage drop of the output rectifying diode.
摘要翻译：初级侧反激式功率转换器提供恒定电压和恒定电流输出。为了在变化的负载条件下产生良好调节的输出电压，功率转换器包括PWM控制器。 PWM控制器产生PWM信号以响应于从电源变压器的第一初级绕组检测到的回扫电压来控制开关晶体管。为了降低功耗，第一个初级绕组的回扫能量被用作PWM控制器的直流电源。在延迟时间之后对回扫电压进行采样，以减少变压器的电感泄漏引起的干扰。为了产生更精确的直流输出电压，从检测输入端拉出偏置电流，在检测电阻上形成电压降，以补偿输出整流二极管的电压降。

80. 发明授权

US06861827B1 Low drop-out voltage regulator and an adaptive frequency compensation 失效
标题翻译：低压差稳压器和自适应频率补偿
公开(公告)号：US06861827B1
公开(公告)日：2005-03-01
申请号：US10666803
申请日：2003-09-17
申请人： Ta-yung Yang , Hsuan-I Pan , Chern-Lin Chen
发明人： Ta-yung Yang , Hsuan-I Pan , Chern-Lin Chen
IPC分类号： G05F1/575 , G05F3/26 , G05F1/40
CPC分类号： G05F1/575 , G05F3/262
摘要： A method and apparatus to dynamically modify the internal compensation of a low drop-out (LDO) voltage regulator is presented. The process involves creating an additional equivalent series resistance (ESR) from an internal circuit. The additional ESR of the internal circuit is sufficient to ensure the DC output stability. This allows the ESR of the output capacitance to be reduced to zero if desired, for improved transient response.
摘要翻译：提出了一种动态修改低压差（LDO）稳压器内部补偿的方法和装置。该过程涉及从内部电路产生额外的等效串联电阻（ESR）。内部电路的额外ESR足以确保直流输出稳定。如果需要，这允许输出电容的ESR减小到零，以改善瞬态响应。

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