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71. 发明授权

US07619937B2 Semiconductor memory device with reset during a test mode 有权
标题翻译：半导体存储器件，在测试模式下复位
公开(公告)号：US07619937B2
公开(公告)日：2009-11-17
申请号：US11819819
申请日：2007-06-29
申请人： Tae-Sik Yun , Kee-Teok Park
发明人： Tae-Sik Yun , Kee-Teok Park
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C7/1078 , G11C7/109 , G11C7/20 , G11C29/1201 , G11C29/46
摘要： A semiconductor memory device performs a reset operation at a wafer state by using a signal input through an address pin in a test mode. The semiconductor memory device includes a buffer for transferring a reset command in response to a reset-active signal and a test reset signal, a test-reset entry signal generation unit for generating an internal test-reset entry signal in response to the test reset signal, and a rest signal driving unit for driving an active signal of an output signal of the buffer and the internal test-reset entry signal as an internal reset signal for a reset mode entry.
摘要翻译：半导体存储器件通过在测试模式下通过地址引脚输入的信号在晶片状态下执行复位操作。半导体存储器件包括用于响应于复位有效信号和测试复位信号传送复位指令的缓冲器，用于响应于测试复位信号产生内部测试复位输入信号的测试复位输入信号产生单元以及用于驱动缓冲器的输出信号的有效信号和内部测试复位输入信号的休息信号驱动单元作为复位模式输入的内部复位信号。

72. 发明授权

US07615451B2 Method for forming semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US07615451B2
公开(公告)日：2009-11-10
申请号：US11819852
申请日：2007-06-29
申请人： Yoon Suk Hyun
发明人： Yoon Suk Hyun
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/3086 , H01L27/1052
摘要： A method for forming a semiconductor device is provided. More specifically, a method for forming a bulb-shaped portion of a bulb-shaped recess gate is provided to overcome an etching process margin reduction caused by a spacer oxide film formed on sidewalls of a recess and thickly laminated to a lower part of a recess. In one aspect, a buffer dielectric film pattern is formed additionally by a plasma enhanced chemical vapor deposition (PECVD) process over a hard mask pattern, so that a sufficient process margin used for forming the bulb-shaped portion is ensured and a process margin for forming a semiconductor device is increased.
摘要翻译：提供一种形成半导体器件的方法。更具体地，提供了一种用于形成灯泡状凹槽的灯泡形部分的方法，以克服由形成在凹槽的侧壁上的厚度层叠到凹部的下部的间隔氧化膜引起的蚀刻工艺边缘减小。在一个方面，通过在硬掩模图案上的等离子体增强化学气相沉积（PECVD）工艺另外形成缓冲电介质膜图案，从而确保用于形成灯泡形部分的足够的工艺余量和用于形成半导体器件增加。

73. 发明授权

US07606674B2 On die thermal sensor 失效
标题翻译：模具热传感器
公开(公告)号：US07606674B2
公开(公告)日：2009-10-20
申请号：US11819792
申请日：2007-06-29
申请人： Jong-Ho Jung
发明人： Jong-Ho Jung
IPC分类号： G01K7/00
CPC分类号： G01K7/01 , G01K7/425
摘要： An on die thermal sensor includes a bandgap unit for generating a first voltage containing temperature information, a tracking unit for tracking a voltage level of the first voltage, and a low power control unit for generating a tracking enable signal for enabling the tracking unit and disabling the tracking unit after a minimum tracking operation time of the tracking unit elapses.
摘要翻译：散热片传感器包括用于产生含有温度信息的第一电压的带隙单元，用于跟踪第一电压的电压电平的跟踪单元，以及用于产生用于启用跟踪单元和禁用的跟踪使能信号的低功率控制单元在跟踪单元的最小跟踪操作时间过去之后的跟踪单元。

74. 发明授权

US07800481B2 RFID device having a nonvolatile ferroelectric memory 有权
标题翻译：具有非易失性铁电存储器的RFID装置
公开(公告)号：US07800481B2
公开(公告)日：2010-09-21
申请号：US11482029
申请日：2006-07-07
申请人： Hee Bok Kang , Jin Hong Ahn
发明人： Hee Bok Kang , Jin Hong Ahn
IPC分类号： H04Q5/22 , G11C7/10 , G11C7/00
CPC分类号： G06K19/07749 , G06K19/0701
摘要： A radio frequency identification (RFID) device includes an antenna configured to transmit or receive a radio frequency signal to or from an external communication apparatus; an analog block configured to generate a first power voltage in response to the radio frequency signal; a digital block configured to receive the first power voltage from the analog block, to transmit a response signal to the analog block, and to output a memory control signal; and a memory configured to read/write data in response to the memory control signal, the memory including a high voltage generating unit for generating a second power voltage from the first power voltage, a first portion driven by the second power voltage, and a second portion driven by the first power voltage, wherein the level of the first power voltage is lower than that of the second power voltage.
摘要翻译：射频识别（RFID）设备包括配置成向外部通信设备发送或接收射频信号的天线; 模拟块，被配置为响应于所述射频信号产生第一电源电压; 配置成从所述模拟块接收所述第一电源电压的数字模块，向所述模拟模块发送响应信号，并输出存储器控制信号; 以及存储器，被配置为响应于所述存储器控制信号读/写数据，所述存储器包括用于从所述第一电源电压产生第二电源电压的高电压产生单元，由所述第二电源电压驱动的第一部分，部分由第一电源电压驱动，其中第一电源电压的电平低于第二电源电压的电平。

75. 发明授权

US07786847B2 Radio frequency identification device 失效
标题翻译：射频识别装置
公开(公告)号：US07786847B2
公开(公告)日：2010-08-31
申请号：US11812832
申请日：2007-06-22
申请人： Hee Bok Kang
发明人： Hee Bok Kang
IPC分类号： H03K17/62
CPC分类号： G01K1/024
摘要： An RFID device includes an analog block configured to receive a radio frequency signal so as to output an operation command signal, a digital block configured to output an address, a temperature address, an operation control signal, and a temperature sensor activation signal in response to the operation command signal received from the analog block and to provide a corresponding response signal into the analog block. The device further includes a memory block configured to receive the address, the temperature address, and the operation control signal so as to generate an internal control signal for controlling the internal operation, and to read/write data in a cell array including a non-volatile ferroelectric capacitor in response to the internal control signal, and a temperature sensor processing unit configured to detect a temperature change state of an RFID tag in response to the temperature sensor activation signal.
摘要翻译： RFID装置包括：模拟块，被配置为接收射频信号以输出操作命令信号;数字块，被配置为输出地址，温度地址，操作控制信号和温度传感器激活信号，以响应于所述操作命令信号从所述模拟块接收并且向所述模拟块提供相应的响应信号。该装置还包括一个存储块，被配置为接收地址，温度地址和操作控制信号，以便产生用于控制内部操作的内部控制信号，并且读取/写入包括非易失性存储器的单元阵列中的数据，响应于内部控制信号的挥发性铁电电容器;以及温度传感器处理单元，被配置为响应于温度传感器激活信号来检测RFID标签的温度变化状态。

76. 发明授权

US07786020B1 Method for fabricating nonvolatile memory device 失效
标题翻译：非易失性存储器件的制造方法
公开(公告)号：US07786020B1
公开(公告)日：2010-08-31
申请号：US12647052
申请日：2009-12-24
申请人： Hye-Ran Kang , Sung-Yoon Cho
发明人： Hye-Ran Kang , Sung-Yoon Cho
IPC分类号： H01L21/302
CPC分类号： H01L21/31138 , H01L21/02071 , H01L21/0273 , H01L21/28123 , H01L21/28273 , H01L21/31116 , H01L21/31144 , H01L21/32137 , H01L21/32139
摘要： A method for fabricating a nonvolatile memory device includes repeatedly stacking a stacked structure over a substrate to form a multi-stacked structure, wherein the stacked structure includes a conductive layer and an insulation layer, forming a photoresist pattern over the multi-stacked structure, first-etching an uppermost stacked structure of the multi-stacked structure using the photoresist pattern as an etch barrier, second-etching a resultant structure formed by the first-etching through the use of a breakthrough etching, slimming the photoresist pattern to form a slimmed photoresist pattern, and third-etching the uppermost stacked structure using the slimmed photoresist pattern as an etch barrier and, at the same time, etching a stacked structure disposed under the uppermost stacked structure and exposed by the first-etching.
摘要翻译：一种非易失性存储器件的制造方法，其特征在于，在基板上重叠层叠叠层结构，形成多层叠结构体，其特征在于，叠层结构包括导电层和绝缘层，在多层叠结构上形成光致抗蚀剂图案 - 使用光致抗蚀剂图案作为蚀刻阻挡层来蚀刻多层叠结构的最上层叠结构，通过使用穿透蚀刻来第二蚀刻通过第一蚀刻形成的结构结构，使光致抗蚀剂图案减薄以形成纤薄的光致抗蚀剂并且使用薄的光致抗蚀剂图案作为蚀刻阻挡层对第一层叠结构进行第三蚀刻，并且同时蚀刻设置在最上层叠结构下方并通过第一蚀刻曝光的层叠结构。

77. 发明授权

US07782647B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07782647B2
公开(公告)日：2010-08-24
申请号：US12204190
申请日：2008-09-04
申请人： Eun-Souk Lee , Kang-Seol Lee
发明人： Eun-Souk Lee , Kang-Seol Lee
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C7/1012 , G11C7/1048 , G11C11/4093 , G11C11/4097 , G11C2207/002
摘要： A semiconductor memory device has a simple layout pattern of a sub hole region. The semiconductor memory device includes a segment input/output line, a first local input/output line and a second local input/output line corresponding to the segment input/output line, an input/output switch configured to selectively connect the segment input/output line and the first local input/output line in response to a first switch control signal, and a dummy input/output switch which is connected to a second local input/output line but is not connected to the segment input/output line.
摘要翻译：半导体存储器件具有子孔区域的简单布局图案。半导体存储器件包括分段输入/输出线，对应于分段输入/输出线的第一局部输入/输出线和第二本地输入/输出线，配置成选择性地连接分段输入/输出以及响应于第一开关控制信号的第一本地输入/输出线，以及连接到第二本地输入/输出线但未连接到段输入/输出线的虚拟输入/输出开关。

78. 发明授权

US07781336B2 Semiconductor device including ruthenium electrode and method for fabricating the same 有权
标题翻译：包括钌电极的半导体器件及其制造方法
公开(公告)号：US07781336B2
公开(公告)日：2010-08-24
申请号：US11978604
申请日：2007-10-30
申请人： Jin-Hyock Kim , Jae-Sung Roh , Seung-Jin Yeom , Kee-Jeung Lee , Han-Sang Song , Deok-Sin Kil , Young-Dae Kim
发明人： Jin-Hyock Kim , Jae-Sung Roh , Seung-Jin Yeom , Kee-Jeung Lee , Han-Sang Song , Deok-Sin Kil , Young-Dae Kim
IPC分类号： H01L21/00
CPC分类号： H01L21/32136 , H01L21/32115 , H01L21/76843 , H01L21/76865 , H01L28/65
摘要： A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a first plug filled in a portion of the contact hole, a diffusion barrier layer formed above the first plug and in a bottom portion and on sidewalls of a remaining portion of the contact hole, a second plug formed on the diffusion barrier layer and filled in the contact hole, and a storage node coupled to and formed on the second plug.
摘要翻译：半导体器件包括半导体衬底，半导体衬底上的绝缘图案和绝缘图案上的蚀刻停止层，绝缘图案和蚀刻停止层限定暴露衬底的接触孔，第一插头填充在部分在所述第一插头上形成的扩散阻挡层，在所述接触孔的剩余部分的底部和侧壁上形成的扩散阻挡层，形成在所述扩散阻挡层上并填充在所述接触孔中的第二插塞，耦合到并形成在第二插头上的节点。

79. 发明授权

US07773709B2 Semiconductor memory device and method for operating the same 失效
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US07773709B2
公开(公告)日：2010-08-10
申请号：US11646418
申请日：2006-12-28
申请人： Sang-Hee Lee
发明人： Sang-Hee Lee
IPC分类号： H04L7/00
CPC分类号： G11C7/1039 , G11C7/1006 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C2207/107
摘要： A semiconductor memory device includes an aligning signal generator, a data aligning unit, a data transmitting controller and a data transmitter. The aligning signal generator receives a data strobe signal to output aligning signals. The data aligning unit aligns a plurality of data pieces input in succession in response to the aligning signals. The data transmitting controller generates a data transmitting signal synchronized with the transition of the aligning signal. The data transmitter transmits an aligned data output from the data aligning unit to a data storage area in response to the data transmitting signal. A method for driving the semiconductor memory device includes aligning data pieces input in succession as parallel data in response to a data strobe signal, generating a data transmitting signal corresponding to transition of the data strobe signal and transmitting the parallel data to a data storage area in response to the data transmitting signal.
摘要翻译：半导体存储器件包括对准信号发生器，数据对准单元，数据发送控制器和数据发送器。对准信号发生器接收数据选通信号以输出对准信号。数据对齐单元响应于对准信号对准连续输入的多个数据段。数据发送控制器产生与对准信号的转换同步的数据发送信号。数据发送器响应于数据发送信号将从数据对准单元输出的对准数据发送到数据存储区域。一种用于驱动半导体存储器件的方法包括响应于数据选通信号将连续输入的数据片段对准为并行数据，产生与数据选通信号的转换相对应的数据发送信号，并将并行数据发送到数据存储区域响应数据发送信号。

80. 发明授权

US07773440B2 ZQ calibration controller and method for ZQ calibration 有权
标题翻译： ZQ校准控制器和ZQ校准方法
公开(公告)号：US07773440B2
公开(公告)日：2010-08-10
申请号：US11967699
申请日：2007-12-31
申请人： Ki-Ho Kim , Kee-Teok Park
发明人： Ki-Ho Kim , Kee-Teok Park
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1057 , G11C7/1072 , G11C7/1084 , G11C2207/2254
摘要： A ZQ calibration circuit performs a ZQ calibration additionally in an initial operation of a semiconductor memory device. The ZQ calibration controller of the ZQ calibration circuit includes a first signal generator, a second signal generator, and a control unit. The first signal generator generates a pre-calibration signal during an initialization of the semiconductor memory device. The second signal generator generates ZQ calibration signals in response to a ZQ calibration command. The control unit outputs signals to control a ZQ calibration in response to the pre-calibration signal and the ZQ calibration signals.
摘要翻译： ZQ校准电路在半导体存储器件的初始操作中另外执行ZQ校准。 ZQ校准电路的ZQ校准控制器包括第一信号发生器，第二信号发生器和控制单元。第一信号发生器在半导体存储器件的初始化期间产生预校准信号。第二信号发生器响应于ZQ校准命令产生ZQ校准信号。控制单元响应于预校准信号和ZQ校准信号输出信号以控制ZQ校准。

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