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71. 发明申请

US20070176253A1 Transistor, memory cell and method of manufacturing a transistor 审中-公开
标题翻译：晶体管，存储单元及制造晶体管的方法
公开(公告)号：US20070176253A1
公开(公告)日：2007-08-02
申请号：US11343812
申请日：2006-01-31
申请人： Peng-Fei Wang , Rolf Weis , Joachim Nuetzel , Arnd Scholz , Alexander Sieck , Sigurd Zehner
发明人： Peng-Fei Wang , Rolf Weis , Joachim Nuetzel , Arnd Scholz , Alexander Sieck , Sigurd Zehner
IPC分类号： H01L29/00
CPC分类号： H01L27/10876 , H01L27/10867
摘要： A transistor which can in particular be used in memory cells of a Dynamic Random Access Memory a memory cell and a method of manufacturing a transistor is disclosed. In one embodiment the transistor is a dual-fin field effect transistor. The transistor includes a first and a second source/drain regions, a channel connecting the first and second source/drain regions, a gate electrode for controlling an electrical current flowing between the first and second source/drain regions. The gate electrode is insulated from the channel by a gate dielectric, wherein the gate electrode is disposed in a gate groove extending in the substrate surface so that the channel comprises two fin-like channel portions extending between the first and second source/drain regions in a cross-sectional view taken perpendicularly to a line connecting the first and the second source/drain regions, the gate electrode delimiting each of the fin-like channel portions at one side thereof.
摘要翻译：公开了一种特别可用于动态随机存取存储器存储单元的存储单元的晶体管，以及制造晶体管的方法。在一个实施例中，晶体管是双鳍场效应晶体管。晶体管包括第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道，用于控制在第一和第二源极/漏极区域之间流动的电流的栅电极。栅极通过栅极电介质与沟道绝缘，其中栅电极设置在在衬底表面中延伸的栅极沟槽中，使得沟道包括在第一和第二源极/漏极区之间延伸的两个鳍状沟道部分垂直于连接第一和第二源极/漏极区域的线截取的截面图，栅极电极在其一侧限定每个鳍状沟道部分。

72. 发明授权

US07208418B1 Sealing sidewall pores in low-k dielectrics 有权
标题翻译：密封低k电介质中的侧壁孔
公开(公告)号：US07208418B1
公开(公告)日：2007-04-24
申请号：US10728774
申请日：2003-12-08
申请人： Lynne A. Okada , Minh Quoc Tran , Fei Wang , Lu You
发明人： Lynne A. Okada , Minh Quoc Tran , Fei Wang , Lu You
IPC分类号： H01L21/311
CPC分类号： H01L21/76831
摘要： Barrier metal layer discontinuities or gaps due to low-k dielectric porosity is reduced by sealing sidewall porosity before barrier metal layer deposition. Embodiments include sealing sidewall porosity by depositing a swelling agent, adhesion promoter or an additional layer of low-k material.
摘要翻译：通过在阻挡金属层沉积之前密封侧壁孔隙率来减少由于低k介电孔隙导致的阻挡金属层不连续性或间隙。实施例包括通过沉积溶胀剂，粘合促进剂或低k材料的附加层来密封侧壁孔隙。

73. 发明授权

US07038320B1 Single damascene integration scheme for preventing copper contamination of dielectric layer 有权
标题翻译：用于防止介电层铜污染的单镶嵌一体化方案
公开(公告)号：US07038320B1
公开(公告)日：2006-05-02
申请号：US09785445
申请日：2001-02-20
申请人： Lu You , Fei Wang , Minh Van Ngo
发明人： Lu You , Fei Wang , Minh Van Ngo
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/76832 , H01L21/76802 , H01L21/76804 , H01L21/76814 , H01L21/76834
摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The first etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A second etch stop layer can also be disposed between the first diffusion barrier layer and the first etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化层，第一扩散阻挡层，第一蚀刻停止层，介电层和延伸穿过介电层的通孔，第一蚀刻停止层和第一扩散阻挡层。第一扩散阻挡层设置在第一金属化层上。第一蚀刻停止层设置在第一扩散阻挡层上并与第一扩散阻挡层隔开，并且介电层设置在第一蚀刻停止层上。通孔也可以有圆角。第二蚀刻停止层也可以设置在第一扩散阻挡层和第一蚀刻停止层之间。侧壁扩散阻挡层可以设置在通孔的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。还公开了制造半导体器件的方法。

74. 发明申请

US20060017155A1 FLIP CHIP PACKAGE CAPABLE OF MEASURING BOND LINE THICKNESS OF THERMAL INTERFACE MATERIAL 有权
标题翻译：用于测量热界面材料的粘合线厚度的FLIP芯片封装
公开(公告)号：US20060017155A1
公开(公告)日：2006-01-26
申请号：US10895052
申请日：2004-07-21
申请人： Sung-Fei Wang
发明人： Sung-Fei Wang
IPC分类号： H01L23/06 , H01L23/10
CPC分类号： H01L23/3675 , H01L23/36 , H01L23/3672 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253 , H01L2224/83385 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2924/16151 , H01L2924/16152 , H01L2924/16195 , H01L2924/16251 , H01L2924/00 , H01L2224/0401
摘要： A flip chip package includes a substrate, a flip chip, a thermal interface material and a heat sink. The flip chip is mounted on the substrate. The thermal interface material is applied on the back surface of the flip chip. The back surface of the flip chip includes a region uncovered by the thermal interface material. The opening exposes the uncover region of the back surface of the flip chip for measuring the height of the back surface. Also the opening has an inner sidewall above the back surface for fillet bonding of the thermal interface material. Therefore the bond line thickness (BLT) of the thermal interface material can be measured and calculated.
摘要翻译：倒装芯片封装包括衬底，倒装芯片，热界面材料和散热器。倒装芯片安装在基板上。将热界面材料涂覆在倒装芯片的背面上。倒装芯片的背面包括未被热界面材料覆盖的区域。开口露出用于测量后表面的高度的倒装芯片的后表面的露出区域。此外，开口具有在后表面上方的内侧壁，用于热界面材料的圆角接合。因此，可以测量和计算热界面材料的粘合线厚度（BLT）。

75. 发明授权

US06943153B1 Use of recombinant gene delivery vectors for treating or preventing diseases of the eye 有权
标题翻译：使用重组基因递送载体治疗或预防眼睛疾病
公开(公告)号：US06943153B1
公开(公告)日：2005-09-13
申请号：US09665493
申请日：2000-09-20
申请人： William C. Manning, Jr. , Varavani J. Dwarki , Katherine Rendahl , Shangzhen Zhou , Sheldon S. Miller , Fei Wang
发明人： William C. Manning, Jr. , Varavani J. Dwarki , Katherine Rendahl , Shangzhen Zhou , Sheldon S. Miller , Fei Wang
IPC分类号： A61K38/17 , A61K38/18 , A61K38/19 , A61K48/00 , C07K14/50 , C07K14/52 , A01N43/04 , A01N63/00 , A61K31/70 , A61K39/23 , A61K39/235
CPC分类号： A01K67/0275 , A01K2217/052 , A01K2267/03 , A61K38/179 , A61K38/185 , A61K38/57 , A61K48/00 , C07K14/50 , C07K14/52 , C12N2799/025
摘要： Gene delivery vectors, such as, for example, recombinant adeno-associated viral vectors, and methods of using such vectors are provided for use in treating or preventing diseases of the eye.
摘要翻译：提供基因递送载体，例如重组腺相关病毒载体，以及使用这些载体的方法用于治疗或预防眼睛疾病。

76. 发明授权

US06937442B2 Contacting point damping method between flex circuit and pivot housing 失效
标题翻译：柔性电路和枢轴外壳之间的接点阻尼方法
公开(公告)号：US06937442B2
公开(公告)日：2005-08-30
申请号：US10175969
申请日：2002-06-20
申请人： (Leon) Liyang Zhao , (Peter) Fei Wang , Kenneth A. Haapala
发明人： (Leon) Liyang Zhao , (Peter) Fei Wang , Kenneth A. Haapala
IPC分类号： G11B5/58 , G11B5/60 , G11B5/54
CPC分类号： G11B5/58 , G11B5/60
摘要： The present invention for a disk drive is a damping feature applied to the contact area between the flexible circuit and the pivot housing, reducing the resonance energy transferred from the flexible circuit to the pivot housing. This invention reduces the direct energy transfer from the flexible circuit to the pivot house by applying a damping feature as embodied by damping material on the flexible circuit or pivot housing at the point at which they make contact or by adding a damper to the flexible circuit re-routing tip area between the pivot housing and the flexible circuit. The damping feature absorbs the resonance energy from the flexible circuit to the damping feature material and reduces the energy transferred from the flexible circuit to the pivot housing.
摘要翻译：用于盘驱动器的本发明是应用于柔性电路和枢转壳体之间的接触区域的阻尼特征，减少了从柔性电路传递到枢转壳体的共振能量。本发明通过施加阻尼特征来减少直接能量从柔性电路传递到枢纽房屋的阻力特征，如阻尼材料在柔性电路或枢轴壳体上的阻尼材料在它们接触的点处或者通过向柔性电路re添加阻尼器在枢轴壳体和柔性电路之间的引导尖端区域。阻尼特征吸收从柔性电路到阻尼特征材料的共振能量，并且减少从柔性电路传递到枢转壳体的能量。

77. 发明授权

US06936930B2 Thermal enhance MCM package 有权
标题翻译：热增强MCM封装
公开(公告)号：US06936930B2
公开(公告)日：2005-08-30
申请号：US10747038
申请日：2003-12-30
申请人： Sung-Fei Wang
发明人： Sung-Fei Wang
IPC分类号： H01L23/36 , H01L23/498 , H01L25/065 , H05K1/02 , H05K1/14 , H05K3/34 , H01I23/48
CPC分类号： H01L23/49816 , H01L23/36 , H01L23/49833 , H01L25/0652 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H05K1/0203 , H05K1/141 , H05K3/3436 , H05K2201/066 , H01L2224/0401
摘要： A thermal enhance multi-chips module package mainly comprises an assembly substrate, a first assembly package, a second assembly package, a heat dissipation board, and a thermally conductive metal ring. The first assembly package and the second assembly package are disposed on the upper surface and the lower surface of the assembly substrate respectively; and the thermally conductive metal ring is disposed at the periphery of the upper surface of the heat dissipation board and encompasses the second assembly package. The second assembly package has a logic chip therein and generates a lot of heat, and the heat dissipation board can transmit the heat to the outside through the thermally conductive metal ring so as to prevent the excessive heat from transmitting to the motherboard and accumulating in the motherboard. Accordingly, the motherboard can be avoided damaging.
摘要翻译：热增强多芯片模块封装主要包括组装衬底，第一组件封装，第二组件封装，散热板和导热金属环。第一组装包和第二组装包分别设置在组装衬底的上表面和下表面上; 并且所述导热金属环设置在所述散热板的上表面的周边并且包围所述第二组装包装。第二组装封装在其中具有逻辑芯片并产生大量热量，并且散热板可以通过导热金属环将热量传递到外部，以防止过热传递到母板并积聚在母板。因此，可以避免主板的损坏。

78. 发明授权

US06879031B2 Multi-chips package 有权
标题翻译：多芯片包装
公开(公告)号：US06879031B2
公开(公告)日：2005-04-12
申请号：US10747189
申请日：2003-12-30
申请人： Sung-Fei Wang
发明人： Sung-Fei Wang
IPC分类号： H01L25/065 , H01L23/02 , H01L23/48
CPC分类号： H01L25/0657 , H01L2224/16145 , H01L2224/73253 , H01L2225/06513 , H01L2225/06517 , H01L2225/06555 , H01L2225/06586 , H01L2225/06589 , H01L2924/00014 , H01L2924/15151 , H01L2924/15311 , H01L2924/16152 , H01L2224/0401
摘要： A multi-chips package at least comprises a substrate, an upper chip, a lower chip, a reinforced device, and a plurality of electrically conductive bumps. The upper chip is flip-chip bonded to the upper surface of the substrate and the lower chip is accommodated in the opening and flip-chip bonded to the upper chip. Furthermore, the reinforced device is mounted onto the back surface of the lower chip and the lower surface of the substrate. The coefficient of the thermal expansion of the reinforced device ranges from the coefficient of the thermal expansion of the substrate to the coefficient of the thermal expansion of the chip. In such a manner, the reinforced device can constrain the thermal deformation of the substrate so as to prevent the electrically conductive bumps connecting the first chip and the substrate from being damaged.
摘要翻译：多芯片封装至少包括基板，上芯片，下芯片，增强器件和多个导电凸块。上芯片被倒装贴合到基板的上表面，并且下芯片容纳在开口中并且倒装芯片接合到上芯片。此外，加强装置安装在下芯片的背面和基板的下表面上。加强装置的热膨胀系数从基板的热膨胀系数到芯片的热膨胀系数的范围。以这种方式，加强装置可以限制基板的热变形，以防止连接第一芯片和基板的导电凸块被损坏。

79. 发明申请

US20050046039A1 Flip-chip package 有权
标题翻译：倒装芯片封装
公开(公告)号：US20050046039A1
公开(公告)日：2005-03-03
申请号：US10648237
申请日：2003-08-27
申请人： Chaur-Chin Yang , Sung-Fei Wang
发明人： Chaur-Chin Yang , Sung-Fei Wang
IPC分类号： H01L23/24 , H01L23/498 , H01L25/10 , H01L23/02 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/49816 , H01L23/24 , H01L24/48 , H01L25/105 , H01L2224/16225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2225/1023 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/01087 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19107 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A flip-chip package comprises a substrate with an opening. A dummy die is disposed onto the substrate corresponding to the opening so as to form a composite chip carrier with a chip cavity. The dummy die has a redistribution layer which includes a plurality of flip-chip pads for flip-chip connection of a chip and a plurality of connecting pads around the dummy die for connecting the substrate. The dummy die mounts at least a chip by flip chip connection for being an electrical interface medium between the chip and the substrate in order to achieve thinner package thickness, high heat dissipation, fine pitch flip-chip mounting and eliminating flip-chip stress on the chip.
摘要翻译：倒装芯片封装包括具有开口的基板。将虚设裸片设置在与开口对应的基板上，以形成具有芯片腔的复合芯片载体。该虚设裸片具有再分配层，该再分配层包括用于芯片倒装芯片连接的多个倒装芯片焊盘和用于连接衬底的虚设裸片周围的多个连接焊盘。该虚设芯片通过倒装芯片连接至少安装一个芯片，作为芯片和基板之间的电接口介质，以实现更薄的封装厚度，高散热，精细的俯仰倒装芯片安装以及消除倒装芯片上的倒装芯片应力芯片。

80. 发明授权

US06664185B1 Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect 有权
标题翻译：由具有至少两个掺杂元素的合金形成的自对准屏障，用于最小化互连电阻
公开(公告)号：US06664185B1
公开(公告)日：2003-12-16
申请号：US10132235
申请日：2002-04-25
申请人： Pin-Chin C. Wang , Fei Wang
发明人： Pin-Chin C. Wang , Fei Wang
IPC分类号： H01L2144
CPC分类号： H01L21/76846 , H01L21/76807 , H01L21/76828 , H01L21/76831 , H01L21/76838 , H01L21/76867 , H01L21/76877 , Y10S977/84
摘要： For fabricating an interconnect structure within a dielectric material comprised of at least one dielectric reactant element, an interconnect opening formed within the dielectric material is filled with a conductive fill material comprised of first and second dopant elements that are different. A diffusion barrier material, that surrounds the conductive fill material, is formed from a reaction of the first dopant element and a dielectric reactant element. Also, a boundary material, that surrounds the conductive fill material, is formed from a reaction of the second dopant element and a dielectric reactant element. The boundary material prevents diffusion of a dielectric reactant element from the dielectric material into the conductive fill material.
摘要翻译：为了在由至少一个介电反应物元件构成的电介质材料内制造互连结构，在电介质材料内形成的互连开口用由不同的第一和第二掺杂元素构成的导电填充材料填充。围绕导电填充材料的扩散阻挡材料由第一掺杂剂元素和介电反应物元件的反应形成。此外，围绕导电填充材料的边界材料由第二掺杂剂元素和介电反应物元件的反应形成。边界材料防止介电反应物元件从电介质材料扩散到导电填充材料中。

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