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1. 发明授权

US09035690B2 Circuit arrangement with a first semiconductor device and with a plurality of second semiconductor devices 有权
标题翻译：具有第一半导体器件和多个第二半导体器件的电路布置
公开(公告)号：US09035690B2
公开(公告)日：2015-05-19
申请号：US13599946
申请日：2012-08-30
申请人： Rolf Weis
发明人： Rolf Weis
IPC分类号： H03K17/567 , H03K17/10 , H03K17/687
CPC分类号： H03K5/08 , H03K17/102 , H03K17/567 , H03K17/687 , H03K2017/6875
摘要： A circuit arrangement includes a first semiconductor device having a load path and a number of second semiconductor devices. Each second semiconductor device has a control terminal and a load path between a first load terminal and a second load terminal. The second semiconductor devices have their load paths connected in series and connected in series with the load path of the first semiconductor device. Each of the second semiconductor devices has a load terminal of one of the first semiconductor device and of one of the second semiconductor devices associated thereto and a voltage limiting element coupled between the control terminal of one of the second semiconductor devices and the load terminal associated with that one of the second semiconductor devices.
摘要翻译：电路装置包括具有负载路径和多个第二半导体器件的第一半导体器件。每个第二半导体器件具有在第一负载端子和第二负载端子之间的控制端子和负载路径。第二半导体器件的负载路径串联连接并与第一半导体器件的负载路径串联连接。每个第二半导体器件具有第一半导体器件中的一个和与其相关联的第二半导体器件中的一个的负载端子，以及耦合在第二半导体器件中的一个的控制端子与与之相关联的负载端子之间的电压限制元件那个第二个半导体器件之一。

2. 发明授权

US08971080B2 Circuit arrangement with a rectifier circuit 有权
标题翻译：电路布置与整流电路
公开(公告)号：US08971080B2
公开(公告)日：2015-03-03
申请号：US13546510
申请日：2012-07-11
申请人： Rolf Weis , Gerald Deboy
发明人： Rolf Weis , Gerald Deboy
IPC分类号： H02M7/217
CPC分类号： H02M3/33592 , H02M3/1588 , H02M7/217 , Y02B70/1466 , Y02B70/1475
摘要： A circuit arrangement includes a rectifier circuit having a first and a second load terminal, a first semiconductor device having a load path and a control terminal and a plurality of n, with n>1, second semiconductor devices, each having a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. The series circuit with the first semiconductor device and the second semiconductor devices are connected between the load terminals of the rectifier circuit. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device.
摘要翻译：一种电路装置包括具有第一和第二负载端子的整流电路，具有负载路径的第一半导体器件和具有n≥1的多个n，第二半导体器件具有负载路径第一负载端子和第二负载端子和控制端子。第二半导体器件的负载路径串联连接并与第一半导体器件的负载路径串联连接。具有第一半导体器件和第二半导体器件的串联电路连接在整流器电路的负载端子之间。每个第二半导体器件的控制端子连接到其它第二半导体器件之一的负载端子。第二半导体器件中的一个具有连接到第一半导体器件的负载端子之一的控制端子。

3. 发明申请

US20140016386A1 Circuit Arrangement with a Rectifier Circuit 有权
标题翻译：整流电路的电路布置
公开(公告)号：US20140016386A1
公开(公告)日：2014-01-16
申请号：US13546510
申请日：2012-07-11
申请人： Rolf Weis , Gerald Deboy
发明人： Rolf Weis , Gerald Deboy
IPC分类号： H02M7/00 , H02M7/217 , H02M7/06
CPC分类号： H02M3/33592 , H02M3/1588 , H02M7/217 , Y02B70/1466 , Y02B70/1475
摘要： A circuit arrangement includes a rectifier circuit having a first and a second load terminal, a first semiconductor device having a load path and a control terminal and a plurality of n, with n>1, second semiconductor devices, each having a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. The series circuit with the first semiconductor device and the second semiconductor devices are connected between the load terminals of the rectifier circuit. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device.
摘要翻译：一种电路装置包括具有第一和第二负载端子的整流电路，具有负载路径的第一半导体器件和具有n≥1的多个n，第二半导体器件具有负载路径第一负载端子和第二负载端子和控制端子。第二半导体器件的负载路径串联连接并与第一半导体器件的负载路径串联连接。具有第一半导体器件和第二半导体器件的串联电路连接在整流器电路的负载端子之间。每个第二半导体器件的控制端子连接到其它第二半导体器件之一的负载端子。第二半导体器件中的一个具有连接到第一半导体器件的负载端子之一的控制端子。

4. 发明授权

US08569842B2 Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices 有权
标题翻译：具有第一半导体器件和多个第二半导体器件的半导体器件布置
公开(公告)号：US08569842B2
公开(公告)日：2013-10-29
申请号：US13275151
申请日：2011-10-17
申请人： Rolf Weis , Franz Hirler , Matthias Stecher , Armin Willmeroth , Gerald Deboy , Martin Feldtkeller
发明人： Rolf Weis , Franz Hirler , Matthias Stecher , Armin Willmeroth , Gerald Deboy , Martin Feldtkeller
IPC分类号： H01L27/06 , H01L27/088 , H01L27/098 , H01L29/161 , H01L29/20 , H01L29/778 , H01L29/788
CPC分类号： H01L27/0207 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L27/0623 , H01L27/0629 , H01L27/0727 , H01L27/088 , H01L27/0883 , H01L27/0886 , H01L27/098 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/4236 , H01L29/4238 , H01L29/78 , H01L29/7817 , H01L29/7824 , H01L29/7825 , H01L29/7835 , H01L29/7838 , H03K17/06
摘要： A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.
摘要翻译：半导体器件布置包括具有负载路径的第一半导体器件和多个第二晶体管，每个具有第一和第二负载端子与控制端子之间的负载路径。第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接。每个第二晶体管的控制端连接到其它第二晶体管的负载端子。第二晶体管中的一个具有其控制端子连接到第一半导体器件的负载端子之一。

5. 发明授权

US07829879B2 Integrated circuit including U-shaped access device 有权
标题翻译：集成电路包括U型接入装置
公开(公告)号：US07829879B2
公开(公告)日：2010-11-09
申请号：US12033519
申请日：2008-02-19
申请人： Rolf Weis , Thomas Happ
发明人： Rolf Weis , Thomas Happ
IPC分类号： H01L29/02
CPC分类号： H01L27/2409 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148
摘要： An integrated circuit includes a first contact, a second contact, and a U-shaped access device coupled to the first contact and the second contact. The integrated circuit includes self-aligned dielectric material isolating the first contact from the second contact.
摘要翻译：集成电路包括耦合到第一触点和第二触点的第一触点，第二触点和U形存取装置。集成电路包括将第一接触与第二接触隔离的自对准电介质材料。

6. 发明授权

US07642586B2 Integrated memory cell array 失效
标题翻译：集成存储单元阵列
公开(公告)号：US07642586B2
公开(公告)日：2010-01-05
申请号：US11517634
申请日：2006-09-08
申请人： Rolf Weis
发明人： Rolf Weis
IPC分类号： H01L27/108
CPC分类号： H01L29/66621 , H01L27/10876 , H01L27/10882 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an integrated memory cell array comprising: a semiconductor substrate; a plurality of cell transistor devices including: a pillar formed in said semiconductor substrate; a gate trench surrounding said pillar; a first source/drain region formed in an upper region of said pillar; a gate dielectric formed on the bottom of said gate trench and surrounding a lower region of said pillar; a gate formed on said gate dielectric in said gate trench and surrounding a lower region of said pillar; and a second source/drain region formed in an upper region of said semiconductor substrate adjoining said gate trench; a plurality of bitlines being connected to respective first groups of first source/drain regions of said cell transistor devices; a plurality of wordlines connecting the respective gates of second groups said cell transistor devices; and a plurality of cell capacitor devices being connected to the second source/drain regions of said cell transistor devices.
摘要翻译：本发明提供一种集成存储单元阵列，包括：半导体衬底; 多个单元晶体管器件，包括：形成在所述半导体衬底中的柱; 围绕所述支柱的栅极沟槽; 形成在所述柱的上部区域中的第一源极/漏极区域; 形成在所述栅极沟槽的底部并围绕所述柱的下部区域的栅极电介质; 形成在所述栅极沟槽中的所述栅极电介质上并围绕所述柱的下部区域的栅极; 以及形成在与所述栅极沟槽相邻的所述半导体衬底的上部区域中的第二源极/漏极区域; 多个位线连接到所述单元晶体管器件的第一源/漏区的相应第一组; 连接第二组的各个栅极的多个字线，所述单元晶体管器件; 并且多个单元电容器器件连接到所述单元晶体管器件的第二源极/漏极区域。

7. 发明授权

US07642572B2 Integrated circuit having a memory cell array and method of forming an integrated circuit 失效
标题翻译：具有存储单元阵列的集成电路和形成集成电路的方法
公开(公告)号：US07642572B2
公开(公告)日：2010-01-05
申请号：US11735164
申请日：2007-04-13
申请人： Martin Popp , Till Schloesser , Ulrike Gruening-von Schwerin , Rolf Weis
发明人： Martin Popp , Till Schloesser , Ulrike Gruening-von Schwerin , Rolf Weis
IPC分类号： H01L27/108
CPC分类号： H01L27/10817 , G11C5/063 , H01L27/10823 , H01L27/10876 , H01L27/10885
摘要： An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75.
摘要翻译：公开了一种具有存储单元阵列的集成电路和形成集成电路的方法。一个实施例提供沿着第一方向行进的位线，沿着基本上垂直于第一方向的第二方向行进的字线，有效区域和位线接触。位线触点被布置成沿着第二方向延伸的列，并且以沿第一方向延伸的列布置。相邻位线之间的距离为DL，相邻位线触点之间的距离为DC，DC平行于第一方向测量。以下关系成立：1 / 2.25 <= DL / DC <= 1 / 1.75。

8. 发明授权

US07635893B2 Transistor, memory cell array and method of manufacturing a transistor 失效
标题翻译：晶体管，存储单元阵列及制造晶体管的方法
公开(公告)号：US07635893B2
公开(公告)日：2009-12-22
申请号：US11128782
申请日：2005-05-13
申请人： Rolf Weis , Till Schloesser , Ulrike Gruening von Schwerin
发明人： Rolf Weis , Till Schloesser , Ulrike Gruening von Schwerin
IPC分类号： H01L29/772
CPC分类号： H01L27/10894 , H01L27/10808 , H01L27/10838 , H01L27/10876 , H01L27/10879 , H01L29/66621 , H01L29/7834 , H01L29/7851
摘要： A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, and a gate electrode disposed along said channel region and being electrically insulated from said channel region, for controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which the channel has the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to a line connecting said first and second source/drain regions, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides.
摘要翻译：公开了晶体管，存储单元阵列和制造晶体管的方法。在一个实施例中，本发明涉及至少部分地形成在半导体衬底中的晶体管，包括第一和第二源极/漏极区域，连接所述第一和第二源极/漏极区域的沟道区域，所述沟道区域是设置在所述半导体衬底中的栅电极以及沿着所述沟道区设置并与所述沟道区电绝缘的栅极，用于控制在所述第一和第二源/漏区之间流动的电流，其中所述沟道区包括所述通道具有脊的形状，所述脊包括垂直于连接所述第一和第二源极/漏极区的线的横截面中的顶侧和两个侧边，其中所述顶侧设置在所述半导体的表面下方基板和所述栅电极沿着所述顶侧和所述两个横向侧面设置。

9. 发明申请

US20090127608A1 INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路及制造集成电路的方法
公开(公告)号：US20090127608A1
公开(公告)日：2009-05-21
申请号：US11943482
申请日：2007-11-20
申请人： Rolf Weis
发明人： Rolf Weis
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/0207 , G11C5/063 , G11C11/4097 , H01L27/10817 , H01L27/10855 , H01L27/10882 , H01L27/10888
摘要： An integrated circuit including a memory cell array is shown. The memory cell array comprises word lines extending in a first direction and bit lines extending in a second direction intersecting the first direction and memory cells. The memory cells may include storage elements, bit line contacts for coupling a corresponding memory cell to a corresponding bit line. The bit line contacts are arranged in a checkerboard pattern with respect to the first direction, and the storage elements are arranged in a regular grid along the first and second directions, respectively.
摘要翻译：示出了包括存储单元阵列的集成电路。存储单元阵列包括沿第一方向延伸的字线和沿与第一方向相交的第二方向延伸的位线和存储单元。存储器单元可以包括存储元件，用于将相应的存储器单元耦合到对应的位线的位线触点。位线触点相对于第一方向布置成棋盘图案，并且存储元件分别沿着第一和第二方向排列成规则的格栅。

10. 发明申请

US20080044980A1 Method of forming a semiconductor device 失效
标题翻译：形成半导体器件的方法
公开(公告)号：US20080044980A1
公开(公告)日：2008-02-21
申请号：US11507647
申请日：2006-08-21
申请人： Kimberly Wilson , Hans-Peter Moll , Rolf Weis , Phillip Stopford , Frank Ludwig
发明人： Kimberly Wilson , Hans-Peter Moll , Rolf Weis , Phillip Stopford , Frank Ludwig
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , Y10S438/942 , Y10S438/952
摘要： A method of forming a semiconductor device includes depositing a fill material (4) on a substrate portion (2) and on a dielectric layer (3) being disposed on the substrate (1) and having an opening (10) located above the substrate portion (2), removing the fill material (4) disposed above the dielectric layer (3), thereby leaving an exposed top surface (6) of the dielectric layer (3) and residual fill material (15) within the opening (10), forming a hard mask material (5) on the exposed top surface (6) of the dielectric layer (3) and on the residual fill material (15), patterning the hard mask material (5) for forming a hard mask (25) having trenches (8a, 8b) extending along a lateral direction (X) and exposing portions of the residual fill material (15) adjacent to the dielectric layer (3) and portions of the dielectric layer (3) adjacent to the residual fill material (15), anisotropically etching the dielectric layer (3), the residual fill material (15) and the substrate (1) selectively to the hard mask (5), thereby forming at least a first and a second isolation trench (11a, 11b) extending along the lateral direction (X).
摘要翻译：一种形成半导体器件的方法包括在衬底部分（2）上沉积填充材料（4）和设置在衬底（1）上并具有位于衬底部分上方的开口（10）的介电层（3）（2），去除设置在电介质层（3）上方的填充材料（4），从而在开口（10）内留下介电层（3）的暴露的顶表面（6）和残余填充材料（15）在所述介电层（3）的暴露的顶表面（6）和所述残留填充材料（15）上形成硬掩模材料（5），对所述硬掩模材料（5）进行图案化以形成硬掩模（25），所述硬掩模材料（25）沿着横向方向（X）延伸的沟槽（8a，8b）和暴露邻近电介质层（3）的残余填充材料（15）的部分和与残余填充材料相邻的介电层（3）的部分（15），各向异性地蚀刻介电层（3），残留填充材料（15）和基板（1）选择性地连接到硬掩模（5），从而形成沿着横向（X）延伸的至少第一和第二隔离沟槽（11a，11b）。

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