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71. 发明申请

US20100232235A1 Memory Device Having Buried Boosting Plate and Methods of Operating the Same 有权
标题翻译：具有埋入板的存储器件及其操作方法
公开(公告)号：US20100232235A1
公开(公告)日：2010-09-16
申请号：US12402300
申请日：2009-03-11
申请人： Akira Goda
发明人： Akira Goda
IPC分类号： G11C16/06 , H01L29/788
CPC分类号： G11C16/10 , H01L21/84 , H01L27/11526 , H01L27/11529 , H01L27/1203
摘要： Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the SOI substrate such that the boosting plate exerts a capacitive coupling effect on a p-well of the memory array. Such a boosting plate may be used to boost the p-well during program and erase operations of the memory array. During a read operation, the boosting plate may be grounded to minimize interaction with p-well. Systems including the memory array and methods of operating the memory array are also disclosed.
摘要翻译：公开了存储器件，例如包括具有升压板的绝缘体上半导体（SOI）NAND存储器阵列的存储器件。升压板可以设置在SOI衬底的绝缘体层中，使得升压板对存储器阵列的p阱施加电容耦合效应。这种升压板可用于在存储器阵列的编程和擦除操作期间升压p阱。在读取操作期间，升压板可以接地以最小化与p阱的相互作用。还公开了包括存储器阵列的系统和操作存储器阵列的方法。

72. 发明授权

US07675772B2 Multilevel memory cell operation 有权
标题翻译：多层存储单元操作
公开(公告)号：US07675772B2
公开(公告)日：2010-03-09
申请号：US11924793
申请日：2007-10-26
申请人： Akira Goda , Seiichi Aritome
发明人： Akira Goda , Seiichi Aritome
IPC分类号： G11C11/34
CPC分类号： G11C16/349 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C2211/5634
摘要： One or more embodiments of the present disclosure provide methods, devices, and systems for operating non-volatile multilevel memory cells. One method embodiment includes programming a memory cell to one of a number of different threshold voltage (Vt) levels, each level corresponding to a program state. The method includes programming a reference cell to a Vt level at least as great as an uppermost Vt level of the number of different Vt levels, performing a read operation on the reference cell, and determining a number of read reference voltages used to determine a particular program state of the memory cell based on the read operation performed on the reference cell.
摘要翻译：本公开的一个或多个实施例提供了用于操作非易失性多电平存储器单元的方法，装置和系统。一个方法实施例包括将存储器单元编程为多个不同阈值电压（Vt）电平之一，每个电平对应于编程状态。该方法包括将参考单元编程至至少与不同Vt电平数量的最高Vt电平一样大的Vt电平，对参考单元执行读取操作，以及确定用于确定特定值的读取参考电压的数量基于对参考单元执行的读取操作，存储器单元的编程状态。

73. 发明申请

US20100039862A1 READ OPERATION FOR NAND MEMORY 有权
标题翻译： NAND存储器的读操作
公开(公告)号：US20100039862A1
公开(公告)日：2010-02-18
申请号：US12582289
申请日：2009-10-20
申请人： Seiichi Aritome , Akira Goda
发明人： Seiichi Aritome , Akira Goda
IPC分类号： G11C16/04 , G11C16/06 , G11C7/06
CPC分类号： G11C16/26 , G11C16/0483
摘要： Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to a source line selectively coupled to a bit line through a string of series-coupled non-volatile memory cells containing a memory cell targeted for reading, and where a second, different, potential is supplied to other source lines selectively coupled to the bit line through other strings of series-coupled non-volatile memory cells not containing the target memory cell. Supplying a different potential to the other source lines facilitates mitigation of current leakage between the other source lines and the bit line while sensing a data value of the target memory cell.
摘要翻译：利用NAND架构的非易失性存储器件适于执行读取操作，其中第一电位被提供给选择性地耦合到位线的源极线，该源极线通过串联耦合的非易失性存储器单元串，其包含用于读取的存储单元并且其中第二不同的电位被提供给通过其它不包含目标存储器单元的串联耦合的非易失性存储器单元串选择性地耦合到位线的其它源极线。向其它源极线提供不同的电位有助于在感测目标存储器单元的数据值的同时减轻其它源极线和位线之间的电流泄漏。

74. 发明申请

US20090103371A1 MEMORY CELL OPERATION 有权
标题翻译：记忆体操作
公开(公告)号：US20090103371A1
公开(公告)日：2009-04-23
申请号：US11876406
申请日：2007-10-22
申请人： Akira Goda , Seiichi Aritome
发明人： Akira Goda , Seiichi Aritome
IPC分类号： G11C16/10 , G11C16/14
CPC分类号： G11C16/3468
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the group of memory cells at least partially based on the determined quantity of erase pulses.
摘要翻译：本公开的实施例提供用于编程存储器单元的方法，设备，模块和系统。一种方法包括确定用于将阵列的一组存储器单元放置在擦除状态中的擦除脉冲的量，以及至少部分地基于确定的擦除量来调整与编程存储器单元组相关联的至少一个操作参数脉冲。

75. 发明授权

US07499330B2 Programming method for NAND EEPROM 有权
标题翻译： NAND EEPROM的编程方法
公开(公告)号：US07499330B2
公开(公告)日：2009-03-03
申请号：US11900443
申请日：2007-09-12
申请人： Akira Goda , Seiichi Aritome , Todd Marquart
发明人： Akira Goda , Seiichi Aritome , Todd Marquart
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/3427
摘要： A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines of the memory cell string or array during an programming cycle. In one embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized depending on the placement of the memory cell in the NAND memory cell string. In another embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized to compensate for faster and slower programming word lines/memory cells.
摘要翻译：描述了NAND架构非易失性存储器件和编程过程，其通过将不同字线通过电压（Vpass）应用到存储器单元串或阵列的未选择字线来对非易失性存储器单元串的各个单元进行编程在编程周期。在本发明的一个实施例中，根据存储器单元在NAND存储器单元串中的位置，利用不同的字线通过电压（Vpass）。在本发明的另一个实施例中，利用不同的字线通过电压（Vpass）来补偿更快和更慢的编程字线/存储器单元。

76. 发明授权

US07364951B2 Nonvolatile semiconductor memory device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07364951B2
公开(公告)日：2008-04-29
申请号：US11302203
申请日：2005-12-14
申请人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
发明人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
IPC分类号： H01L21/82 , H01L21/8234 , H01L21/8236 , H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529 , H01L27/11543 , Y10S257/909
摘要： A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.
摘要翻译：一种非易失性半导体存储器件的制造方法，具有在存储单元部分的外围电路部分和第二栅电极上形成第一栅电极的步骤，将杂质引入外围电路部分和存储单元部分的步骤，在至少所述存储单元部分之上形成第一绝缘膜的步骤，以及对其中引入了所述杂质的所述半导体衬底进行退火的步骤。第一栅电极具有第一栅极长度。第二栅电极具有比第一栅极长度短的第二栅极长度。

77. 发明授权

US07292476B2 Programming method for NAND EEPROM 有权
标题翻译： NAND EEPROM的编程方法
公开(公告)号：US07292476B2
公开(公告)日：2007-11-06
申请号：US11215933
申请日：2005-08-31
申请人： Akira Goda , Seiichi Aritome , Todd Marquart
发明人： Akira Goda , Seiichi Aritome , Todd Marquart
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/3427
摘要： A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines of the memory cell string or array during an programming cycle. In one embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized depending on the placement of the memory cell in the NAND memory cell string. In another embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized to compensate for faster and slower programming word lines/memory cells.
摘要翻译：描述了NAND架构非易失性存储器件和编程过程，其通过将不同字线通过电压（Vpass）应用到存储器单元串或阵列的未选择字线来对非易失性存储器单元串的各个单元进行编程在编程周期。在本发明的一个实施例中，根据存储器单元在NAND存储器单元串中的位置，利用不同的字线通过电压（Vpass）。在本发明的另一个实施例中，利用不同的字线通过电压（Vpass）来补偿更快和更慢的编程字线/存储器单元。

78. 发明申请

US20070215958A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070215958A1
公开(公告)日：2007-09-20
申请号：US11798593
申请日：2007-05-15
申请人： Masayuki Tanaka , Yoshio Ozawa , Shigehiko Saida , Akira Goda , Mitsuhiro Noguchi , Yuichiro Mitani , Yoshitaka Tsunashima
发明人： Masayuki Tanaka , Yoshio Ozawa , Shigehiko Saida , Akira Goda , Mitsuhiro Noguchi , Yuichiro Mitani , Yoshitaka Tsunashima
IPC分类号： H01L29/94
CPC分类号： H01L21/022 , H01L21/0217 , H01L21/28176 , H01L21/28202 , H01L21/28247 , H01L21/28518 , H01L21/3185 , H01L21/76838 , H01L21/76897 , H01L29/40117 , H01L29/513 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/792
摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.
摘要翻译：公开了一种半导体器件，包括半导体衬底，栅电极，形成在半导体衬底和栅电极之间的第一绝缘膜，以及沿着栅电极的顶表面或侧表面形成的第二绝缘膜，包含氮，硅和氢的氮化硅膜和形成在下部氮化硅膜上并含有氮，硅和氢的上部氮化硅膜，并且其中氮（N）与硅（Si）的组成比N / Si在下氮化硅膜比上述氮化硅膜高。

79. 发明授权

US07184356B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07184356B2
公开(公告)日：2007-02-27
申请号：US11074801
申请日：2005-03-09
申请人： Mitsuhiro Noguchi , Akira Goda , Hiroyuki Nitta
发明人： Mitsuhiro Noguchi , Akira Goda , Hiroyuki Nitta
IPC分类号： G11C8/00
CPC分类号： G06F11/1008 , G06F11/108 , G11C7/22 , G11C16/04 , G11C16/0483 , G11C16/26 , G11C16/32 , G11C16/3454 , G11C29/50004 , G11C29/52 , G11C29/76 , G11C29/82 , G11C29/84 , G11C2029/0409 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device includes: a memory cell array having a plurality of data select lines disposed in parallel with each other, a plurality of data transfer line disposed in parallel with each other to intersect the data select lines, and electrically rewritable memory cells laid out at cross portions between the data select lines and data transfer lines; a data select line driver for driving the data select lines of the memory cell array; a sense amplifier circuit connected to the data transfer lines of the memory cell array, for performing data read of memory cells selected by one of the data select lines; and a control circuit used for timing control of data read of the memory cell array, for outputting at least two types of timing signals as being different in accordance with a selected data area of the memory cell array.
摘要翻译：半导体存储器件包括：存储单元阵列，具有彼此平行布置的多个数据选择线;多个数据传输线，彼此并联设置，以与数据选择线相交;以及布置的电可重写存储器单元在数据选择线和数据传输线之间的交叉部分; 用于驱动存储单元阵列的数据选择线的数据选择线驱动器; 连接到存储单元阵列的数据传输线的读出放大器电路，用于对数据选择线之一选择的存储器单元执行数据读取; 以及用于对存储单元阵列的数据读取进行定时控制的控制电路，用于根据存储单元阵列的所选择的数据区输出不同的至少两种类型的定时信号。

80. 发明授权

US07095085B2 Nonvolatile semiconductor memory device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07095085B2
公开(公告)日：2006-08-22
申请号：US10798481
申请日：2004-03-12
申请人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
发明人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529 , H01L27/11543 , Y10S257/909
摘要： A nonvolatile semiconductor memory device includes erasable and programmable memory cell transistors, a selection transistor, a peripheral transistor, first post-oxidation films each provided on a gate electrode of all of the plurality of erasable and programmable memory cell transistors, a second post-oxidation film provided on a gate electrode of the selection transistor, a third post-oxidation film provided on a gate electrode of the peripheral transistor, and an insulating film covering the memory cell transistors, the selection transistor, and the peripheral transistor. The insulating film is harder for an oxidizing agent to pass through than a silicon oxide film. The insulating film has an oxidized region. The insulating film includes a silicon nitride film. The oxidized region is provided in a surface of the silicon nitride film.
摘要翻译：非易失性半导体存储器件包括可擦除和可编程存储单元晶体管，选择晶体管，外围晶体管，每个设置在所有多个可擦除和可编程存储单元晶体管的栅电极上的第一后氧化膜，第二后氧化提供在选择晶体管的栅电极上的第三后氧化膜，以及设置在外围晶体管的栅电极上的第三后氧化膜以及覆盖存储单元晶体管，选择晶体管和外围晶体管的绝缘膜。绝缘膜比氧化硅膜更难通过氧化剂通过。绝缘膜具有氧化区域。绝缘膜包括氮化硅膜。氧化区域设置在氮化硅膜的表面。

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