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1. 发明公开

US20240257887A1 ACCELERATING CONFIGURATION UPDATES FOR MEMORY DEVICES 审中-公开
公开(公告)号：US20240257887A1
公开(公告)日：2024-08-01
申请号：US18630983
申请日：2024-04-09
申请人： Micron Technology, Inc.
发明人： Tawalin Opastrakoon , Renato C. Padilla , Vamsi Pavan Rayaprolu , Sampath K. Ratnam , Michael G. Miller , Gary F. Besinga , Christopher M. Smitchger
IPC分类号： G11C16/34 , G11C16/10 , G11C16/26
CPC分类号： G11C16/3468 , G11C16/10 , G11C16/26 , G11C16/3459
摘要： A configuration setting manager of a memory device receives a request to perform an adjustment operation on one or more configuration setting values of the memory device; calculate one or more updated configuration setting values by applying a multiplier value to the one or more configuration setting values based on a configuration adjustment definition associated with the one or more configuration setting values, wherein the multiplier value is associated with a number of memory operations performed on the memory device; and store the one or more updated configuration setting values to one or more corresponding configuration registers.

2. 发明授权

US11984174B2 Accelerating configuration updates for memory devices 有权
公开(公告)号：US11984174B2
公开(公告)日：2024-05-14
申请号：US17249448
申请日：2021-03-02
申请人： Micron Technology, Inc.
发明人： Tawalin Opastrakoon , Renato C. Padilla , Vamsi Pavan Rayaprolu , Sampath K. Ratnam , Michael G. Miller , Gary F. Besinga , Christopher M. Smitchger
IPC分类号： G11C16/06 , G11C16/10 , G11C16/26 , G11C16/34
CPC分类号： G11C16/3468 , G11C16/10 , G11C16/26 , G11C16/3459
摘要： A configuration setting manager of a memory device receives a request to perform an adjustment operation on a set of configuration setting values for the memory device, where each configuration setting value of the set of configuration setting values is stored in a corresponding configuration register of a set of configuration registers; determines a configuration adjustment definition associated with one or more configuration setting values of the set of configuration setting values; calculates an updated set of configuration setting values by applying a multiplier value to the configuration adjustment definition, wherein the multiplier value is associated with a number of programming operations performed on the memory device; and stores the updated set of configuration setting values in the corresponding configuration registers.

3. 发明公开

US20230148408A1 MEMORY DEVICE FOR DETECTING FAIL CELL AND OPERATION METHOD THEREOF 审中-公开
公开(公告)号：US20230148408A1
公开(公告)日：2023-05-11
申请号：US17982550
申请日：2022-11-08
申请人： Samsung Electronics Co., Ltd.
发明人： Jooyong Park , Wontaeck Jung , Nayeon Kim , Jiwon Seo , Seungyong Hyun
IPC分类号： G11C16/34 , G11C16/08
CPC分类号： G11C16/3459 , G11C16/3468 , G11C16/08
摘要： An operation method of a memory device for programming memory cells to a plurality of program states includes providing a series of program pulses to selected memory cells, performing a first verification operation of verifying a target program state among the plurality of program states, performing, when the first verification operation is passed, a second verification operation of detecting fail cells among the selected memory cells to determine if these memory cells have been overprogrammed. When the number of detected fail cells is greater than or equal to a reference value, the program operation may be terminated for that location and the data may be written to another location.

4. 发明授权

US10074432B2 Programming of memory devices 有权
公开(公告)号：US10074432B2
公开(公告)日：2018-09-11
申请号：US14856105
申请日：2015-09-16
申请人： MICRON TECHNOLOGY, INC.
发明人： Silvia Beltrami , Angelo Visconti
IPC分类号： G11C16/10 , G11C16/12 , G11C16/34
CPC分类号： G11C16/10 , G11C16/12 , G11C16/3459 , G11C16/3463 , G11C16/3468 , G11C16/3486 , G11C16/3495
摘要： Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage, determining a programming voltage indicative of a programming efficiency of the page of the memory block during programming of the page of the memory block, storing a representation of the programming voltage indicative of the programming efficiency of the page of the memory block, setting a starting programming voltage for a different page of the memory block in response to the stored representation of the programming voltage indicative of the programming efficiency of the page of the memory block, and programming the different page of the memory block using its starting programming voltage.

5. 发明申请

US20170062054A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20170062054A1
公开(公告)日：2017-03-02
申请号：US15061967
申请日：2016-03-04
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takashi MAEDA
IPC分类号： G11C16/10 , G11C16/34 , G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/32 , G11C16/3459 , G11C16/3468
摘要： A semiconductor memory device includes a memory string on a well, the memory string including a memory cell connected in series between first and second select transistors, a bit line and a source line respectively connected to the first and second select transistors, a well line connected to the well, first and second select lines respectively connected to gates of the first and second select transistors, a word line connected to a gate of the memory cell transistor, and a control circuit that performs a write operation on the first select transistor, the write operation including a pre-charge operation of the bit line, in which a first voltage is applied to the word line and the second select line, a second voltage higher than the first voltage to the source line and the well line, and a third voltage higher than the first voltage to the first select line.
摘要翻译：半导体存储器件包括阱上的存储器串，存储串包括串联连接在第一和第二选择晶体管之间的存储单元，分别连接到第一和第二选择晶体管的位线和源极线，分别连接到第一和第二选择晶体管的栅极的阱，第一和第二选择线，连接到存储单元晶体管的栅极的字线和对第一选择晶体管执行写入操作的控制电路，写入操作，其包括将第一电压施加到字线和第二选择线的位线的预充电操作，高于源极线和阱线的第一电压的第二电压，以及第三电压电压高于第一选择线的第一电压。

6. 发明授权

US09349481B2 Semiconductor memory device and method of operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US09349481B2
公开(公告)日：2016-05-24
申请号：US14199412
申请日：2014-03-06
申请人： SK hynix Inc.
发明人： Seiichi Aritome , Soo Jin Wi , Angelo Visconti , Mattia Robustelli
IPC分类号： G11C16/06 , G11C16/34
CPC分类号： G11C16/3459 , G11C16/06 , G11C16/3454 , G11C16/3468
摘要： A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage, and performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells.
摘要翻译：一种操作半导体存储器件的方法包括执行第一程序操作以提高存储单元的阈值电压，执行用于检测快速程序存储单元的程序验证操作，每个程序存储单元的阈值电压升高高于第一次验证电压通过使用目标验证电压和顺序地低于目标验证电压的第一子验证电压和第二子验证电压，从第二子验证电压或更低的次级验证电压进行第二子验证电压，并且在低于目标验证电压的存储单元的每个阈值电压的增量大于每个快速程序存储单元的阈值电压的增量。

7. 发明授权

US09331265B2 Non-volatile memory with linear hot-electron injection technique and strain gauge using the same 有权
标题翻译：使用线性热电子注入技术的非易失性存储器和使用其的应变仪
公开(公告)号：US09331265B2
公开(公告)日：2016-05-03
申请号：US14380122
申请日：2013-01-28
申请人： Board of Trustees of Michigan State University
发明人： Shantanu Chakrabartty
IPC分类号： G01L1/16 , H01L41/113 , G11C16/34 , G11C27/00 , G01B7/16 , A61B5/00 , H01L27/20 , H01L29/788
CPC分类号： H01L41/1132 , A61B5/4509 , A61B5/4519 , A61B5/4533 , A61B5/6847 , G01B7/18 , G11C16/3468 , G11C16/3481 , G11C16/3486 , G11C27/005 , H01L27/20 , H01L29/7884
摘要： A linear hot-electron injection technique is provided for a non-volatile memory arrangement. The non-volatile memory is comprised of: a floating gate transistor; a capacitor with a first terminal electrically coupled to the gate node of the floating gate transistor; a current reference circuit electrically coupled to the source node of the floating gate transistor; and a feedback circuit electrically coupled between the source node of the floating gate transistor and a second terminal of the capacitor. The feedback circuit operates to adjust a voltage at the gate node of the floating gate transistor in accordance with a source-to-drain voltage across the floating gate transistor.
摘要翻译：为非易失性存储装置提供线性热电子注入技术。非易失性存储器包括：浮栅晶体管; 电容器，其具有电耦合到所述浮动栅极晶体管的栅极节点的第一端子; 电流参考电路，电耦合到所述浮栅晶体管的源节点; 以及电耦合在所述浮栅晶体管的源节点和所述电容器的第二端之间的反馈电路。反馈电路根据浮置栅极晶体管两端的源极 - 漏极电压进行调节浮栅晶体管栅极节点的电压。

8. 发明申请

US20140376316A1 PROGRAMMABLE MEMORY CELL AND DATA READ METHOD THEREOF 审中-公开
标题翻译：可编程存储器单元及其数据读取方法
公开(公告)号：US20140376316A1
公开(公告)日：2014-12-25
申请号：US13924615
申请日：2013-06-23
申请人： UNITED MICROELECTRONICS CORPORATION
发明人： Shi-Wen CHEN , Hsin-Pang Lu
IPC分类号： G11C7/14
CPC分类号： G11C7/14 , G11C16/28 , G11C16/3436 , G11C16/3468 , G11C16/349
摘要： A programmable memory cell includes a non-volatile memory unit, a reference current generator and a readout unit. The non-volatile memory unit is configured to be performed by a program operation, a read operation or an erase operation. The reference current generator is configured to generate a reference current; wherein a value of the reference current is dynamically modulated according to a count number of the program and erase operations performed on the non-volatile memory unit. The readout unit, electrically coupled to the non-volatile memory unit and the reference current generator, is configured to read a data stored in the non-volatile memory cell according to the reference current. A data read method applied to the aforementioned programmable memory cell is also provided.
摘要翻译：可编程存储单元包括非易失性存储单元，参考电流发生器和读出单元。非易失性存储器单元被配置为通过编程操作，读取操作或擦除操作来执行。参考电流发生器被配置为产生参考电流; 其中，所述参考电流的值根据对所述非易失性存储器单元执行的所述程序的计数和擦除操作进行动态调制。电耦合到非易失性存储器单元和参考电流发生器的读出单元被配置为根据参考电流读取存储在非易失性存储单元中的数据。还提供了应用于上述可编程存储单元的数据读取方法。

9. 发明授权

US08832506B2 Bit error rate based wear leveling for solid state drive memory 有权
标题翻译：固态硬盘存储器的基于误码率的磨损均衡
公开(公告)号：US08832506B2
公开(公告)日：2014-09-09
申请号：US13355050
申请日：2012-01-20
申请人： Thomas J. Griffin , Dustin J. Vanstee
发明人： Thomas J. Griffin , Dustin J. Vanstee
IPC分类号： G06F11/00 , G11C29/00 , G01R31/28 , H03M13/00 , G11C16/34 , H04L1/20 , G06F11/16 , G01R31/317 , G11C11/406 , G11C16/16 , G11C29/50 , G11C29/42 , G11C16/14 , G11C16/10 , G06F11/10
CPC分类号： G01R31/3171 , G06F11/008 , G06F11/076 , G06F11/1048 , G06F11/1068 , G06F11/16 , G11C11/406 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3468 , G11C16/3495 , G11C29/42 , G11C29/50 , H04L1/203
摘要： According to exemplary embodiments, a system, method, and computer program product are provided for BER-based wear leveling in a SSD. A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.
摘要翻译：根据示例性实施例，提供了一种用于SSD中的基于BER的磨损均衡的系统，方法和计算机程序产品。确定SSD中的块的块级BER值。块的调整PE周期计数根据块级BER值递增或递减。然后，根据调整后的PE循环次数，在SSD中进行磨损均衡。

10. 发明授权

US08811091B2 Non-volatile memory and method with improved first pass programming 有权
标题翻译：非易失性存储器和具有改进的第一遍编程的方法
公开(公告)号：US08811091B2
公开(公告)日：2014-08-19
申请号：US13329103
申请日：2011-12-16
申请人： Yan Li , Cynthia Hsu , Ken Oowada
发明人： Yan Li , Cynthia Hsu , Ken Oowada
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3468
摘要： A nonvolatile memory with a multi-pass programming scheme enables a page of multi-level memory cells to be programmed with reduced floating-gate to floating-gate perturbations (Yuping effect). The memory cells operate within a common threshold voltage range or window, which is partitioned into multiple bands to denote a series of increasingly programmed states. The series is divided into two halves, a lower set and a higher set. The memory cells are programmed in a first, coarse programming pass such that the memory cells of the page with target states from the higher set are programmed to a staging area near midway in the threshold window. In particular, they are programmed closer to their targeted destinations than previous schemes, without incurring much performance penalty. Subsequent passes will then complete the programming more quickly. Yuping effect is reduced since the threshold voltage change in subsequent passes are reduced.
摘要翻译：具有多遍编程方案的非易失性存储器使得能够以降低的浮栅到浮栅扰动（Yuping效应）来编程一页多层存储单元。存储器单元在公共阈值电压范围或窗口内工作，其被划分为多个频带以表示一系列日益编程的状态。该系列分为两部分，一组较低，一组较高。存储器单元被编程在第一粗略编程遍历中，使得具有来自较高集合的目标状态的页面的存储器单元被编程到阈值窗口中途附近的分段区域。特别地，它们被编程为比先前的方案更接近目标目的地，而不会导致太多的性能损失。随后的通行证将更快地完成编程。 Yuping效应降低，因为后续通过中的阈值电压变化减小。

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