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71. 发明授权

US10102607B2 Method for chaining media processing 有权
公开(公告)号：US10102607B2
公开(公告)日：2018-10-16
申请号：US15692469
申请日：2017-08-31
申请人： Apple Inc.
发明人： Timothy J. Millet , Manu Gulati , Arthur L. Spence , Gurjeet S. Saund , Robert P. Esser
IPC分类号： G06T1/20 , G06F9/52 , G06F9/48 , G06T1/60 , G09G5/36 , G09G5/00
摘要： One embodiment may include media circuits, an application processor, a direct memory access circuit (DMA), and a media managing circuit. The application processor may issue media commands into a queue. The media managing circuit may retrieve a first media command, set the DMA to copy data associated with the first media command to the first media circuit, and send the first media command to the first media circuit. While the first media command is being executed, the media managing circuit may also retrieve a second media command, determine that the second media command utilizes data that is dependent on a completion of the first media command, and set the DMA to copy data from the first media circuit to the second media circuit. After the first media command has been completed, the media managing circuit may also send the second media command to the second media circuit.

72. 发明申请

US20180063016A1 COMMUNICATION QUEUE MANAGEMENT SYSTEM 审中-公开
公开(公告)号：US20180063016A1
公开(公告)日：2018-03-01
申请号：US15246046
申请日：2016-08-24
申请人： Apple Inc.
发明人： Manu Gulati , Christopher D. Shuler , Benjamin K. Dodge , Thejasvi M. Vijayaraj , Harshavardhan Kaushikkar , Yang Yang , Rong Z. Hu , Srinivasa R. Sridharan , Wolfgang H. Klingauf , Neeraj Parik
IPC分类号： H04L12/863
CPC分类号： H04L47/6295 , G06F9/546 , G06F13/1642 , H04L47/6275
摘要： In some embodiments, a system includes a memory system, plurality of computing devices, and plurality of queues. The plurality of computing devices perform actions dependent on data stored at the memory device, where traffic between the plurality of computing devices and the memory device has at least a first priority level and a second priority level. The first priority level is higher than the second priority level. The plurality of queues pass data between the memory device and the plurality of computing devices. A particular queue allocates a first portion of the particular queue to traffic having the first priority level and allocates a second portion of the particular queue to traffic having the first priority level and to traffic having the second priority level.

73. 发明申请

US20170365034A1 METHOD FOR CHAINING MEDIA PROCESSING 审中-公开
公开(公告)号：US20170365034A1
公开(公告)日：2017-12-21
申请号：US15692469
申请日：2017-08-31
申请人： Apple Inc.
发明人： Timothy J. Millet , Manu Gulati , Arthur L. Spence , Gurjeet S. Saund , Robert P. Esser
IPC分类号： G06T1/20 , G06F9/52 , G06F9/48 , G06T1/60 , G09G5/00 , G09G5/36
CPC分类号： G06T1/20 , G06F9/4893 , G06F9/52 , G06T1/60 , G09G5/001 , G09G5/363 , G09G2360/08 , Y02D10/24
摘要： One embodiment may include media circuits, an application processor, a direct memory access circuit (DMA), and a media managing circuit. The application processor may issue media commands into a queue. The media managing circuit may retrieve a first media command, set the DMA to copy data associated with the first media command to the first media circuit, and send the first media command to the first media circuit. While the first media command is being executed, the media managing circuit may also retrieve a second media command, determine that the second media command utilizes data that is dependent on a completion of the first media command, and set the DMA to copy data from the first media circuit to the second media circuit. After the first media command has been completed, the media managing circuit may also send the second media command to the second media circuit.

74. 发明授权

US09653079B2 Clock switching in always-on component 有权
公开(公告)号：US09653079B2
公开(公告)日：2017-05-16
申请号：US14621093
申请日：2015-02-12
申请人： Apple Inc.
发明人： Manu Gulati , Gilbert H. Herbeck , Alexei E. Kosut , Girault W. Jones , Timothy J. Millet
IPC分类号： G10L15/28 , G10L19/00 , G10L15/22 , G10L15/08
CPC分类号： G10L15/28 , G10L15/08 , G10L15/22 , G10L2015/088 , G10L2015/223
摘要： In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

75. 发明授权

US09632137B2 Serial wire debug bridge 有权
公开(公告)号：US09632137B2
公开(公告)日：2017-04-25
申请号：US14693116
申请日：2015-04-22
申请人： Apple Inc.
发明人： James D. Ramsay , Manu Gulati , Mitchell Palmer Lichtenberg, Jr.
IPC分类号： G06F11/00 , G01R31/317 , G06F11/22
CPC分类号： G01R31/31705 , G06F11/2221
摘要： An integrated circuit (IC) having a bridge for interfacing a debugger and method of operating the same is provided. In one embodiment, an IC includes a debug control circuit and a debug interface block (DIB) implemented thereon. The DIB is coupled to the debug control circuit. The IC also includes an interface for a debugger and a number of interfaces for external circuits, each of the interfaces being coupled to the debug control circuit. The debug control circuit may function as a bridge for coupling an external debugger to the DIB and to external circuits coupled to the IC through corresponding ones of the interfaces. The debug control circuit may establish a connection between the debugger and one of the external circuits. Communications between the debugger and the external circuit may be conducted while bypassing the DIB.

76. 发明授权

US09619377B2 System on a chip with always-on processor which reconfigures SOC and supports memory-only communication mode 有权
公开(公告)号：US09619377B2
公开(公告)日：2017-04-11
申请号：US14458949
申请日：2014-08-13
申请人： Apple Inc.
发明人： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
IPC分类号： G06F12/02 , G06F12/06 , G06F1/32
CPC分类号： G06F12/0223 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F3/0625 , G06F3/0632 , G06F3/0634 , G06F3/0673 , G06F9/4406 , G06F12/0646 , G06F13/1668 , G06F13/4068 , G06F13/4265 , G06F2212/1032 , G11C11/40615 , Y02D10/122 , Y02D10/151 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

77. 发明授权

US09549373B2 Method for waking a data transceiver through data reception 有权
标题翻译：通过数据接收唤醒数据收发器的方法
公开(公告)号：US09549373B2
公开(公告)日：2017-01-17
申请号：US14444198
申请日：2014-07-28
申请人： Apple Inc.
发明人： Manu Gulati , Gilbert H. Herbeck
IPC分类号： H04M1/00 , H04W52/02
CPC分类号： H04W52/0235 , H04W52/0212 , Y02D70/00 , Y02D70/142 , Y02D70/26
摘要： A method for managing power in a system, in which the system may include a first device configured to transmit serial data and a second device, coupled to the first device. The second device may include a transceiver and interrupt logic, and may be configured to activate the interrupt logic and enable a reduced power mode for the transceiver. Power consumption of the transceiver operating in the reduced power mode may be less than power consumption of the transceiver in an operating mode. The second device may also be configured to assert an interrupt signal responsive to a change in a voltage level of an input of the second device and then de-activate the reduced power mode for the transceiver responsive to the assertion of the interrupt signal.
摘要翻译：一种用于管理系统中的电力的方法，其中所述系统可以包括被配置为传送串行数据的第一设备和耦合到所述第一设备的第二设备。第二设备可以包括收发器和中断逻辑，并且可以被配置为激活中断逻辑并使能收发器的降低的功率模式。以降低功率模式工作的收发器的功耗可能小于工作模式下收发器的功耗。第二设备还可以被配置为响应于第二设备的输入的电压电平的变化来断言中断信号，然后响应于断言中断信号的断言而使得收发器的降低功率模式被去激活。

78. 发明申请

US20160313396A1 Serial Wire Debug Bridge 有权
标题翻译：串行线路调试桥
公开(公告)号：US20160313396A1
公开(公告)日：2016-10-27
申请号：US14693116
申请日：2015-04-22
申请人： Apple Inc.
发明人： James D. Ramsay , Manu Gulati , Mitchell Palmer Lichtenberg, JR.
IPC分类号： G01R31/3177
CPC分类号： G01R31/31705 , G06F11/2221
摘要： An integrated circuit (IC) having a bridge for interfacing a debugger and method of operating the same is provided. In one embodiment, an IC includes a debug control circuit and a debug interface block (DIB) implemented thereon. The DIB is coupled to the debug control circuit. The IC also includes an interface for a debugger and a number of interfaces for external circuits, each of the interfaces being coupled to the debug control circuit. The debug control circuit may function as a bridge for coupling an external debugger to the DIB and to external circuits coupled to the IC through corresponding ones of the interfaces. The debug control circuit may establish a connection between the debugger and one of the external circuits. Communications between the debugger and the external circuit may be conducted while bypassing the DIB.
摘要翻译：提供一种具有用于与调试器进行接口的桥接器及其操作方法的集成电路（IC）。在一个实施例中，IC包括在其上实现的调试控制电路和调试接口块（DIB）。 DIB耦合到调试控制电路。 IC还包括用于调试器的接口和用于外部电路的多个接口，每个接口耦合到调试控制电路。调试控制电路可以用作用于将外部调试器耦合到DIB的桥，以及通过相应的接口耦合到IC的外部电路。调试控制电路可以建立调试器和其中一个外部电路之间的连接。调试器和外部电路之间的通信可以绕过DIB进行。

79. 发明申请

US20160240193A1 Clock Switching in Always-On Component 有权
标题翻译：始终打开组件中的时钟切换
公开(公告)号：US20160240193A1
公开(公告)日：2016-08-18
申请号：US14621093
申请日：2015-02-12
申请人： Apple Inc.
发明人： Manu Gulati , Gilbert H. Herbeck , Alexei E. Kosut , Girault W. Jones , Timothy J. Millet
IPC分类号： G10L15/28 , G10L19/00 , G10L15/22
CPC分类号： G10L15/28 , G10L15/08 , G10L15/22 , G10L2015/088 , G10L2015/223
摘要： In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.
摘要翻译：在一个实施例中，芯片上的系统（SOC）可以包括一个或多个中央处理单元（CPU），存储器控制器和被配置为当SOC的其余部分断电时保持通电的电路。该电路可以被配置为接收音频采样并将这些音频样本与预定模式相匹配。在SOC的其余部分断电的时间内，电路可以根据第一时钟进行操作。响应于检测样本中的预定模式，电路可以使存储器控制器和处理器加电。在上电过程中，具有比第一时钟具有一个或多个更好特征的第二时钟可以变得可用。电路可以切换到第二时钟，同时保持采样，或者丢失至多一个采样，或者不超过阈值数量的采样。

80. 发明申请

US20160054773A1 Method and Apparatus for Providing Telemetry for Power Management Functions 有权
标题翻译：为电源管理功能提供遥测的方法和装置
公开(公告)号：US20160054773A1
公开(公告)日：2016-02-25
申请号：US14466205
申请日：2014-08-22
申请人： Apple Inc.
发明人： Manu Gulati , Parin Patel , Keith Cox , Derek Iwamoto , Cyril de la Cropte de Chanterac , Christopher J. Young
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： A method and apparatus for providing telemetry for use in power control functions is disclosed. A system includes an integrated circuit (IC) having a first power management circuit. The IC also includes a number of functional circuit blocks within a number of different power domains. A second power management circuit is implemented external to the IC and includes a number of voltage regulators. Each of the power domains is coupled to receive power from one voltage regulators. During operation, the first power management circuit may send commands requesting the change of one or more voltages provided to the IC. The second power management circuit may respond by performing the requested voltage change(s), and may also provide telemetry data to the first power management circuit. The second power management circuit may also provide telemetry data responsive to receiving a no operation command from the first power management circuit.
摘要翻译：公开了一种用于提供用于功率控制功能的遥测的方法和装置。一种系统包括具有第一电源管理电路的集成电路（IC）。 IC还包括多个不同功率域内的多个功能电路块。第二电源管理电路在IC外部实现并且包括多个电压调节器。每个电源域被耦合以从一个电压调节器接收电力。在操作期间，第一电源管理电路可以发送请求改变提供给IC的一个或多个电压的命令。第二电力管理电路可以通过执行所请求的电压变化来响应，并且还可以向第一电力管理电路提供遥测数据。第二电力管理电路还可以响应于从第一电力管理电路接收无操作命令来提供遥测数据。

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