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71. 发明授权

US09564575B2 Dual encapsulation integration scheme for fabricating integrated circuits with magnetic random access memory structures 有权
标题翻译：用于制造具有磁性随机存取存储器结构的集成电路的双封装集成方案
公开(公告)号：US09564575B2
公开(公告)日：2017-02-07
申请号：US14586415
申请日：2014-12-30
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Danny Pak-Chum Shum , Hai Cong , Yi Jiang , Juan Boon Tan
IPC分类号： H01L43/08 , H01L43/12 , H01L27/22 , H01L43/02
CPC分类号： H01L43/02 , H01L27/222 , H01L43/08 , H01L43/12
摘要： Integrated circuits with magnetic random access memory (MRAM) and dual encapsulation for double magnesium oxide tunnel barrier structures and methods for fabricating the same are disclosed herein. As an illustration, an integrated circuit includes a magnetic random access memory structure that includes a bottom electrode that has a bottom electrode width and has bottom electrode sidewalls and a fixed layer overlying the bottom electrode that has a fixed layer width that is substantially equal to the bottom electrode width and has fixed layer sidewalls. The MRAM structure of the integrated circuit further includes a free layer overlying a central area of the fixed layer. Still further, the MRAM structure of the integrated circuit includes a first encapsulation layer disposed along the free layer sidewalls and a second encapsulation layer disposed along the bottom electrode sidewalls and the fixed layer sidewalls.
摘要翻译：具有磁性随机存取存储器（MRAM）和双重氧化镁隧道势垒结构的双重封装的集成电路及其制造方法在本文中公开。作为说明，集成电路包括磁性随机存取存储器结构，其包括具有底部电极宽度并具有底部电极侧壁的底部电极和覆盖底部电极的固定层，该固定层具有基本上等于底电极宽度并具有固定层侧壁。集成电路的MRAM结构还包括覆盖固定层的中心区域的自由层。此外，集成电路的MRAM结构包括沿自由层侧壁设置的第一封装层和沿着底部电极侧壁和固定层侧壁设置的第二封装层。

72. 发明申请

US20160343773A1 INTERPOSERS FOR INTEGRATED CIRCUITS WITH MULTIPLE-TIME PROGRAMMING AND METHODS FOR MANUFACTURING THE SAME 有权
标题翻译：具有多个时间编程的集成电路的间隔器及其制造方法
公开(公告)号：US20160343773A1
公开(公告)日：2016-11-24
申请号：US14719467
申请日：2015-05-22
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Juan Boon Tan , Yi Jiang , Danny Shum , Shunqiang Gong
IPC分类号： H01L27/24 , H01L43/12 , H01L43/08 , H01L27/22 , H01L45/00
CPC分类号： H01L27/2436 , H01L27/228 , H01L43/08 , H01L43/12 , H01L45/06 , H01L45/144 , H01L45/16 , H01L45/1675 , H01L2224/16225 , H01L2924/15311
摘要： An interposer for an integrated circuit includes a first side and a second side. The interposer includes a substrate and a via disposed in the substrate. A first electrical contact is disposed on the first side. A second electrical contact is disposed on the second side and electrically connected to the via. The interposer also includes a multiple-time programmable (“MTP”) element electrically connected to the first electrical contact and/or the via.
摘要翻译：用于集成电路的插入器包括第一侧和第二侧。插入器包括衬底和布置在衬底中的通孔。第一电触头设置在第一侧上。第二电触点设置在第二侧上并电连接到通孔。插入器还包括电连接到第一电触点和/或通孔的多时间可编程（“MTP”）元件。

73. 发明授权

US09437550B2 TSV without zero alignment marks 有权
标题翻译： TSV无零对齐标记
公开(公告)号：US09437550B2
公开(公告)日：2016-09-06
申请号：US14106870
申请日：2013-12-16
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Shunqiang Gong , Juan Boon Tan , Wei Liu , Hai Cong
IPC分类号： H01L21/4763 , H01L23/544 , H01L21/768
CPC分类号： H01L23/544 , H01L21/76816 , H01L21/76898 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor device and method of forming a semiconductor device are disclosed. The method includes providing a substrate. A dielectric layer is formed on the substrate. The dielectric layer includes an upper and lower level. The upper level of the dielectric layer is patterned to form at least first and second trench openings and alignment mark openings. One of the first and second trench openings serve as a through via (TV) trench while another trench opening serves as an interconnect trench. A TV opening aligned to the TV trench is formed. The TV opening extends partially into the substrate. A conductive layer is formed over the substrate to fill the trenches and the openings.
摘要翻译：公开了形成半导体器件的半导体器件和方法。该方法包括提供基板。在基板上形成电介质层。电介质层包括上层和下层。图案化电介质层的上层以形成至少第一和第二沟槽开口和对准标记开口。第一和第二沟槽开口中的一个用作通孔（TV）沟槽，而另一个沟槽开口用作互连沟槽。形成了与电视槽对准的电视开口。 TV开口部分地延伸到基板中。导电层形成在衬底上以填充沟槽和开口。

74. 发明申请

US20160190432A1 DUAL ENCAPSULATION INTEGRATION SCHEME FOR FABRICATING INTEGRATED CIRCUITS WITH MAGNETIC RANDOM ACCESS MEMORY STRUCTURES 有权
标题翻译：用于制造具有磁性随机存取存储器结构的集成电路的双重封装集成方案
公开(公告)号：US20160190432A1
公开(公告)日：2016-06-30
申请号：US14586415
申请日：2014-12-30
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Danny Pak-Chum Shum , Hai Cong , Yi Jiang , Juan Boon Tan
IPC分类号： H01L43/02 , H01L27/22 , H01L43/12 , H01L43/08
CPC分类号： H01L43/02 , H01L27/222 , H01L43/08 , H01L43/12
摘要： Integrated circuits with magnetic random access memory (MRAM) and dual encapsulation for double magnesium oxide tunnel barrier structures and methods for fabricating the same are disclosed herein. As an illustration, an integrated circuit includes a magnetic random access memory structure that includes a bottom electrode that has a bottom electrode width and has bottom electrode sidewalls and a fixed layer overlying the bottom electrode that has a fixed layer width that is substantially equal to the bottom electrode width and has fixed layer sidewalls. The MRAM structure of the integrated circuit further includes a free layer overlying a central area of the fixed layer. Still further, the MRAM structure of the integrated circuit includes a first encapsulation layer disposed along the free layer sidewalls and a second encapsulation layer disposed along the bottom electrode sidewalls and the fixed layer sidewalls.
摘要翻译：具有磁性随机存取存储器（MRAM）和双重氧化镁隧道势垒结构的双重封装的集成电路及其制造方法在本文中公开。作为说明，集成电路包括磁性随机存取存储器结构，其包括具有底部电极宽度并具有底部电极侧壁的底部电极和覆盖底部电极的固定层，该固定层具有基本上等于底电极宽度并具有固定层侧壁。集成电路的MRAM结构还包括覆盖固定层的中心区域的自由层。此外，集成电路的MRAM结构包括沿自由层侧壁设置的第一封装层和沿着底部电极侧壁和固定层侧壁设置的第二封装层。

75. 发明申请

US20160190041A1 DEVICE WITHOUT ZERO MARK LAYER 有权
标题翻译：没有零标记层的设备
公开(公告)号：US20160190041A1
公开(公告)日：2016-06-30
申请号：US14981873
申请日：2015-12-28
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Shunqiang Gong , Juan Boon Tan , Shijie Wang , Mahesh Bhatkar , Daxiang Wang
IPC分类号： H01L23/48 , H01L21/768 , H01L23/544 , H01L23/528
CPC分类号： H01L21/76898 , H01L23/525 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.
摘要翻译：公开了用于形成装置的装置和方法。该方法包括提供具有第一表面和第二表面的基底。在衬底中形成至少一个通硅通孔（TSV）开口。 TSV开口延伸穿过衬底的第一和第二表面。在基板上形成与对准标记对应的对准沟槽。对准沟槽从衬底的第一表面延伸到比TSV开口的深度浅的深度。介电衬里层设置在衬底上。电介质衬垫层至少对TSV开口的侧壁进行排列。导电层设置在衬底上。导电层填充至少TSV开口以形成TSV接触。在衬底上形成再分布层（RDL）。使用掩模版图案化RDL层以形成对应于TSV接触焊盘的至少一个开口。使用衬底中的对准标记对准标线。

76. 发明申请

US20160189971A1 ETCH BIAS CONTROL 有权
标题翻译： ETCH偏差控制
公开(公告)号：US20160189971A1
公开(公告)日：2016-06-30
申请号：US14981881
申请日：2015-12-28
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Wanbing Yi , Chin Chuan Neo , Hai Cong , Kin Wai Tang , Weining Li , Juan Boon Tan
IPC分类号： H01L21/308 , H01L21/027
CPC分类号： H01L21/3088 , G03F1/00 , G03F1/144 , G03F1/36 , G03F1/38 , G03F1/80 , H01L21/0274 , H01L21/0337 , H01L21/3081
摘要： A semiconductor device and method for forming a semiconductor device are presented. The method includes providing a patterned reticle having a pattern perimeter defined by active and dummy patterns. The dummy patterns include dummy structures modified according to a density equation. The patterned reticle is used to pattern a resist layer on a substrate with a device layer. An etch is performed to pattern the device layer using the patterned resist layer. Additional processing is performed to complete formation of the device.
摘要翻译：本发明提供一种用于形成半导体器件的半导体器件和方法。该方法包括提供具有由有源和虚拟图案限定的图案周长的图案化掩模版。虚拟图案包括根据密度方程修改的虚拟结构。图案化的掩模版用于在具有器件层的衬底上图案化抗蚀剂层。执行蚀刻以使用图案化的抗蚀剂层对器件层进行图案化。执行附加处理以完成设备的形成。

77. 发明授权

US09305886B2 Integrated circuits having crack-stop structures and methods for fabricating the same 有权
标题翻译：具有断裂结构的集成电路及其制造方法
公开(公告)号：US09305886B2
公开(公告)日：2016-04-05
申请号：US14132368
申请日：2013-12-18
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Wei Shao , Fan Zhang , Juan Boon Tan
IPC分类号： H01L21/4763 , H01L23/00 , H01L21/768 , H01L21/311 , H01L23/522 , H01L21/263
CPC分类号： H01L23/562 , H01L21/2633 , H01L21/31116 , H01L21/76805 , H01L21/76807 , H01L21/76879 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes fabricating a crack-stop structure that extends through a plurality of metallization layers above a semiconductor substrate. The plurality of metallization layers includes a first metallization layer and a second metallization layer that overlies the first metallization layer. Fabricating the crack-stop structure includes forming a first via-bar overlying and coupled to a first metal line of the first metallization layer that is disposed in a first ILD layer of dielectric material. The first via-bar is disposed in a second ILD layer of dielectric material and has a first width. A second metal line of the second metallization layer that is in the second ILD layer is formed overlying and coupled to the first via-bar. The second metal line has a second width that is from about 1 to about 5 times the first width.
摘要翻译：提供了用于制造集成电路的集成电路和方法。在一个示例中，制造集成电路的方法包括制造延伸穿过半导体衬底上的多个金属化层的裂纹 - 停止结构。多个金属化层包括覆盖在第一金属化层上的第一金属化层和第二金属化层。制造裂纹 - 停止结构包括形成第一通孔条，其覆盖并耦合到第一金属化层的设置在介电材料的第一ILD层中的第一金属线。第一通孔杆设置在介电材料的第二ILD层中并且具有第一宽度。位于第二ILD层中的第二金属化层的第二金属线形成为覆盖并耦合到第一通孔条。第二金属线具有第一宽度的约1至约5倍的第二宽度。

78. 发明授权

US11444045B2 Bonding structures of semiconductor devices 有权
公开(公告)号：US11444045B2
公开(公告)日：2022-09-13
申请号：US16994644
申请日：2020-08-16
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Ramasamy Chockalingam , Juan Boon Tan , Xiaodong Li , Kai Chong Chan , Ranjan Rajoo
IPC分类号： H01L23/08 , H01L23/52 , H01L29/40 , H01L23/00
摘要： A semiconductor device is provided that includes a bond pad, an insulating layer, and a bonding structure. The bond pad is in a dielectric layer and the insulating layer is over the bond pad; the insulating layer having an opening over the bond pad formed therein. The bonding structure electrically couples the bond pad in the opening. The bonding structure has a height that at least extends to an upper surface of the insulating layer.

79. 发明授权

US11289649B2 Non-volatile memory elements with a narrowed electrode 有权
公开(公告)号：US11289649B2
公开(公告)日：2022-03-29
申请号：US16846940
申请日：2020-04-13
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Lup San Leong , Curtis Chun-I Hsieh , Juan Boon Tan , Eng Huat Toh , Kin Wai Tang
IPC分类号： H01L45/00 , H01L27/24
摘要： Structures for a non-volatile memory element and methods of forming a structure for a non-volatile memory element. A switching layer is positioned over a first electrode, and a dielectric layer is positioned over the switching layer. The dielectric layer includes an opening extending to the switching layer. A second electrode includes a portion in the opening in the dielectric layer. The portion of the second electrode is in contact with a first portion of the switching layer. The switching layer further includes a second portion positioned between the dielectric layer and the first electrode.

80. 发明授权

US11270938B2 Semiconductor devices and methods of forming semiconductor devices 有权
公开(公告)号：US11270938B2
公开(公告)日：2022-03-08
申请号：US16910100
申请日：2020-06-24
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Kai Kang , Yi Jiang , Curtis Chun-I Hsieh , Wanbing Yi , Juan Boon Tan
IPC分类号： H01L23/522 , H01L21/283 , H01L49/02 , H01L45/00 , G11C5/06 , H01L43/12 , H01L27/22 , H01L27/24
摘要： A semiconductor device may be provided, including a base layer, an insulating layer arranged over the base layer, a memory structure arranged at least partially within the insulating layer, where the memory structure may include a first electrode, a second electrode, and an intermediate element between the first electrode and the second electrode, and a resistor arranged at least partially within the insulating layer, where the resistor may be arranged in substantially a same horizontal plane with one of the first electrode and the second electrode.

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