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1. 发明授权

US10446607B2 Integrated two-terminal device with logic device for embedded application 有权
公开(公告)号：US10446607B2
公开(公告)日：2019-10-15
申请号：US15393200
申请日：2016-12-28
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Wanbing Yi , Curtis Chun-I Hsieh , Juan Boon Tan , Soh Yun Siah , Hai Cong , Alex See , Young Seon You , Danny Pak-Chum Shum , Hyunwoo Yang
IPC分类号： H01L27/22 , H01L43/08 , H01L43/12
摘要： Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the regions. A two-terminal device element which includes a device layer coupled in between first and second terminals is formed over the first upper dielectric layer in the second region. The first terminal contacts the metal line in the first upper interconnect level of the second region and the second terminal is formed on the device layer. An encapsulation liner covers at least exposed side surfaces of the device layer of the two-terminal device element. A dielectric layer which includes a second upper interconnect level with dual damascene interconnects is provided in the regions. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the dual damascene interconnect in the second region is coupled to the two-terminal device element.

2. 发明授权

US09805971B2 Method of forming a via contact 有权
公开(公告)号：US09805971B2
公开(公告)日：2017-10-31
申请号：US14658261
申请日：2015-03-16
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Rui Li , Chin Chuan Neo , Hai Cong
IPC分类号： H01L21/768 , H01L21/311 , H01L21/8234
CPC分类号： H01L21/76804 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76805 , H01L21/76897 , H01L21/823475
摘要： Semiconductor device and method for forming a semiconductor device are presented. The method includes providing a substrate having a device component with a contact region. A contact dielectric layer is formed on the substrate. The contact dielectric layer covers the substrate and device component. At least one contact opening is formed through the contact dielectric layer. Upper portion of the contact opening includes wider opening with tapered sidewall profile while lower portion of the contact opening includes narrower opening with vertical sidewall profile.

3. 发明授权

US10608046B2 Integrated two-terminal device with logic device for embedded application 有权
公开(公告)号：US10608046B2
公开(公告)日：2020-03-31
申请号：US16503967
申请日：2019-07-05
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Wanbing Yi , Curtis Chun-I Hsieh , Juan Boon Tan , Soh Yun Siah , Hai Cong , Alex See , Young Seon You , Danny Pak-Chum Shum , Hyunwoo Yang
IPC分类号： H01L27/22 , H01L43/08 , H01L43/12
摘要： Devices and methods of forming a device. A two-terminal device element includes a device stack coupled between first and second terminals. The first terminal contacts a metal line in an underlying interconnect level, and the second terminal is formed over the device layer. An encapsulation liner covers exposed side surfaces of the device stack of the two-terminal device element. A dual damascene interconnect is coupled to the two-terminal device element.

4. 发明授权

US10115625B2 Methods for removal of hard mask 有权
公开(公告)号：US10115625B2
公开(公告)日：2018-10-30
申请号：US15394851
申请日：2016-12-30
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Liang Li , Yun Ling Tan , Hai Cong , Changwei Pei , Alex See
IPC分类号： H01L21/762 , H01L21/306 , H01L21/308 , H01L21/3065 , H01L27/11548 , H01L27/11575
摘要： Embodiments of a method of processing semiconductor devices are presented. The method includes providing a substrate prepared with isolation regions having a non-planar surface topology. The substrate includes at least first and second regions. The first region includes a memory region and the second region includes a logic region. A hard mask layer is formed covering the substrate and the isolation regions with non-planar surface topology. The method includes selectively processing an exposed portion of the hard mask layer over a select region while protecting a portion of the hard mask layer over a non-select region. The top substrate area and isolation regions of the non-select region are not exposed during processing of the portion of the hard mask layer over the select region. Hard mask residue is completely removed over the select region during processing of the exposed portion of the hard mask layer.

5. 发明授权

US10103097B2 CD control 有权
公开(公告)号：US10103097B2
公开(公告)日：2018-10-16
申请号：US14484220
申请日：2014-09-11
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Zheng Zou , Alex See , Huang Liu , Hai Cong
IPC分类号： H01L21/302 , H01L23/48 , H01L21/768 , H01L23/522 , H01L21/311
摘要： A method includes providing a substrate with a patterned second layer over a first layer. The second layer includes a second layer opening having a first CD equal to the CD produced by a lithographic system (CDL). CDL is larger than a desired CD (CDD). A third layer is formed to fill the opening, leaving a top surface of the second layer exposed. The second layer is removed to produce a mesa formed by the third layer. The CD of the mesa is equal to about the first CD. The mesa is trimmed to produce a mesa with a second CD equal to about CDD. A fourth layer is formed to cover the first layer, leaving a top of the mesa exposed. The substrate is etched to remove the mesa and a portion of the first layer below the mesa to form an opening in the first layer with CDD.

6. 发明授权

US09520299B2 Etch bias control 有权
标题翻译：蚀刻偏压控制
公开(公告)号：US09520299B2
公开(公告)日：2016-12-13
申请号：US14981881
申请日：2015-12-28
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Wanbing Yi , Chin Chuan Neo , Hai Cong , Kin Wai Tang , Weining Li , Juan Boon Tan
IPC分类号： H01L21/308 , H01L21/027 , G03F1/00 , G03F1/36 , H01L21/033
CPC分类号： H01L21/3088 , G03F1/00 , G03F1/144 , G03F1/36 , G03F1/38 , G03F1/80 , H01L21/0274 , H01L21/0337 , H01L21/3081
摘要： A semiconductor device and method for forming a semiconductor device are presented. The method includes providing a patterned reticle having a pattern perimeter defined by active and dummy patterns. The dummy patterns include dummy structures modified according to a density equation. The patterned reticle is used to pattern a resist layer on a substrate with a device layer. An etch is performed to pattern the device layer using the patterned resist layer. Additional processing is performed to complete formation of the device.
摘要翻译：本发明提供一种用于形成半导体器件的半导体器件和方法。该方法包括提供具有由有源和虚拟图案限定的图案周长的图案化掩模版。虚拟图案包括根据密度方程修改的虚拟结构。图案化的掩模版用于在具有器件层的衬底上图案化抗蚀剂层。执行蚀刻以使用图案化的抗蚀剂层对器件层进行图案化。执行附加处理以完成设备的形成。

7. 发明授权

US09230886B2 Method for forming through silicon via with wafer backside protection 有权
公开(公告)号：US09230886B2
公开(公告)日：2016-01-05
申请号：US14575639
申请日：2014-12-18
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Lup San Leong , Zheng Zou , Alex Kai Hung See , Hai Cong , Xuesong Rao , Yun Ling Tan , Huang Liu
IPC分类号： H01L23/48 , H01L23/00 , H01L21/768 , H01L21/02 , H01L21/48
CPC分类号： H01L23/481 , H01L21/02107 , H01L21/486 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/13009 , H01L2224/1357
摘要： Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.

8. 发明申请

US20150349095A1 METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH NONVOLATILE MEMORY DEVICES 审中-公开
标题翻译：用非易失性存储器件制造集成电路的方法
公开(公告)号：US20150349095A1
公开(公告)日：2015-12-03
申请号：US14294984
申请日：2014-06-03
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Chiew Wah Yap , Hai Cong , Zhehui Wang , Thomas Wang , Wei Loong Loh
IPC分类号： H01L29/66 , H01L21/283 , H01L27/115 , H01L29/40
CPC分类号： H01L29/66825 , H01L27/11521 , H01L29/7881
摘要： Methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes forming a stack gate structure overlying a semiconductor substrate. The method forms a select gate material overlying the stack gate structure and the semiconductor substrate and having a planar surface overlying the stack gate structure. The method includes anisotropically etching the select gate material to define a select gate adjacent the stack gate structure, wherein the select gate is formed with a planar upper surface.
摘要翻译：提供了制造集成电路的方法。用于制造集成电路的示例性方法包括形成覆盖半导体衬底的堆叠栅极结构。该方法形成覆盖堆叠栅极结构和半导体衬底并且具有覆盖堆叠栅极结构的平坦表面的选择栅极材料。该方法包括各向异性蚀刻选择栅极材料以限定邻近堆叠栅极结构的选择栅极，其中选择栅极形成有平坦的上表面。

9. 发明授权

US09972775B2 Integrated magnetic random access memory with logic device having low-k interconnects 有权
公开(公告)号：US09972775B2
公开(公告)日：2018-05-15
申请号：US15063544
申请日：2016-03-08
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Danny Pak-Chum Shum , Juan Boon Tan , Yi Jiang , Wanbing Yi , Francis Yong Wee Poh , Hai Cong
IPC分类号： H01L29/82 , H01L43/12 , H01L43/08 , H01L27/22
CPC分类号： H01L43/12 , H01L27/228 , H01L43/08
摘要： Device and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first, second and third regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the first and second regions. A MRAM cell which includes a MTJ element sandwiched between top and bottom electrodes is formed in the second region. The bottom electrode is in direct contact with the metal line in the first upper interconnect level of the second region. A dielectric layer which includes a second upper interconnect level with a dual damascene interconnect in the first region and a damascene interconnect in the second region is provided over the first upper dielectric layer. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the damascene interconnect in the second region is coupled to the MTJ element.

10. 发明授权

US08836139B2 CD control 有权
标题翻译： CD控制
公开(公告)号：US08836139B2
公开(公告)日：2014-09-16
申请号：US13655408
申请日：2012-10-18
申请人： Globalfoundries Singapore Pte. Ltd.
发明人： Zheng Zou , Alex See , Huang Liu , Hai Cong
IPC分类号： H01L21/302 , H01L21/768 , H01L23/48
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/31144 , H01L21/76816 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： A method includes providing a substrate with a patterned second layer over a first layer. The second layer includes a second layer opening having a first CD equal to the CD produced by a lithographic system (CDL). CDL is larger than a desired CD (CDD). A third layer is formed to fill the opening, leaving a top surface of the second layer exposed. The second layer is removed to produce a mesa formed by the third layer. The CD of the mesa is equal to about the first CD. The mesa is trimmed to produce a mesa with a second CD equal to about CDD. A fourth layer is formed to cover the first layer, leaving a top of the mesa exposed. The substrate is etched to remove the mesa and a portion of the first layer below the mesa to form an opening in the first layer with CDD.
摘要翻译：一种方法包括在第一层上提供具有图案化的第二层的衬底。第二层包括具有等于由光刻系统（CDL）产生的CD的第一CD的第二层开口。 CDL大于所需的CD（CDD）。形成第三层以填充开口，留下第二层的顶表面露出。去除第二层以产生由第三层形成的台面。台面的CD等于第一张CD。台面被修剪以产生具有等于约CDD的第二CD的台面。形成第四层以覆盖第一层，留下台面的顶部。蚀刻衬底以去除台面和台面下面的第一层的一部分以在具有CDD的第一层中形成开口。

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