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71. 发明申请

US20140211541A1 READ MEASUREMENT OF A PLURALITY OF RESISTIVE MEMORY CELLS 有权
标题翻译：阅读测量电阻记忆细胞的多样性
公开(公告)号：US20140211541A1
公开(公告)日：2014-07-31
申请号：US14164725
申请日：2014-01-27
申请人： International Business Machines Corporation
发明人： ABU SEBASTIAN , Nikolaos Papandreou , Charalampos Pozidis
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/5685 , G11C13/0002 , G11C13/0061 , G11C2013/0057
摘要： A method for read measurement of a plurality N of resistive memory cells having a plurality M of programmable levels is suggested. The method includes a step of reading back from a number of reference cells to obtain a reading back parameter, a step of determining an actual read voltage for the N memory cells based on the obtained reading back parameter for obtaining a target read current at a following read measurement, and, a step of applying the determined actual read voltage to the N memory cells at the following read measurement.
摘要翻译：提出了一种用于读取测量具有多个可编程电平的多个N个电阻存储器单元的方法。该方法包括从多个参考单元读取以获得回读参数的步骤，基于获得的读回参数确定N个存储单元的实际读取电压的步骤，用于获得下一个目标读取电流读取测量，以及在以下读取测量时将所确定的实际读取电压施加到N个存储器单元的步骤。

72. 发明申请

US20130086457A1 DETECTING CODEWORDS IN SOLID-STATE STORAGE DEVICES 有权
标题翻译：检测固态储存装置中的编码
公开(公告)号：US20130086457A1
公开(公告)日：2013-04-04
申请号：US13622451
申请日：2012-09-19
申请人： International Business Machines Corporation
发明人： Thomas Mittelholzer , Nikolaos Papandreou , Charalampos Pozidis
IPC分类号： H03M13/51
CPC分类号： G11C11/5678 , G11C2211/563 , G11C2211/5634
摘要： A method for detecting codewords in solid-state storage devices. The method includes the steps of: obtaining respective read signals by reading memory cells that stores a group of codewords, where each of the read signals includes N signal components corresponding to respective symbols of the codeword; producing an ordered read signal by ordering the components of each of the read signals according to a signal level; producing an average read signal by averaging corresponding components of the ordered read signals; determining a reference signal level that corresponds to each of q levels of the memory cells in relation to the average read signal with predefined probabilities of each symbol value occurring at each symbol position in the codeword, where the symbols of the codeword are ordered according to the symbol value; and detecting the codeword corresponding to each of the read signal in relation to the reference signal levels.
摘要翻译：一种用于检测固态存储设备中的码字的方法。该方法包括以下步骤：通过读取存储一组码字的存储器单元来获得相应的读取信号，其中每个读取信号包括与码字的各个符号对应的N个信号分量; 通过根据信号电平对每个读取信号的分量进行排序来产生有序的读取信号; 通过对有序读取信号的相应分量进行平均来产生平均读取信号; 确定与所述平均读取信号相对应的所述存储器单元的每个q电平的参考信号电平，所述参考信号电平具有在所述码字中的每个符号位置处出现的每个符号值的预定义概率，其中所述码字的符号根据符号值并且相对于参考信号电平检测与每个读取信号相对应的码字。

73. 发明公开

US20240071542A1 CALIBRATION OF THRESHOLD VOLTAGE SHIFT VALUES 审中-公开
公开(公告)号：US20240071542A1
公开(公告)日：2024-02-29
申请号：US17821608
申请日：2022-08-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Radu Ioan Stoica , Roman Alexander Pletka , Nikolas Ioannou , Nikolaos Papandreou , Charalampos Pozidis , Timothy J. Fisher , Aaron Daniel Fry
IPC分类号： G11C29/02 , G11C29/52
CPC分类号： G11C29/021 , G11C29/52
摘要： Threshold voltage shift values, or TVS values, are calibrated for a non-volatile memory unit including strings of memory cells organized into memory pages, the memory pages being organized into blocks. The calibration involves a read operation to read a given page of the memory pages, based on given one or more TVS values for the given page. In response to a read failure of the read operation, the calibration determines one or more corrected TVS values based on one or more reference TVS values of one or more reference pages of the memory pages. The calibration subsequently performs a read operation to read the given page based on the one or more corrected TVS values. This calibration exploits TVS values of reference pages to determine corrected TVS values of the failing page, instead of finding appropriate TVS values by repeatedly re-reading the failing page.

74. 发明授权

US11908531B2 Detecting and managing under-program failures in non-volatile memory 有权
公开(公告)号：US11908531B2
公开(公告)日：2024-02-20
申请号：US17495574
申请日：2021-10-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Nikolaos Papandreou , Roman Alexander Pletka , Radu Ioan Stoica , Nikolas Ioannou , Charalampos Pozidis , Timothy J. Fisher , Aaron Daniel Fry
IPC分类号： G11C16/34 , G11C16/32 , G11C16/10 , G11C16/26
CPC分类号： G11C16/3459 , G11C16/102 , G11C16/26 , G11C16/32 , G11C16/3404 , G11C16/3495
摘要： A non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages. A controller of the non-volatile memory issues a command to perform a programming pass for a physical page among the multiple physical pages. The controller determines whether or not the programming pass took less than a minimum threshold time and no program fail status indication was received. Based on determining the programming pass took less than a minimum threshold time and no program fail status indication was received, the controller detects an under-programming error and performs mitigation for the detected under-programming error.

75. 发明授权

US11886725B2 Accelerating decision tree inferences 有权
公开(公告)号：US11886725B2
公开(公告)日：2024-01-30
申请号：US17347918
申请日：2021-06-15
申请人： International Business Machines Corporation
发明人： Jan Van Lunteren , Charalampos Pozidis
IPC分类号： G06F7/00 , G06F3/06 , G06N20/20 , G06F17/11 , G06F12/0895 , G06N5/01
CPC分类号： G06F3/064 , G06F3/0604 , G06F3/0656 , G06F3/0673 , G06F12/0895 , G06F17/11 , G06N5/01 , G06N20/20 , G06F2212/608
摘要： Methods, computer program products, and/or systems are provided that perform the following operations: setting a memory buffer having contiguous memory blocks; obtaining a decision tree comprising nodes including split nodes and leaf nodes, wherein each of the split nodes includes at least two child nodes that are ordered according to a likelihood of accessing a child node after each of the split nodes; mapping the nodes onto respective blocks of the memory blocks, each of the memory blocks storing attributes of a corresponding one of the nodes, wherein each of the split nodes and any child nodes of each split node are mapped onto successive blocks, wherein ordered child nodes of a same one of the split nodes are mapped onto successive blocks; executing the nodes by processing the attributes of the nodes as accessed from the memory according to an order of the memory blocks in the memory buffer.

76. 发明授权

US11861175B2 Latency in data storage systems 有权
公开(公告)号：US11861175B2
公开(公告)日：2024-01-02
申请号：US17654328
申请日：2022-03-10
申请人： International Business Machines Corporation
发明人： Radu Ioan Stoica , Aaron Daniel Fry , Nikolas Ioannou , Nikolaos Papandreou , Roman Alexander Pletka , Charalampos Pozidis , Jenny L Brown
IPC分类号： G06F3/06
CPC分类号： G06F3/0611 , G06F3/0655 , G06F3/0679
摘要： A method, system, and computer program product are disclosed. The method includes receiving a write request to a system and calculating, based on operating parameters of the system, a total processing time associated with servicing the write request in the system. The method also includes determining an actual time taken to store data specified in the write request and, when the actual time is less than the total processing time, delaying sending a completion message for the write request to an I/O interface.

77. 发明公开

US20230325681A1 DYNAMICALLY OPTIMIZING DECISION TREE INFERENCES 审中-公开
公开(公告)号：US20230325681A1
公开(公告)日：2023-10-12
申请号：US17658841
申请日：2022-04-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jan Van Lunteren , Nikolaos Papandreou , Charalampos Pozidis , Martin Petermann , Thomas Parnell , Milos Stanisavljevic
IPC分类号： G06N5/00 , G06N5/04 , G06F12/0802 , G06F12/1027
CPC分类号： G06N5/003 , G06N5/04 , G06F12/0802 , G06F12/1027
摘要： A method of dynamically optimizing decision tree inference is provided. The method, which is performed at the computerized system, repeatedly executes one or more decision trees for inference purposes and repeatedly performs an optimization procedure according to two-phase cycles. Each cycle includes two alternating phases, i.e., a first phase followed by a second phase. The decision trees are executed based on a reference data structure, whereby attributes of nodes of the decision trees are repeatedly accessed from the reference data structure during the first phase of each of the cycles. First, the accessed attributes are monitored during the first phase of each cycle, which leads to update statistical characteristics of the nodes. Second, a substitute data structure is configured during the second phase of each cycle based on the updated statistical characteristics. Third, the reference data structure is updated in accordance with the substitute data structure.

78. 发明授权

US11762569B2 Workload based relief valve activation for hybrid controller architectures 有权
公开(公告)号：US11762569B2
公开(公告)日：2023-09-19
申请号：US16667702
申请日：2019-10-29
申请人： International Business Machines Corporation
发明人： Radu Ioan Stoica , Roman Alexander Pletka , Timothy Fisher , Nikolaos Papandreou , Sasa Tomic , Nikolas Ioannou , Aaron Daniel Fry , Charalampos Pozidis , Andrew D. Walls
IPC分类号： G06F3/06 , G06F12/02 , G06F9/30
CPC分类号： G06F3/064 , G06F3/0611 , G06F3/0679 , G06F9/3004 , G06F12/0246 , G06F2209/5011
摘要： A computer-implemented method, according to one embodiment, includes: maintaining a first subset of the plurality of blocks in a first pool, where the blocks maintained in the first pool are configured in SLC mode. A second subset of the plurality of blocks is maintained in a second pool, where the blocks maintained in the second pool are configured in multi-bit-per-cell mode. A current I/O rate for the memory is identified during runtime, and a determination is made as to whether the current I/O rate is outside a first range. In response to determining that the current I/O rate is not outside the first range, the blocks maintained in the first pool are used to satisfy incoming host writes. Moreover, in response to determining that the current I/O rate is outside the first range, the blocks maintained in the second pool are used to satisfy incoming host writes.

79. 发明公开

US20230177351A1 ACCELERATING DECISION TREE INFERENCES BASED ON TENSOR OPERATIONS 审中-公开
公开(公告)号：US20230177351A1
公开(公告)日：2023-06-08
申请号：US17457684
申请日：2021-12-06
申请人： International Business Machines Corporation
发明人： Nikolaos Papandreou , Charalampos Pozidis , Milos Stanisavljevic , Jan Van Lunteren , Thomas Parnell , Cedric Lichtenau , Andrew M. Sica
IPC分类号： G06N5/00 , G06K9/62
CPC分类号： G06N5/003 , G06K9/623 , G06K9/6201
摘要： Accessing a value M identifying M top levels of one or more N decision trees, wherein 1 ≤ M

80. 发明申请

US20220358356A1 COMPUTERIZED METHODS OF FORECASTING A TIMESERIES USING ENCODER-DECODER RECURRENT NEURAL NETWORKS AUGMENTED WITH AN EXTERNAL MEMORY BANK 有权
公开(公告)号：US20220358356A1
公开(公告)日：2022-11-10
申请号：US17301990
申请日：2021-04-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Mircea R. Gusat , Konstantinos Kouziou , Charalampos Pozidis
IPC分类号： G06N3/08 , G06N3/04
摘要： A computer-implemented method forecasts a timeseries. The method includes loading and running a machine learning model. The machine learning model includes an encoder recurrent neural network (RNN) mapping an input sequence into a fixed-dimensionality vector c and a decoder RNN decoding the vector to produce an intermediate sequence. The model includes a fully connected feed-forward layer (FC-FFL) to produce an output sequence. The machine learning model is run concomitantly. Values of a given input sequence are coupled to produce a given output sequence in output of the FC-FFL. Values of a feedback sequence are stored in a location-addressable memory bank. The memory addresses of the memory bank are mapped onto a temporal sequence of the feedback sequence. Values stored are read to retrieve values of the feedback sequence. The retrieved values are fed to the decoder RNN as the model is being run to obtain the given output sequence.

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