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1. 发明申请

US20180025777A1 HIGH-RELIABILITY MEMORY READ TECHNIQUE 审中-公开
公开(公告)号：US20180025777A1
公开(公告)日：2018-01-25
申请号：US15213581
申请日：2016-07-19
申请人： SANDISK TECHNOLOGIES LLC
发明人： ADAM JACOBVITZ , XINDE HU
IPC分类号： G11C11/56 , G11C29/52 , G06F3/06 , G06F11/10
CPC分类号： G11C29/52 , G06F11/1072 , G11C11/5671 , G11C16/0483 , G11C16/349 , G11C2029/0409 , G11C2029/0411 , G11C2211/563 , G11C2211/5644
摘要： A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured, based on a metric associated with a portion of the non-volatile memory, to store a read technique indicator that indicates that the portion is to be read using a high-reliability read technique.

2. 发明授权

US09400747B2 Batch command techniques for a data storage device 有权
标题翻译：用于数据存储设备的批处理命令技术
公开(公告)号：US09400747B2
公开(公告)日：2016-07-26
申请号：US14264160
申请日：2014-04-29
申请人： SANDISK TECHNOLOGIES INC.
发明人： Daniel Edward Tuers , Abhijeet Manohar , Mark Murin , Mark Shlick , Menahem Lasser
IPC分类号： G11C29/00 , G06F12/02 , G06F13/16 , G06F11/10 , G11C11/56
CPC分类号： G06F12/0246 , G06F11/1072 , G06F13/16 , G06F2212/1016 , G06F2212/7205 , G11C11/5621 , G11C2211/562 , G11C2211/563
摘要： A data storage device includes a non-volatile memory and a controller. A method includes sending a memory command from the controller to the non-volatile memory. The memory command indicates multiple sense operations to be performed at a single plane of the non-volatile memory.
摘要翻译：数据存储装置包括非易失性存储器和控制器。一种方法包括从控制器向非易失性存储器发送存储器命令。存储器命令指示要在非易失性存储器的单个平面上执行的多个感测操作。

3. 发明授权

US09312029B2 Memory device and associated controlling method 有权
标题翻译：存储器和相关控制方法
公开(公告)号：US09312029B2
公开(公告)日：2016-04-12
申请号：US14309920
申请日：2014-06-20
申请人： Macronix International Co., Ltd.
发明人： Win-San Khwa , Chao-I Wu , Tzu-Hsiang Su
IPC分类号： G11C11/56 , G11C29/12 , G11C29/50 , G11C29/04 , G11C13/00
CPC分类号： G11C29/12 , G11C11/5678 , G11C13/0004 , G11C13/0035 , G11C13/004 , G11C13/0069 , G11C29/50008 , G11C2013/0092 , G11C2029/0409 , G11C2211/563 , G11C2211/5644 , G11C2211/5646
摘要： A memory device and associated controlling method are provided. The memory device includes a memory cell array, a sensing unit and a controller. The memory cell array has a plurality of memory cells. The sensing unit is electrically connected to the memory cell array and the controller. The sensing unit senses characteristic of a memory cell of the plurality of memory cells. The controller determines whether the characteristic of the one of the memory cells deviates and accordingly controls the memory cell array.
摘要翻译：提供了存储器件和相关联的控制方法。存储器件包括存储单元阵列，感测单元和控制器。存储单元阵列具有多个存储单元。感测单元电连接到存储单元阵列和控制器。感测单元感测多个存储单元的存储单元的特性。控制器确定存储器单元之一的特性是否偏离，从而控制存储单元阵列。

4. 发明授权

US09263125B2 Nonvolatile memory apparatus, and semiconductor system and computer device using the same 有权
标题翻译：非易失性存储装置，半导体系统及使用其的计算机装置
公开(公告)号：US09263125B2
公开(公告)日：2016-02-16
申请号：US14091992
申请日：2013-11-27
申请人： SK hynix Inc.
发明人： Min Chul Shin , Yoon Jae Shin
IPC分类号： G11C7/06 , G11C13/00 , G11C5/14 , G11C7/08 , G11C11/56
CPC分类号： G11C13/004 , G11C5/143 , G11C5/147 , G11C7/06 , G11C7/08 , G11C11/56 , G11C2211/563
摘要： A nonvolatile memory apparatus includes a memory cell array including a plurality of sub arrays. A plurality of analog-to-digital converters (ADCs) configured to sense sensing voltages outputted from memory cells of the plurality of sub arrays and a path selection unit configured to electrically couple the plurality of sub arrays with the plurality of ADCs in one-to-one correspondence in a first operation mode, and electrically couple the plurality of ADCs with a terminal of a power supply voltage in a second operation mode.
摘要翻译：非易失性存储装置包括包括多个子阵列的存储单元阵列。多个模数转换器（ADC），被配置为感测从所述多个子阵列的存储器单元输出的感测电压;以及路径选择单元，被配置为将所述多个子阵列与所述多个ADC以一对一 - 在第一操作模式中的一个对应关系，并且在第二操作模式中将多个ADC与电源电压的端子电耦合。

5. 发明授权

US09196373B2 Timed multiplex sensing 有权
标题翻译：定时复用传感
公开(公告)号：US09196373B2
公开(公告)日：2015-11-24
申请号：US14191130
申请日：2014-02-26
申请人： SANDISK 3D LLC
发明人： Anurag Nigam , Gopinath Balakrishnan
IPC分类号： G11C13/00 , G11C16/26 , G11C16/04 , G11C11/56
CPC分类号： G11C7/08 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C16/0483 , G11C16/26 , G11C2211/563 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/75
摘要： Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.
摘要翻译：描述了使用检测方案来确定存储单元状态的方法，所述检测方案通过时间多路复用检测电路的部分来减少用于检测存储器单元的状态的检测电路的面积。读取操作可以包括预充电阶段，感测阶段和检测阶段。在一些实施例中，第一位线和第二位线可以并行地预充电到读取电压，然后可以串行地使用对应于第一位线和第二位线的所选存储单元的感测和/或检测相同的检测电路通过对检测电路的使用进行时间复用。在一些情况下，时间复用检测电路可以用于检测在读操作期间被感测到的两个或多个存储器单元相对应的两个或多个状态。

6. 发明申请

US20150243362A1 TIMED MULTIPLEX SENSING 有权
标题翻译：定时多传感器
公开(公告)号：US20150243362A1
公开(公告)日：2015-08-27
申请号：US14191130
申请日：2014-02-26
申请人： SANDISK 3D LLC
发明人： Anurag Nigam , Gopinath Balakrishnan
IPC分类号： G11C16/26 , G11C16/04
CPC分类号： G11C7/08 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C16/0483 , G11C16/26 , G11C2211/563 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/75
摘要： Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.
摘要翻译：描述了使用检测方案来确定存储单元状态的方法，所述检测方案通过时间多路复用检测电路的部分来减少用于检测存储器单元的状态的检测电路的面积。读取操作可以包括预充电阶段，感测阶段和检测阶段。在一些实施例中，第一位线和第二位线可以并行地预充电到读取电压，然后可以串行地使用对应于第一位线和第二位线的所选存储单元的感测和/或检测相同的检测电路通过对检测电路的使用进行时间复用。在一些情况下，时间复用检测电路可以用于检测在读操作期间被感测到的两个或多个存储器单元相对应的两个或多个状态。

7. 发明授权

US08811088B2 Method of reading memory cells with different threshold voltages without variation of word line voltage and nonvolatile memory device using the same 有权
标题翻译：使用不同字线电压的不同阈值电压读取存储单元的方法和使用其的非易失性存储器件
公开(公告)号：US08811088B2
公开(公告)日：2014-08-19
申请号：US13608030
申请日：2012-09-10
申请人： Sang-Hyun Joo , Kiwhan Song , Ju Seok Lee , Kihwan Choi
发明人： Sang-Hyun Joo , Kiwhan Song , Ju Seok Lee , Kihwan Choi
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C2211/563
摘要： A soft-decision read method of a nonvolatile memory device includes receiving a soft-decision read command, applying a read voltage to a selected word line, pre-charging bit lines respectively connected to selected memory cells of the selected word line, continuously sensing states of the selected memory cells. The pre-charged voltages of the bit lines and the read voltage supplied to the selected word line are not varied during the sensing states of the selected memory cells.
摘要翻译：非易失性存储器件的软判决读取方法包括：接收软判决读命令，将读电压施加到所选择的字线，对分别连接到所选字线的选定存储单元的位线进行预充电，连续检测状态的所选存储单元。提供给所选字线的位线的预充电电压和读取电压在所选存储单元的感测状态期间不改变。

8. 发明申请

US20130290813A1 Method and System For Error Correction in Flash Memory 有权
标题翻译：闪存中误差校正的方法和系统
公开(公告)号：US20130290813A1
公开(公告)日：2013-10-31
申请号：US13926514
申请日：2013-06-25
申请人： MARVELL WORLD TRADE LTD.
发明人： Aditya Ramamoorthy , Zining Wu , Pantas Sutardja
IPC分类号： G06F11/10
CPC分类号： G06F11/1068 , G06F11/1072 , G06F11/1666 , G06F2212/403 , G11C7/02 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C16/10 , G11C27/005 , G11C29/00 , G11C2029/0411 , G11C2207/16 , G11C2211/562 , G11C2211/563 , H03M13/1177 , H03M13/1515
摘要： A controller is described for a multi-level, solid state, non-volatile memory array having memory cells. The memory cells are configured to store data using a first number of digital levels. The controller is configured to encode multiple data bits to generate multiple encoded data bits, convert the multiple encoded data bits into multiple data symbols, and send the multiple data symbols for storage in a memory cell of the multi-level, solid state, non-volatile memory array. The controller is further configured to generate an output signal, using a second number of digital levels, based on data associated with the multiple data symbols stored in the memory cell. The second number of digital levels is greater than the first number of digital levels used to store the multiple data symbols in the memory cell. The controller is further configured to output multiple output data symbols based on the output signal.
摘要翻译：描述了一种具有存储单元的多级固态非易失性存储器阵列的控制器。存储器单元被配置为使用第一数字级别存储数据。控制器被配置为对多个数据位进行编码以产生多个编码数据位，将多个编码数据位转换为多个数据符号，并将多个数据符号发送以存储在多级固态，易失性存储器阵列。控制器还被配置为基于与存储在存储器单元中的多个数据符号相关联的数据，使用第二数量级别生成输出信号。数字电平的第二数量大于用于在存储器单元中存储多个数据符号的数字电平的第一数量。控制器还被配置为基于输出信号输出多个输出数据符号。

9. 发明授权

US07663086B2 Obtaining digital image of a scene with an imager moving relative to the scene 失效
标题翻译：用相机相对于场景移动的图像获取场景的数字图像
公开(公告)号：US07663086B2
公开(公告)日：2010-02-16
申请号：US12327533
申请日：2008-12-03
申请人： Rex K. Hales , Tracy Johancsik , Thomas L. Wolf
发明人： Rex K. Hales , Tracy Johancsik , Thomas L. Wolf
IPC分类号： H01L27/00
CPC分类号： H03K3/03 , G01J1/46 , G11C11/56 , G11C11/5642 , G11C2211/563 , G11C2211/5644
摘要： An imager acquires a scene's image by pixels each of which has a digital storage device which accumulates information on a pertinent portion of the image. During image acquisition, the imager moves relative to the scene, and the contents of the digital storage devices are shifted from one pixel to another. In some embodiments, less than all bits of a digital storage device are shifted, and/or the shift is accompanied by some operation on the contents of the digital storage devices. Other features are also provided.
摘要翻译：成像器通过像素获取场景的图像，每个像素具有在图像的相关部分上积累信息的数字存储装置。在图像采集期间，成像器相对于场景移动，数字存储设备的内容从一个像素移位到另一个像素。在一些实施例中，少于数字存储设备的所有位被移位，和/或移位伴随着对数字存储设备的内容的一些操作。还提供其他功能。

10. 发明申请

US20090084940A1 SENSING LIGHT AND SENSING THE STATE OF A MEMORY CELL 失效
公开(公告)号：US20090084940A1
公开(公告)日：2009-04-02
申请号：US12327533
申请日：2008-12-03
申请人： Rex K. Hales , Tracy Johancsik , Thomas L. Wolf
发明人： Rex K. Hales , Tracy Johancsik , Thomas L. Wolf
IPC分类号： H01L27/00 , H03K3/00
CPC分类号： H03K3/03 , G01J1/46 , G11C11/56 , G11C11/5642 , G11C2211/563 , G11C2211/5644
摘要： A light-to-frequency converter includes a switch (130) connected in series with a reverse-biased photodiode (120). A node (150) in the current path through the switch and the photodiode is connected to the input of a Schmidt trigger (160), whose output controls the switch. New techniques are provided for motion compensation, partial readouts, dark current elimination, non-destructive testing, and sensing the state of a memory cell.

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