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71. 发明申请

US20140070280A1 Active Area Shaping of III-Nitride Devices Utilizing Steps of Source-Side and Drain-Side Field Plates 有权
标题翻译：利用源侧和排水侧场板的三维氮化物器件的主动区域整形
公开(公告)号：US20140070280A1
公开(公告)日：2014-03-13
申请号：US14082007
申请日：2013-11-15
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L29/06 , H01L29/778
CPC分类号： H01L29/0688 , H01L21/28264 , H01L23/291 , H01L29/2003 , H01L29/402 , H01L29/42376 , H01L29/518 , H01L29/66462 , H01L29/778 , H01L29/7786 , H01L2924/0002 , H01L2924/00
摘要： In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas. The III-nitride semiconductor device further includes a gate well formed in a dielectric body, the dielectric body situated over the III-nitride heterojunction. A gate arrangement is situated in the gate well and includes a gate electrode, a source-side field plate, and a drain-side field plate. The source-side field plate and the drain-side field plate each include one or more steps, where the drain-side field plate has a different number of the one or more steps than the source-side field plate.
摘要翻译：在示例性实施方案中，III族氮化物半导体器件包括III族氮化物异质结，其包括位于第二III族氮化物体上方的第一III族氮化物体，以形成二维电子气。 III族氮化物半导体器件还包括形成在电介质体中的栅极阱，该电介质体位于III族氮化物异质结之上。栅极布置位于栅极阱中，并且包括栅电极，源极场板和漏极侧场板。源极场板和漏极侧场板各自包括一个或多个步骤，其中漏极侧场板具有与源极场板不同数量的一个或多个步骤。

72. 发明申请

US20140034959A1 III-Nitride Semiconductor Device with Stepped Gate 有权
标题翻译：带步进门的III型氮化物半导体器件
公开(公告)号：US20140034959A1
公开(公告)日：2014-02-06
申请号：US13965421
申请日：2013-08-13
申请人： International Rectifier Corporation
发明人： Michael A. Briere , Paul Bridger , Jianjun Cao
IPC分类号： H01L29/778 , H01L29/66
CPC分类号： H01L29/778 , H01L21/28264 , H01L23/291 , H01L23/3171 , H01L29/2003 , H01L29/42376 , H01L29/51 , H01L29/66431 , H01L29/66462 , H01L29/66477 , H01L29/7787 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same.
摘要翻译：一种III族氮化物异质结功率半导体器件及其制造方法，其包括具有栅极阱的钝化体，其具有比其底部口宽的顶部口。

73. 发明申请

US20140027778A1 Robust Fused Transistor 审中-公开
标题翻译：坚固的熔丝晶体管
公开(公告)号：US20140027778A1
公开(公告)日：2014-01-30
申请号：US13937173
申请日：2013-07-08
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L29/778 , H01L29/20
CPC分类号： H01L29/778 , H01L23/4824 , H01L23/5256 , H01L23/62 , H01L29/2003 , H01L29/41758 , H01L29/42316 , H01L29/4238 , H01L2924/0002 , H01L2924/00
摘要： According to an exemplary implementation, a transistor includes a plurality of drain fingers interdigitated with a plurality of source fingers. The transistor further includes a gate configured to control current conduction between the plurality of drain fingers and the plurality of source fingers. Additionally, the transistor includes a plurality of drain fuses, each being configured to electrically disconnect a drain finger of the plurality of drain fingers from remaining ones of the plurality of drain fingers. At least one of the plurality of drain fuses can electrically couple the drain finger to a common drain pad. The transistor may further include a plurality of source fuses, each being configured to electrically disconnect a source finger of the plurality of source fingers from remaining ones of the plurality of source fingers.
摘要翻译：根据示例性实施方式，晶体管包括与多个源极指相交叉的多个漏极指状物。晶体管还包括被配置为控制多个漏极指与多个源极之间的电流导通的栅极。另外，晶体管包括多个漏极保险丝，每个漏极熔丝被配置为使多个漏极指的漏极指状物与多个漏极指中的剩余引线电气断开。多个漏极熔丝中的至少一个可以将漏极电极电耦合到公共漏极焊盘。晶体管可以进一步包括多个源保险丝，每个源保险丝被配置为将多个源极指的源极手指与多个源极指中的剩余源极电气断开。

74. 发明申请

US20130334574A1 Monolithic Integrated Composite Group III-V and Group IV Device 有权
标题翻译：单片综合复合组III-V和IV组装置
公开(公告)号：US20130334574A1
公开(公告)日：2013-12-19
申请号：US13968840
申请日：2013-08-16
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L29/267
CPC分类号： H01L29/205 , H01L21/761 , H01L21/8252 , H01L27/0605 , H01L29/267
摘要： According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench.
摘要翻译：根据一个公开的实施例，一种用于制造单片集成复合器件的方法包括在IV族半导体衬底上形成III-V族半导体体，在III-V族半导体体中形成沟槽，并形成IV族半导体体在沟里。该方法还包括在IV族半导体本体中制造至少一种IV族半导体器件，并且在III-V族半导体器件中制造至少一种III-V族III族半导体器件。在一个实施例中，该方法还包括使III-V半导体体的上表面和IV族半导体本体的上表面平坦化，以使这些相应的上表面基本上共面。在一个实施例中，该方法还包括在与沟槽的侧壁相邻的所述IV族半导体主体的缺陷区域中制造至少一个无源器件。

75. 发明申请

US20130256694A1 Programmable Gate III-Nitride Semiconductor Device 有权
标题翻译：可编程门III-氮化物半导体器件
公开(公告)号：US20130256694A1
公开(公告)日：2013-10-03
申请号：US13906098
申请日：2013-05-30
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L29/778 , H01L29/66
CPC分类号： H01L29/778 , H01L29/2003 , H01L29/4232 , H01L29/42328 , H01L29/42336 , H01L29/51 , H01L29/513 , H01L29/518 , H01L29/66431 , H01L29/772 , H01L29/7787 , H01L29/803
摘要： A III-nitride semiconductor device which includes a charged gate insulation body.
摘要翻译：一种III族氮化物半导体器件，包括带电栅极绝缘体。

76. 发明申请

US20130240898A1 Group III-V and Group IV Composite Switch 有权
标题翻译： III-V组和IV组复合开关
公开(公告)号：US20130240898A1
公开(公告)日：2013-09-19
申请号：US13780436
申请日：2013-02-28
申请人： INTERNATIONAL RECTIFIER CORPORATION
发明人： Michael A. Briere , Tim McDonald
IPC分类号： H01L27/04 , H01L29/20
CPC分类号： H01L27/04 , H01L25/07 , H01L25/18 , H01L29/2003 , H01L2224/16 , H01L2924/13062 , H01L2924/13091 , H01L2924/00
摘要： In one implementation, a group III-V and group IV composite switch includes a group IV transistor in a lower active die, the group IV transistor having a source and a gate situated on a bottom side of the lower active die. The group III-V and group IV composite switch also includes a group III-V transistor in an upper active die stacked over the lower active die, the group III-V transistor having a drain, a source, and a gate situated on a top side of the upper active die. The source of the group III-V transistor is electrically coupled to a drain of the group IV transistor using a through-semiconductor via (TSV) of the upper active die.
摘要翻译：在一个实施方案中，III-V族和IV族复合开关包括在下有源管芯中的IV族晶体管，该IV族晶体管具有源极和位于下部有源裸片底部的栅极。 III-V族和IV族复合开关还包括在下部有源裸片上堆叠的上部有源管芯中的III-V族晶体管，具有位于顶部的漏极，源极和栅极的III-V晶体管上活动模具的一侧。使用上部有源管芯的贯通半导体通孔（TSV）将III-V族晶体管的源极电耦合到IV族晶体管的漏极。

77. 发明授权

US09379231B2 Transistor having increased breakdown voltage 有权
标题翻译：晶体管具有增加的击穿电压
公开(公告)号：US09379231B2
公开(公告)日：2016-06-28
申请号：US13749477
申请日：2013-01-24
申请人： International Rectifier Corporation
发明人： Michael A. Briere , Naresh Thapar , Reenu Garg
IPC分类号： H01L29/778 , H01L29/417 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7788 , H01L29/41758 , H01L29/42316 , H01L29/7787 , H01L29/78
摘要： A transistor includes a source finger electrode having a source finger electrode beginning and a source finger electrode end. The transistor also includes a drain finger electrode with a curved drain finger electrode end having an increased radius of curvature. The resulting decreased electric field at the curved drain finger electrode end allows for an increased breakdown voltage and a more robust and reliable transistor.
摘要翻译：晶体管包括具有源极指电极开始的源极指电极和源极指电极端。晶体管还包括具有弯曲的漏极指状电极端的漏极指电极，其具有增加的曲率半径。在弯曲的漏极指状电极端处产生的减小的电场允许增加的击穿电压和更坚固和可靠的晶体管。

78. 发明授权

US09312374B2 Integrated power device with III-nitride half bridges 有权
标题翻译：具有III族氮化物半桥的集成功率器件
公开(公告)号：US09312374B2
公开(公告)日：2016-04-12
申请号：US14222332
申请日：2014-03-21
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L29/66 , H01L29/778 , H01L27/06 , H01L29/20 , H01L29/205
CPC分类号： H01L29/7787 , H01L27/0605 , H01L29/2003 , H01L29/205 , H01L29/41758 , H01L29/778
摘要： A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die.
摘要翻译：一种半导体器件，包括形成在公共半导体管芯中的多个隔离半桥。

79. 发明授权

US09281387B2 High voltage durability III-nitride device 有权
标题翻译：高耐压III族氮化物器件
公开(公告)号：US09281387B2
公开(公告)日：2016-03-08
申请号：US14459726
申请日：2014-08-14
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L29/778 , H01L29/04 , H01L29/20 , H01L29/66
CPC分类号： H01L29/778 , H01L21/8258 , H01L29/045 , H01L29/2003 , H01L29/66462 , H01L29/7786 , H01L29/7787
摘要： A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a silicon layer, an insulator layer over the silicon layer, and a P type conductivity silicon layer over the insulator layer. The high voltage durability HEMT also comprises a III-nitride semiconductor body formed over the P type conductivity silicon layer, the III-nitride semiconductor body forming a heterojunction of the HEMT.
摘要翻译：高耐压III族氮化物半导体器件包括：支撑衬底，其包括第一硅体，位于第一硅体上的绝缘体，以及位于绝缘体上方的第二硅体。高电压耐久性III族氮化物半导体器件还包括在第二硅体上形成的以多数电荷载流子导电型为特征的III族氮化物半导体体。第二硅体具有与多数电荷载流子导电类型相反的导电类型。在一个实施例中，高电压耐久性III族氮化物半导体器件是高电子迁移率晶体管（HEMT），其包含支撑衬底，该支撑衬底包括<100>硅层，在<100>硅层上的绝缘体层，以及P型导电性 <111>硅层。高电压耐久性HEMT还包括在P型导电性<111>硅层上形成的III族氮化物半导体体，III族氮化物半导体体形成HEMT的异质结。

80. 发明授权

US09202811B2 Cascode circuit integration of group III-N and group IV devices 有权
标题翻译： III-N组和IV组器件的串联电路集成
公开(公告)号：US09202811B2
公开(公告)日：2015-12-01
申请号：US14073783
申请日：2013-11-06
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L25/10 , H01L27/088 , H01L25/18 , H01L21/8258
CPC分类号： H01L27/0883 , H01L21/8258 , H01L25/105 , H01L25/18 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： In an exemplary implementation, an integrated assembly includes a printed circuit board, and a depletion mode III-Nitride transistor die and a group IV transistor die coupled to the printed circuit board. The depletion mode III-Nitride transistor die is situated on one side of the printed circuit board and the group IV transistor die is situated on an opposing side of the printed circuit board. At least one via in the printed circuit board electrically connects the depletion mode III-Nitride transistor die to the group IV transistor die. In some implementations, the depletion mode III-Nitride transistor die is in cascode with the group IV transistor die. Furthermore, the depletion mode III-Nitride transistor die can be situated over the group IV transistor die.
摘要翻译：在示例性实施方案中，集成组件包括印刷电路板和耗尽型III氮化物晶体管管芯和耦合到印刷电路板的IV族晶体管管芯。耗尽型III型氮化物晶体管管芯位于印刷电路板的一侧，而IV族晶体管管芯位于印刷电路板的相对侧上。印刷电路板中的至少一个通孔将耗尽型III型氮化物晶体管管芯与第IV族晶体管管芯电连接。在一些实施方案中，耗尽型III型氮化物晶体管管芯与IV族晶体管管芯共级共栅。此外，耗尽型III型氮化物晶体管管芯可以位于IV族晶体管管芯之上。

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