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1. 发明授权

US08729644B2 Programmable III-nitride semiconductor device 有权
标题翻译：可编程III族氮化物半导体器件
公开(公告)号：US08729644B2
公开(公告)日：2014-05-20
申请号：US13906098
申请日：2013-05-30
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L21/02
CPC分类号： H01L29/778 , H01L29/2003 , H01L29/4232 , H01L29/42328 , H01L29/42336 , H01L29/51 , H01L29/513 , H01L29/518 , H01L29/66431 , H01L29/772 , H01L29/7787 , H01L29/803
摘要： A III-nitride semiconductor device which includes a charged gate insulation body.
摘要翻译：一种III族氮化物半导体器件，包括带电栅极绝缘体。

2. 发明授权

US08482035B2 Enhancement mode III-nitride transistors with single gate Dielectric structure 有权
标题翻译：具有单栅极电介质结构的增强型III族氮化物晶体管
公开(公告)号：US08482035B2
公开(公告)日：2013-07-09
申请号：US13017970
申请日：2011-01-31
申请人： Michael A. Briere
发明人： Michael A. Briere
IPC分类号： H01L21/8232 , H01L29/778
CPC分类号： H01L29/7783 , H01L21/02063 , H01L21/76814 , H01L29/2003 , H01L29/205 , H01L29/4232 , H01L29/51 , H01L29/518 , H01L29/66431 , H01L29/66462 , H01L29/778 , H01L29/7787 , H01L29/803
摘要： According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge.
摘要翻译：根据一个实施例，III族氮化物晶体管包括在第一和第二III族氮化物体之间形成的导电通道，该导电通道包括二维电子气。所述晶体管还包括至少一个具有限制在其中的电荷的栅介质层，以引起导通通道的中断区域，以及可操作以恢复导通通道的中断区域的栅电极。晶体管可以是增强型晶体管。在一个实施例中，栅介质层是氮化硅层。在另一个实施例中，至少一个栅介质层是氧化硅层。电荷可以离子注入到至少一个栅极电介质层中。至少一个栅介电层也可以与电荷一起生长。

3. 发明授权

US08331142B2 Memory 有权
标题翻译：记忆
公开(公告)号：US08331142B2
公开(公告)日：2012-12-11
申请号：US12970744
申请日：2010-12-16
申请人： Dieter Bimberg , Martin Geller , Andreas Marent , Tobias Nowozin
发明人： Dieter Bimberg , Martin Geller , Andreas Marent , Tobias Nowozin
IPC分类号： G11C11/34 , H01L29/68
CPC分类号： B82Y10/00 , H01L29/66825 , H01L29/788 , H01L29/803
摘要： An embodiment of the invention relates to a memory comprising a strained double-heterostructure having an inner semiconductor layer which is sandwiched between two outer semiconductor layers, wherein the lattice constant of the inner semiconductor layer differs from the lattice constants of the outer semiconductor layers, the resulting lattice strain in the double-heterostructure inducing the formation of at least one quantum dot inside the inner semiconductor layer, said at least one quantum dot being capable of storing charge carriers therein, and wherein, due to the lattice strain, the at least one quantum dot has an emission barrier of 1.15 eV or higher, and provides an energy state density of at least three energy states per 1000 nm3, all said at least three energy states being located in an energy band of 50 meV or less.
摘要翻译：本发明的一个实施例涉及包含应变双异质结构的存储器，其具有夹在两个外半导体层之间的内半导体层，其中内半导体层的晶格常数与外半导体层的晶格常数不同，所述双异质结构中的晶格应变导致在所述内半导体层内部形成至少一个量子点，所述至少一个量子点能够在其中存储电荷载流子，并且其中由于晶格应变，所述至少一个量子点具有1.15eV或更高的发射势垒，并且提供每1000nm 3至少三个能量状态的能态状态密度，所有所述至少三个能态位于50meV或更小的能带内。

4. 发明申请

US20120091470A1 Programmable Gate III-Nitride Power Transistor 有权
标题翻译：可编程门III-氮化物功率晶体管
公开(公告)号：US20120091470A1
公开(公告)日：2012-04-19
申请号：US13334720
申请日：2011-12-22
申请人： Michael A. Briere
发明人： Michael A. Briere
IPC分类号： H01L29/161 , H01L21/20 , H01L29/20
CPC分类号： H01L29/778 , H01L29/2003 , H01L29/4232 , H01L29/42328 , H01L29/42336 , H01L29/51 , H01L29/513 , H01L29/518 , H01L29/66431 , H01L29/772 , H01L29/7787 , H01L29/803
摘要： A III-nitride semiconductor device which includes a charged floating gate electrode.
摘要翻译：一种III族氮化物半导体器件，其包括带电的浮置栅电极。

5. 发明授权

US5055890A Nonvolatile semiconductor memory having three dimension charge confinement 失效
标题翻译：具有三维电荷限制的非易失性半导体存储器
公开(公告)号：US5055890A
公开(公告)日：1991-10-08
申请号：US469995
申请日：1990-01-25
申请人： L. Ralph Dawson , Gordon C. Osbourn , Paul S. Peercy , Harry T. Weaver , Thomas E. Zipperian
发明人： L. Ralph Dawson , Gordon C. Osbourn , Paul S. Peercy , Harry T. Weaver , Thomas E. Zipperian
IPC分类号： H01L29/80 , H01L29/812
CPC分类号： H01L29/812 , H01L29/803
摘要： A layered semiconductor device with a nonvolatile three dimensional memory comprises a storage channel which stores charge carriers. Charge carriers flow laterally through the storage channel from a source to a drain. Isolation material, either a Schottky barrier or a heterojunction, located in a trench of an upper layer controllably retains the charge within the a storage portion determined by the confining means. The charge is retained for a time determined by the isolation materials' nonvolatile characteristics or until a change of voltage on the isolation material and the source and drain permit a read operation. Flow of charge through an underlying sense channel is affected by the presence of charge within the storage channel, thus the presences of charge in the memory can be easily detected.
摘要翻译：具有非易失性三维存储器的分层半导体器件包括存储电荷载体的存储通道。电荷载体横向流过存储通道从源极到漏极。位于上层的沟槽中的隔离材料，肖特基势垒或异质结可控地将电荷保持在由限制装置确定的存储部分内。电荷被保持一段时间，由隔离材料的非易失性特性决定，或直到隔离材料和源极和漏极上的电压变化才允许读取操作。通过底层感测通道的电荷流动受存储通道内的电荷的存在的影响，因此可以容易地检测存储器中的电荷的存在。

6. 发明授权

US09236462B2 Programmable gate III-nitride power transistor 有权
标题翻译：可编程门III-氮化物功率晶体管
公开(公告)号：US09236462B2
公开(公告)日：2016-01-12
申请号：US13334720
申请日：2011-12-22
申请人： Michael A. Briere
发明人： Michael A. Briere
IPC分类号： H01L29/778 , H01L29/66 , H01L29/80 , H01L29/423 , H01L29/772 , H01L29/20 , H01L29/51
CPC分类号： H01L29/778 , H01L29/2003 , H01L29/4232 , H01L29/42328 , H01L29/42336 , H01L29/51 , H01L29/513 , H01L29/518 , H01L29/66431 , H01L29/772 , H01L29/7787 , H01L29/803
摘要： A III-nitride semiconductor device which includes a charged floating gate electrode.
摘要翻译：一种III族氮化物半导体器件，其包括带电的浮置栅电极。

7. 发明授权

US08120071B2 MEMFET RAM 有权
公开(公告)号：US08120071B2
公开(公告)日：2012-02-21
申请号：US12685494
申请日：2010-01-11
申请人： Alexandre M. Bratkovski , R. Stanley Williams
发明人： Alexandre M. Bratkovski , R. Stanley Williams
IPC分类号： H01L29/80 , H01L31/112 , H01L29/792
CPC分类号： H01L27/101 , H01L29/803
摘要： A non-volatile field-effect device. The non-volatile field-effect device includes a source, a drain, a channel-formation portion and a memristive gate. The channel-formation portion is disposed between and coupled with the source and the drain. The memristive gate is disposed over the channel-formation portion and coupled with the channel-formation portion. The memristive gate includes a plurality of mobile ions and a confinement structure for the plurality of mobile ions. Moreover, the memristive gate is configured to switch the channel-formation portion from a first conductivity state to a second conductivity state in response to migration of the plurality of mobile ions within the confinement structure.
摘要翻译：非易失性场效应器件。非易失性场效应器件包括源极，漏极，沟道形成部分和忆阻栅极。通道形成部分设置在源极和漏极之间并与源极耦合。忆阻门设置在通道形成部分上方并与通道形成部分联接。忆阻门包括多个移动离子和多个移动离子的约束结构。此外，忆阻门被配置为响应于限制结构内的多个移动离子的迁移，将沟道形成部分从第一导电状态切换到第二导电状态。

8. 发明申请

US20110169052A1 MEMFET RAM 有权
公开(公告)号：US20110169052A1
公开(公告)日：2011-07-14
申请号：US12685494
申请日：2010-01-11
申请人： Alexandre M. Bratkovski , R. Stanley Williams
发明人： Alexandre M. Bratkovski , R. Stanley Williams
IPC分类号： H01L27/085 , H01L29/80
CPC分类号： H01L27/101 , H01L29/803
摘要： A non-volatile field-effect device. The non-volatile field-effect device includes a source, a drain, a channel-formation portion and a memristive gate. The channel-formation portion is disposed between and coupled with the source and the drain. The memristive gate is disposed over the channel-formation portion and coupled with the channel-formation portion. The memristive gate includes a plurality of mobile ions and a confinement structure for the plurality of mobile ions. Moreover, the memristive gate is configured to switch the channel-formation portion from a first conductivity state to a second conductivity state in response to migration of the plurality of mobile ions within the confinement structure.
摘要翻译：非易失性场效应器件。非易失性场效应器件包括源极，漏极，沟道形成部分和忆阻栅极。通道形成部分设置在源极和漏极之间并与源极耦合。忆阻门设置在通道形成部分上方并与通道形成部分联接。忆阻门包括多个移动离子和多个移动离子的约束结构。此外，忆阻门被配置为响应于限制结构内的多个移动离子的迁移，将沟道形成部分从第一导电状态切换到第二导电状态。

9. 发明申请

US20110121313A1 Enhancement Mode III-Nitride Transistors with Single Gate Dielectric Structure 有权
标题翻译：具有单栅介质结构的增强型III型氮化物晶体管
公开(公告)号：US20110121313A1
公开(公告)日：2011-05-26
申请号：US13017970
申请日：2011-01-31
申请人： Michael A. Briere
发明人： Michael A. Briere
IPC分类号： H01L29/778 , H01L29/20
CPC分类号： H01L29/7783 , H01L21/02063 , H01L21/76814 , H01L29/2003 , H01L29/205 , H01L29/4232 , H01L29/51 , H01L29/518 , H01L29/66431 , H01L29/66462 , H01L29/778 , H01L29/7787 , H01L29/803
摘要： According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge.
摘要翻译：根据一个实施例，III族氮化物晶体管包括在第一和第二III族氮化物体之间形成的导电通道，该导电通道包括二维电子气。所述晶体管还包括至少一个具有限制在其中的电荷的栅介质层，以引起导通通道的中断区域，以及可操作以恢复导通通道的中断区域的栅电极。晶体管可以是增强型晶体管。在一个实施例中，栅介质层是氮化硅层。在另一个实施例中，至少一个栅介质层是氧化硅层。电荷可以离子注入到至少一个栅极电介质层中。至少一个栅介电层也可以与电荷一起生长。

10. 发明授权

US06459120B1 Semiconductor device and manufacturing method of the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US06459120B1
公开(公告)日：2002-10-01
申请号：US09635691
申请日：2000-08-10
申请人： Masashi Shima
发明人： Masashi Shima
IPC分类号： H01L29788
CPC分类号： B82Y10/00 , H01L21/30617 , H01L29/122 , H01L29/127 , H01L29/803
摘要： A regular tetrahedral groove is formed in a wafer, and a memory unit is formed, which includes a channel layer as a first semiconductor layer to serve as a channel, a three-layer structure floating layer as a second semiconductor layer to serve as a floating gate, and an electrode contact layer as a third semiconductor layer to secure drain contact. The floating layer is formed into a three-layer structure of a p-AlGaAs layer, an i-InGaAs layer and a p-AlGaAs layer. It is possible to provide a semiconductor device capable of securing its sufficient functionality at a room temperature by using a quantum dot structure, and achieving an ultimate high-density integration with high reliability. Also provided is a method capable of easily manufacturing semiconductor devices having such a construction.
摘要翻译：在晶片中形成规则的四面体沟槽，并且形成存储单元，该存储单元包括沟道层作为用作沟道的第一半导体层，作为第二半导体层的三层结构浮动层用作浮置栅极和电极接触层作为第三半导体层以确保漏极接触。浮置层形成为p-AlGaAs层，i-InGaAs层和p-AlGaAs层的三层结构。可以提供能够通过使用量子点结构在室温下确保其足够的功能性的半导体器件，并且以高可靠性实现最终的高密度集成。还提供了能够容易地制造具有这种结构的半导体器件的方法。

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