专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20210028308A1 MEMORY ARRAYS WITH VERTICAL TRANSISTORS AND THE FORMATION THEREOF 有权
公开(公告)号：US20210028308A1
公开(公告)日：2021-01-28
申请号：US16522390
申请日：2019-07-25
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege , Steve V. Cole , Scott J. Derner , Toby D. Robbs
IPC分类号： H01L29/78 , H01L29/66 , H01L27/108 , H01L27/11587 , G11C11/22 , G11C11/4091
摘要： An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.

72. 发明申请

US20210013305A1 CHANNEL CONDUCTION IN SEMICONDUCTOR DEVICES 有权
公开(公告)号：US20210013305A1
公开(公告)日：2021-01-14
申请号：US16509093
申请日：2019-07-11
申请人： Micron Technology, Inc.
发明人： Kamal M. Karda , Haitao Liu , Si-Woo Lee , Fatma Arzum Simsek-Ege , Deepak Chandra Pandey , Chandra V. Mouli , John A. Smythe, III
IPC分类号： H01L29/06 , H01L27/108 , H01L21/762
摘要： An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

73. 发明授权

US10515972B2 Memory cell pillar including source junction plug 有权
公开(公告)号：US10515972B2
公开(公告)日：2019-12-24
申请号：US15685878
申请日：2017-08-24
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege , Krishna K. Parat , Luan C. Tran , Meng-Wei Kuo , Yushi Hu
IPC分类号： H01L27/11524 , H01L27/1157 , H01L27/11582 , H01L27/11556 , H01L21/822 , H01L27/11578 , H01L27/11529 , H01L27/1158
摘要： Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

74. 发明申请

US20190267379A1 Memory Cells and Memory Arrays 审中-公开
公开(公告)号：US20190267379A1
公开(公告)日：2019-08-29
申请号：US16412750
申请日：2019-05-15
申请人： Micron Technology, Inc.
发明人： Suraj J. Mathew , Kris K. Brown , Raghunath Singanamalla , Vinay Nair , Fawad Ahmed , Fatma Arzum Simsek-Ege , Diem Thy N. Tran
IPC分类号： H01L27/108 , H01L29/94 , H01L27/06 , H01L49/02 , H01L27/02 , H01L29/10 , H01L29/78
摘要： Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

75. 发明申请

US20190081071A1 Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells 审中-公开
公开(公告)号：US20190081071A1
公开(公告)日：2019-03-14
申请号：US16184907
申请日：2018-11-08
申请人： Micron Technology, Inc.
发明人： Jie Sun , Fatma Arzum Simsek-Ege
IPC分类号： H01L27/11582 , H01L27/115 , H01L21/02 , H01L21/768 , H01L23/522 , H01L23/528 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L21/28 , H01L23/532
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/0217 , H01L21/02244 , H01L21/02274 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/53271 , H01L27/115 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/40114 , H01L29/40117
摘要： Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

76. 发明授权

US10153298B2 Integrated structures and methods of forming vertically-stacked memory cells 有权
公开(公告)号：US10153298B2
公开(公告)日：2018-12-11
申请号：US15893380
申请日：2018-02-09
申请人： Micron Technology, Inc.
发明人： Jie Sun , Fatma Arzum Simsek-Ege
IPC分类号： H01L23/00 , H01L27/11582 , H01L27/115 , H01L21/02 , H01L21/28 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532
摘要： Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

77. 发明授权

US10056386B2 Memory cells and memory arrays 有权
公开(公告)号：US10056386B2
公开(公告)日：2018-08-21
申请号：US15664217
申请日：2017-07-31
申请人： Micron Technology, Inc.
发明人： Suraj J. Mathew , Kris K. Brown , Raghunath Singanamalla , Vinay Nair , Fawad Ahmed , Fatma Arzum Simsek-Ege , Diem Thy N. Tran
IPC分类号： H01L27/108 , H01L27/06 , H01L29/78 , H01L29/10 , H01L49/02 , H01L27/02 , H01L29/08 , H01L23/528
CPC分类号： H01L27/108 , H01L23/528 , H01L27/0207 , H01L27/0688 , H01L27/10841 , H01L27/10864 , H01L28/60 , H01L29/0847 , H01L29/1037 , H01L29/7827 , H01L29/945
摘要： Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

78. 发明申请

US20180061835A1 Memory Cells and Memory Arrays 审中-公开
公开(公告)号：US20180061835A1
公开(公告)日：2018-03-01
申请号：US15664161
申请日：2017-07-31
申请人： Micron Technology, Inc.
发明人： Gloria Yang , Suraj J. Mathew , Raghunath Singanamalla , Vinay Nair , Scott J. Derner , Michael Amiel Shore , Brent Keeth , Fatma Arzum Simsek-Ege , Diem Thy N. Tran
IPC分类号： H01L27/108 , H01L27/06 , H01L29/423 , H01L49/02 , H01L29/78
CPC分类号： H01L27/108 , G11C11/403 , H01L23/528 , H01L27/0688 , H01L28/90 , H01L29/0847 , H01L29/1037 , H01L29/42376 , H01L29/7827
摘要： Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

79. 发明授权

US09793282B2 Floating gate memory cells in vertical memory 有权
公开(公告)号：US09793282B2
公开(公告)日：2017-10-17
申请号：US14925589
申请日：2015-10-28
申请人： Micron Technology, Inc.
发明人： Charles H. Dennison , Akira Goda , John Hopkins , Fatma Arzum Simsek-Ege , Krishna K. Parat
IPC分类号： H01L27/11556 , H01L29/66 , H01L27/11578 , H01L21/28
CPC分类号： H01L27/11556 , H01L21/28273 , H01L27/11578 , H01L29/66666 , H01L29/66825 , H01L29/66833
摘要： Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

80. 发明申请

US20160293623A1 Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells 审中-公开
标题翻译：形成垂直堆叠记忆单元的综合结构和方法
公开(公告)号：US20160293623A1
公开(公告)日：2016-10-06
申请号：US14679926
申请日：2015-04-06
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege , Meng-Wei Kuo , John D. Hopkins
IPC分类号： H01L27/115 , H01L29/423 , H01L21/3213 , H01L21/02 , H01L21/28 , H01L21/311
摘要： Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels. Regions of the insulative levels remain as ledges which separate adjacent cavities from one another. Material is removed from the ledges to thin the ledges, and then charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative levels and conductive levels. Cavities extend into the conductive levels. Ledges of the insulative levels separate adjacent cavities from one another. The ledges are thinned relative to regions of the insulative levels not encompassed by the ledges. Charge-blocking dielectric and charge-storage structures are within the cavities.
摘要翻译：一些实施例包括形成垂直堆叠的存储单元的方法。通过交替的绝缘和导电水平的叠层形成开口。空穴形成为延伸到导电水平。绝缘水平的区域保持为将相邻腔彼此分开的壁架。将材料从凸缘上移除以使突出部分变薄，然后在腔内形成电荷阻挡电介质和电荷存储结构。一些实施例包括具有交替绝缘水平和导电水平的叠层的集成结构。穴位扩展到导电水平。绝缘层的楔形物将相邻的空腔彼此分开。相对于不包括在突出部分的绝缘水平的区域，这些壁架变薄。电荷阻挡电介质和电荷存储结构在空腔内。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式