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71. 发明授权

US06852302B1 Carbon monoxide removing apparatus and process for operating the same 失效
标题翻译：一氧化碳去除装置及其操作方法
公开(公告)号：US06852302B1
公开(公告)日：2005-02-08
申请号：US10130760
申请日：2000-11-16
申请人： Kunihiro Ukai , Takeshi Tomizawa , Kiyoshi Taguchi , Akira Maenishi , Tetsuya Ueda
发明人： Kunihiro Ukai , Takeshi Tomizawa , Kiyoshi Taguchi , Akira Maenishi , Tetsuya Ueda
IPC分类号： B01J8/02 , C01B3/32 , C01B3/38 , C01B3/58 , C10K3/04 , H01M8/04 , H01M8/06 , C01B31/20
CPC分类号： B01J8/025 , B01J8/0278 , B01J2208/00061 , B01J2208/00415 , B01J2208/00548 , C01B3/583 , C01B2203/00 , C01B2203/0233 , C01B2203/044 , C01B2203/047 , C01B2203/066 , C01B2203/0877 , C01B2203/107 , C01B2203/16 , C01B2203/1609 , C01B2203/1619 , C01B2203/1623 , C10K3/04 , H01M8/0662
摘要： An apparatus of removing carbon monoxide, has: a hydrogen gas supply unit of supplying a hydrogen gas, a catalytic reaction unit provided with a catalyst body carrying a platinum group metal catalyst, a hydrogen gas introducing unit which introduces a hydrogen gas containing carbon monoxide from the hydrogen gas supply unit to the catalytic reaction unit, and an oxidizing gas supply unit of supplying an oxidizing gas containing oxygen to the catalytic reaction unit, wherein the catalyst body is brought into an oxidizing atmosphere for a period of time during operation according to a predetermined condition or when the apparatus is stopped. Thus, carbon monoxide can be eliminated sufficiently.
摘要翻译：一种除去一氧化碳的装置具有：供给氢气的氢气供给单元，具备载有铂族金属催化剂的催化剂体的催化反应单元，将含有一氧化碳的氢气从氢气导入单元所述催化剂反应单元的氢气供给单元和向所述催化反应单元供给氧的氧化气体的氧化气体供给单元，所述催化剂体在所述催化剂反应单元的运转期间，在预定条件下进入氧化气氛中一段时间或者当设备停止时。因此，可以充分消除一氧化碳。

72. 发明授权

US06759322B2 Method for forming wiring structure 有权
标题翻译：形成布线结构的方法
公开(公告)号：US06759322B2
公开(公告)日：2004-07-06
申请号：US10328171
申请日：2002-12-26
申请人： Hideaki Yoshida , Tetsuya Ueda , Masashi Hamanaka , Takeshi Harada
发明人： Hideaki Yoshida , Tetsuya Ueda , Masashi Hamanaka , Takeshi Harada
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/02074 , H01L21/31053 , H01L21/31144 , H01L21/3212 , H01L21/76807 , H01L21/7684 , Y10S438/906 , Y10S438/952 , Y10S438/959
摘要： After a plurality of grooves are formed in an insulating film and in an anti-reflection film on the insulating film, a barrier metal film and a conductive film are deposited on the anti-reflection film such that each of the wiring grooves is filled therewith. Subsequently, the portions of the conductive film outside the grooves are removed by polishing and then the portions of the barrier metal film outside the wiring are removed by polishing. Thereafter, a foreign matter adhered to a surface to be polished during polishing is removed and then a surface of the anti-reflection film is polished.
摘要翻译：在绝缘膜和绝缘膜上的抗反射膜中形成多个沟槽之后，在防反射膜上沉积阻挡金属膜和导电膜，使得每个布线槽被填充。随后，通过研磨去除沟槽外部的导电膜的部分，然后通过抛光除去布线外部的阻挡金属膜的部分。此后，除去在抛光期间附着于抛光表面的异物，然后抛光抗反射膜的表面。

73. 发明授权

US06252427B1 CMOS inverter and standard cell using the same 有权
标题翻译： CMOS反相器和标准电池使用相同
公开(公告)号：US06252427B1
公开(公告)日：2001-06-26
申请号：US09333048
申请日：1999-06-15
申请人： Shinichi Domae , Tetsuya Ueda
发明人： Shinichi Domae , Tetsuya Ueda
IPC分类号： H03K1920
CPC分类号： H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： To prevent a void from being formed in a CMOS inverter due to electromigration. A power line 11 is connected to the source of a p-channel MOS transistor Tr1 via a first contact 12. A ground line 13 is connected to the source of an n-channel MOS transistor Tr2 via a second contact 14. One terminal of a first output signal line 15 is connected to the drain of the p-channel MOS transistor Tr1 via a third contact 16, while the other terminal thereof is connected to the drain of the n-channel MOS transistor Tr2 via a fourth contact 17. one terminal of a second output signal line 18 is connected to the fourth contact 17, while the other terminal thereof extends toward the output terminal of the inverter. A first path of an input signal line 19 is connected to the gate electrode 20 of the p-channel MOS transistor Tr1 via a fifth contact 21, while a second path thereof is connected to the gate electrode 20 of the n-channel MOS transistor Tr2 via a sixth contact 22.
摘要翻译：为了防止由于电迁移而在CMOS反相器中形成空隙。电源线11经由第一触点12连接到p沟道MOS晶体管Tr1的源极。地线13连接到n的源极通道MOS晶体管Tr2经由第二触点14.第一输出信号线15的一个端子经由第三触点16连接到p沟道MOS晶体管Tr1的漏极，而另一端连接到 n沟道MOS晶体管Tr2经由第四触点17.第二输出信号线18的一个端子连接到第四触点17，而另一端延伸到逆变器的输出端。输入信号线19的第一路径经由第五接点21连接到p沟道MOS晶体管Tr1的栅电极20，其第二路径连接到n沟道MOS晶体管Tr2的栅电极20 经由第六接触件22。

74. 发明授权

US5969426A Substrateless resin encapsulated semiconductor device 失效
标题翻译：无脊椎树脂封装的半导体器件
公开(公告)号：US5969426A
公开(公告)日：1999-10-19
申请号：US571604
申请日：1995-12-13
申请人： Shinji Baba , Jun Shibata , Tetsuya Ueda
发明人： Shinji Baba , Jun Shibata , Tetsuya Ueda
IPC分类号： H01L21/60 , H01L21/56 , H01L21/68 , H01L23/12 , H01L23/31 , H01L23/433 , H01L23/498 , H01L23/28 , H01L23/48
CPC分类号： H01L21/568 , H01L23/3128 , H01L23/4334 , H01L23/49816 , H01L24/16 , H01L2221/68345 , H01L2224/11003 , H01L2224/1147 , H01L2224/13023 , H01L2224/13099 , H01L2224/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/32225 , H01L2224/32245 , H01L2224/451 , H01L2224/48227 , H01L2224/48465 , H01L2224/73204 , H01L2224/73253 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/351
摘要： A semiconductor device includes an encapsulating resin encapsulating a semiconductor substrate, a lead pattern or a laminated wiring layers transferred or secured on the lower surface of the encapsulating resin and a plurality of external electrode disposed on the lower surface of the lead pattern. The device may be manufactured by bonding a semiconductor substrate on a transferring substrate to which a lead pattern is formed, resin encapsulating an upper portion of the transferring substrate to cover the semiconductor substrate, and removing only the transferring substrate with the lead pattern left bonded to the encapsulating resin and the semiconductor substrate.
摘要翻译：半导体器件包括封装半导体衬底的封装树脂，引线图案或被转移或固定在封装树脂的下表面上的层叠布线层和设置在引线图案的下表面上的多个外部电极。该器件可以通过将半导体衬底接合到其上形成引线图案的转印衬底上，将封装转印衬底的上部的树脂覆盖半导体衬底，并且仅将转印衬底除去，并将引线图案留下封装树脂和半导体衬底。

75. 发明授权

US5508232A Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5508232A
公开(公告)日：1996-04-16
申请号：US386808
申请日：1995-02-06
申请人： Tetsuya Ueda , Kazunari Michii , Yutaka Koyama , Naoto Ueda
发明人： Tetsuya Ueda , Kazunari Michii , Yutaka Koyama , Naoto Ueda
IPC分类号： H01L21/60 , H01L21/56 , H01L23/495 , H01L23/50
CPC分类号： H01L21/565 , H01L23/49537 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01068 , H01L2924/01079 , H01L2924/14 , Y10T29/49121
摘要： In a method of manufacturing a semiconductor device, overlaid on a first lead frame including a die pad supported by a plurality of die pad suspending leads is a second lead frame having connecting leads wherein the first and second lead frames are disposed on a first molding die such that the die pad and inner lead portions of the inner leads of the second lead frame are accommodated within a first cavity of the first molding die while offset portions of the die pad suspending leads are disposed outside of the first cavity. A second molding die is clamped onto the first molding die to define a resin molding chamber which is then filled with a molten resin to form a package. After removing the package from the first and second molding dies, the offset portions are cut away from the package while cutting the connecting leads to a predetermined length. A semiconductor chip as large as permissible can be embedded within a semiconductor device of a standard size while ensuring high quality and improved reliability of the semiconductor device.
摘要翻译：在制造半导体器件的方法中，覆盖在包括由多个管芯焊盘悬挂引线支撑的管芯焊盘的第一引线框架上的是具有连接引线的第二引线框架，其中第一引线框架和第二引线框架设置在第一成型模具使得第二引线框架的内引线的管芯焊盘和内引线部分容纳在第一成型模具的第一腔内，同时将芯片垫悬挂引线的偏移部分设置在第一腔体的外部。将第二成型模具夹在第一模具上以限定树脂模制室，然后用熔融树脂填充以形成包装。在从第一和第二模具中取出包装之后，将连接引线切割成预定长度，将偏移部分从包装中切出。可以将尺寸大的半导体芯片嵌入到标准尺寸的半导体器件中，同时确保半导体器件的高品质和可靠性。

76. 发明授权

US5334872A Encapsulated semiconductor device having a hanging heat spreading plate electrically insulated from the die pad 失效
标题翻译：封装半导体器件具有与管芯焊盘电绝缘的悬挂散热板
公开(公告)号：US5334872A
公开(公告)日：1994-08-02
申请号：US62567
申请日：1993-05-18
申请人： Tetsuya Ueda , Osamu Nakagawa
发明人： Tetsuya Ueda , Osamu Nakagawa
IPC分类号： H01L21/56 , H01L23/433 , H01L23/495 , H01L23/48 , H01L23/02 , H01L23/28 , H01L27/54
CPC分类号： H01L21/565 , H01L23/4334 , H01L23/49541 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L24/48 , H01L2924/00014 , H01L2924/01029 , H01L2924/181
摘要： A packaged semiconductor device includes a semiconductor chip having first and second surfaces, a plurality of electrodes formed on the first surface of the semiconductor chip, a die pad bonded to the second surface of the semiconductor chip for supporting the semiconductor chip, a plurality of leads having first and second ends, the first ends being connected to corresponding electrodes of the semiconductor chip, a heat spreading plate disposed in opposed relation to the die pad and having an area larger than that of the die pad, at least one end portion of the heat spreading plate lying in the same plane as the second ends of the plurality of leads, and a resin package body encapsulating the semiconductor chip, the die pad, the first ends of the plurality of leads, and the heat spreading plate.
摘要翻译：封装半导体器件包括具有第一和第二表面的半导体芯片，形成在半导体芯片的第一表面上的多个电极，连接到用于支撑半导体芯片的半导体芯片的第二表面的芯片焊盘，多个引线具有第一端和第二端，所述第一端连接到所述半导体芯片的对应电极，与所述芯片焊盘相对设置并且具有大于所述管芯焊盘的面积的散热板，所述散热板的至少一个端部与多根引线的第二端部位于同一平面上的散热板以及封装半导体芯片，芯片焊盘，多个引线的第一端部和散热板的树脂封装主体。

77. 发明授权

US5196917A Carrier tape 失效
标题翻译：载带
公开(公告)号：US5196917A
公开(公告)日：1993-03-23
申请号：US444973
申请日：1989-12-04
申请人： Tetsuya Ueda , Kou Shimomura , Osamu Nakagawa , Seiji Takemura , Kazunari Michii
发明人： Tetsuya Ueda , Kou Shimomura , Osamu Nakagawa , Seiji Takemura , Kazunari Michii
IPC分类号： H01L21/56 , H01L21/60 , H01L23/48
CPC分类号： H01L23/48 , H01L2224/16
摘要： A carrier tape includes an insulating film supporting a plurality of leads. The film has a center device hole for receiving a semiconductor chip therein, a plurality of outer lead holes formed at the periphery of the center device hole, a lead supporting portion positioned between the center device hole and the outer lead holes, and a link portion positioned between a pair of adjacent outer lead holes and connected to the lead supporting portion for directing the flow of molten resin during encapsulation of the semiconductor chip. The link portion includes an opening or recess. The plurality of leads of the carrier tape are supported on the lead supporting of the film, with one end portion of each lead projecting into the center device hole of the film. During manufacture, a semiconductor chip having a plurality of electrodes is positioned within the center device hole, and the leads are electrically connected to respective electrodes of the semiconductor chip. The resultant chip is placed within a cavity of a mold, and a molten resin is injected into the cavity through the opening or recess passage formed in the link portion of the film.
摘要翻译：载带包括支撑多根引线的绝缘膜。薄膜具有用于容纳半导体芯片的中心装置孔，形成在中心装置孔周边的多个外部引线孔，位于中心装置孔和外部引线孔之间的引线支承部分，以及连接部分定位在一对相邻的外引线孔之间并连接到引线支撑部分，用于在半导体芯片封装期间引导熔融树脂的流动。连杆部分包括开口或凹槽。载带的多个引线被支撑在膜的引线支撑上，每个引线的一个端部突出到膜的中心装置孔中。在制造过程中，具有多个电极的半导体芯片位于中心器件孔内，引线与半导体芯片的各个电极电连接。将所得的芯片放置在模具的空腔内，并且通过形成在薄膜的连接部分中的开口或凹槽通道将熔融树脂注入空腔中。

78. 发明授权

US5134093A Method of fabricating a semiconductor device including a protective layer 失效
标题翻译：制造包括保护层的半导体器件的方法
公开(公告)号：US5134093A
公开(公告)日：1992-07-28
申请号：US642474
申请日：1991-01-17
申请人： Teruhito Onishi , Tetsuya Ueda
发明人： Teruhito Onishi , Tetsuya Ueda
IPC分类号： H01L21/302 , H01L21/304 , H01L21/3065 , H01L21/321 , H01L21/3213 , H01L21/768 , H01L23/29 , H01L23/532
CPC分类号： H01L21/76886 , H01L21/321 , H01L23/291 , H01L23/5329 , H01L2924/0002 , H01L2924/13091 , Y10S148/015
摘要： A method of fabricating a semiconductor device is disclosed, which can prevent disconnection failures due to corrosion of aluminum-base alloy lines in the semiconductor device. First, an aluminum-base alloy film containing at least one kind of alloying element other than aluminum is formed on an insulating film which covers a semiconductor substrate. Before the surface of the aluminum-base alloy film is cleaned with fuming nitric acid, the surface treatment of the aluminum-base alloy film is performed using a plasma of an oxygen-base gas, to cover fully the surface of the aluminum-base alloy film with passivation film. Next, the given portions of the aluminum-base alloy film are selectively etched to form a line pattern. The surface treatment of the line pattern is performed using a plasma of an oxygen-base gas to cover fully the sides of the line pattern with passive film, before the surface of the line pattern is cleaned with fuming nitric acid.
摘要翻译：公开了一种制造半导体器件的方法，其可以防止由于半导体器件中的铝基合金线的腐蚀导致的断开故障。首先，在覆盖半导体基板的绝缘膜上形成含有铝以外的至少一种合金元素的铝基合金膜。在用发烟硝酸清洗铝基合金膜的表面之前，使用氧基气体的等离子体进行铝基合金膜的表面处理，以完全覆盖铝基合金的表面薄膜与钝化膜。接下来，选择性地蚀刻铝基合金膜的给定部分以形成线图案。在使用发烟硝酸清洁线图案的表面之前，使用氧基气体的等离子体进行表面处理，以完全覆盖具有钝化膜的线图案的侧面。

79. 发明授权

US5105261A Semiconductor device package having particular lead structure for mounting multiple circuit boards 失效
标题翻译：具有用于安装多个电路板的特定引线结构的半导体器件封装
公开(公告)号：US5105261A
公开(公告)日：1992-04-14
申请号：US758719
申请日：1991-09-09
申请人： Tetsuya Ueda , Toru Tachikawa , Masataka Takehara
发明人： Tetsuya Ueda , Toru Tachikawa , Masataka Takehara
IPC分类号： H05K1/18 , H01L23/495 , H01L23/50 , H01L25/00 , H01L25/10 , H01L25/11 , H01L25/18 , H05K1/14 , H05K3/36
CPC分类号： H05K1/145 , H01L23/49555 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01078 , H01L2924/181 , H05K2201/09709 , H05K2201/10946
摘要： The semiconductor device has leads projecting from at least two sides of all of a package which are bent in a zigzag manner so that ends of the leads lie on at least two planes. The semiconductor device may be mounted across a plurality of printed circuit boards by fixing a part of the leads from one side to a first board and fixing a remaining part of the leads from the other side to a second board, or by fixing a part of the leads on one plane to a first board and fixing a remaining part of the leads on the other plane to a second board.
摘要翻译：半导体器件具有从所有封装的至少两侧突出的引线，其以锯齿形的方式弯曲，使得引线的端部位于至少两个平面上。半导体器件可以通过将一部分引线从一侧固定到第一板并将引线的剩余部分从另一侧固定到第二板，或者通过固定一部分将一个平面上的引线连接到第一板，并将另一个平面上的引线的剩余部分固定到第二板。

80. 发明授权

US5064706A Carrier tape including molten resin flow path element for resin packaged semiconductor devices 失效
标题翻译：载带，包括树脂封装半导体器件的熔融树脂流路元件
公开(公告)号：US5064706A
公开(公告)日：1991-11-12
申请号：US281401
申请日：1988-12-08
申请人： Tetsuya Ueda , Haruo Shimamoto , Hideya Yagoura , Hiroshi Seki , Yasuhiro Teraoka
发明人： Tetsuya Ueda , Haruo Shimamoto , Hideya Yagoura , Hiroshi Seki , Yasuhiro Teraoka
IPC分类号： H01L21/60 , H01L21/56 , H01L23/495
CPC分类号： H01L24/50 , H01L21/565 , H01L23/49524 , H01L23/49572 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , Y10S428/901 , Y10S428/906 , Y10T29/49121 , Y10T428/24273 , Y10T428/24298 , Y10T428/24322
摘要： A carrier tape includes a film having an opening for receiving a semiconductor chip to be resin-molded by a pair of mold halves and outer lead holes formed around the periphery of the opening, a plurality of leads for mounting the semiconductor chip on the film, and a resin running portion cooperating, when the mold halves are closed with the film held between the mold halves, with a gate formed on a parting surface of one of the mold halves to define a resin running path which extends from a portion of the film outside the outer lead holes to the opening for guiding a molten resin into the mold halves while preventing the resin from entering the outer lead holes.
摘要翻译：载带包括具有用于接收半导体芯片的开口的膜，该半导体芯片由一对半模形成，并且形成在开口周围的外部引线孔;多个用于将半导体芯片安装在膜上的引线，以及当所述半模被所述半模保持在所述半模之间的所述半模封闭时，与所述半模中的一个的分离面上形成的门形成一个树脂运行路径，从而形成从所述膜的一部分延伸的树脂行进路径，在外部引线孔外面到开口，用于将熔融树脂引导到半模中，同时防止树脂进入外部引线孔。

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