专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US4953128A Variable delay circuit for delaying input data 失效
标题翻译：用于延迟输入数据的可变延迟电路
公开(公告)号：US4953128A
公开(公告)日：1990-08-28
申请号：US133790
申请日：1987-12-16
申请人： Hiroyuki Kawai , Masahiko Yoshimoto
发明人： Hiroyuki Kawai , Masahiko Yoshimoto
IPC分类号： G11C7/00 , G11C7/10 , G11C8/04 , G11C19/00 , H04N7/62
CPC分类号： H04N21/4302 , G11C7/1006 , G11C8/04 , H04N21/242
摘要： An address counter (2) counts the clock pulses sequentially to provide a count value as an address signal to a coincidence detecting circuit (3) and decoder (4). The coincidence detecting circuit (3) compares delay data applied from a delay data generating circuit (8) with the address signal and applies a reset signal to the address counter (2) when they coincide with each other. The address counter (2) repeats sequentially the above-mentioned operation in response to the reset signal after the count of address is reset to a predetermined value. The decoder (4) specifies a memory cell comprised in a memory device for performing a reading and writing operation in response to the address signal. The data output circuit (6) and the data input circuit (5) perform the reading and writing operation sequentially to the specified memory cell in response to the control signal outputted from the control circuit (7). As a result, the input data previously written is read and outputted with a delay. Therefore, a delayed input data can be obtained as an output data.
摘要翻译：地址计数器（2）对时钟脉冲进行顺序计数，以向计数器（3）和解码器（4）提供作为地址信号的计数值。比较从延迟数据产生电路（8）施加的延迟数据与地址信号，并将复位信号与地址计数器（2）相互重合的同时检测电路（3）进行比较。地址计数器（2）在将地址计数复位到预定值之后，响应于复位信号顺序重复上述操作。解码器（4）指定包含在存储器件中的存储器单元，用于响应于地址信号执行读和写操作。数据输出电路（6）和数据输入电路（5）响应于从控制电路（7）输出的控制信号，顺序地向指定的存储单元执行读和写操作。结果，预先写入的输入数据被延迟地读出并输出。因此，可以获得延迟的输入数据作为输出数据。

72. 发明授权

US4912741A Heating box for a microwave oven 失效
标题翻译：微波炉加热箱
公开(公告)号：US4912741A
公开(公告)日：1990-03-27
申请号：US225421
申请日：1988-07-28
申请人： Yuji Tanaka , Shuji Nagao , Takeshi Nakagawa , Tetsuji Ono
发明人： Yuji Tanaka , Shuji Nagao , Takeshi Nakagawa , Tetsuji Ono
IPC分类号： G11C7/00 , G11C7/10 , G11C8/04 , G11C11/401 , H05B6/80
CPC分类号： H05B6/6426
摘要： A heating box has an interior exposed to microwave energy. The heating box includes a first metal panel and a second metal panel. The first panel has a join portion. The second panel has a join portion which opposes and contacts the join portion of the first panel. The first panel and the second panel are bonded together at the join portions thereof. A plurality of electrical connections between the first and second panels extend in the join portions of the first and second panels. The electrical connections are spaced.
摘要翻译：加热箱内部暴露于微波炉。加热箱包括第一金属板和第二金属板。第一个面板具有连接部分。第二面板具有与第一面板的接合部分相对并接触的接合部分。第一面板和第二面板在其连接部分处结合在一起。第一和第二面板之间的多个电连接在第一和第二面板的连接部分中延伸。电气连接间隔开。

73. 发明授权

US4903242A Serial access memory circuit with improved serial addressing circuit composed of a shift register 失效
标题翻译：串行存取存储器电路具有改进的串行寻址电路，由移位寄存器组成
公开(公告)号：US4903242A
公开(公告)日：1990-02-20
申请号：US190969
申请日：1988-05-06
申请人： Kunihiko Hamaguchi , Yasuhide Ohara
发明人： Kunihiko Hamaguchi , Yasuhide Ohara
IPC分类号： G11C8/04 , G11C7/00 , G11C7/10
CPC分类号： G11C7/1018
摘要： A serial access memory circuit provided with an improved serial addressing circuit which can be fabricated with a reduced number of elements, is disclosed. The memory circuit comprises a memory array of N columns to be serially accessed, and a serial selection circuit including a shift register of N/K stages, a control circuit generating K output signals and a gate circuit receiving output signals of N/K stages of the shift register and K output signals of the control circuit and generating N output signals.

74. 发明授权

US4807192A Memory device employing address multiplexing 失效
标题翻译：采用地址复用的存储器件
公开(公告)号：US4807192A
公开(公告)日：1989-02-21
申请号：US90988
申请日：1987-08-31
申请人： Masao Nakano , Hirohiko Mochizuki , Tsuyoshi Ohira , Yukinori Kodama , Hidenori Nomura
发明人： Masao Nakano , Hirohiko Mochizuki , Tsuyoshi Ohira , Yukinori Kodama , Hidenori Nomura
IPC分类号： G11C7/10 , G11C8/04 , G11C11/40 , G11C13/00
CPC分类号： G11C7/1018 , G11C8/04
摘要： A memory device employing address multiplexing comprises a counter. An external address is initially set in the counter and a counter address value is incremented responsive to toggle of a column address strobe. The counted address value in the counter is supplied as an address signal directly to a column decoder or indirectly to the column decoder through an address buffer. The memory device may be provided with a switching logic circuit which switches the address bits in the counter depending on switching information so that it is possible to arbitrarily determine which address bits in the counter are to determine a nibble address.

75. 发明授权

US4769778A Circuit arrangement comprising a matrix-shaped memory arrangement for digital filtration of image signals in row and column directions 失效
公开(公告)号：US4769778A
公开(公告)日：1988-09-06
申请号：US831791
申请日：1986-02-21
申请人： Reinhard Tielert , Bernd Zehner
发明人： Reinhard Tielert , Bernd Zehner
IPC分类号： H04N7/26 , G11C8/04 , G11C11/409 , G11C11/4096 , H03H17/02 , H03H17/06 , G06F15/31
CPC分类号： G11C11/4096 , G11C11/409 , G11C8/04
摘要： A circuit arrangement comprises a matrix-shaped memory arrangement for digital filtration of image signals in row and column directions and contains three-transistor cells having overlapping write/read cycles as storage elements. A row selector is clocked controlled by the input clock of the incoming image signals and is continuously steppable and resettable at any time. The row selector comprises, respectively, two phase offset signal outputs per selection step which respectively drive a write word line and a read word line and which are provided per row of the matrix. Two separate bit lines, a write bit line and a read bit line, are provided per column and are respectively interconnected to all memory cells of the column. A storage amplifier which is disconnectible from the read bit line is provided per column and has an input connected to the read bit line of the assigned column and an output connected to the bit write line of the following column and serves as a data output. A reset input is connected to the setting inputs of a first element of the row selector as well as to the reset inputs of the remaining elements of the row selector. The chronological spacing between reset pulses is selected such that it equals the required delay time to be set between the undelayed data output and a first, delayed data output. A plurality of such memory-shaped memory arrangements is provided in accordance with the word width of the image data the row selector being provided in common for such plurality, whereby a respective memory block accepts one bit of the image data word and offers the same as the respective corresponding bit of a plurality of differently time delayed output data words. An arithmetic unit combines the data outputs, by adding or, respectively, subtracting, in an arrangement of cascaded logic elements in order to achieve the required filter function.

76. 发明授权

US4740924A Circuit arrangement comprising a matrix-shaped memory arrangement for variably adjustable time delay of digital signals 失效
标题翻译：电路装置包括用于数字信号的可变调节的时间延迟的矩阵状存储装置
公开(公告)号：US4740924A
公开(公告)日：1988-04-26
申请号：US828513
申请日：1986-02-12
申请人： Reinhard Tielert
发明人： Reinhard Tielert
IPC分类号： H03H17/08 , G11C7/10 , G11C8/04 , G11C8/16 , G11C7/00
CPC分类号： G11C7/1006 , G11C8/04 , G11C8/16
摘要： A circuit arrangement for providing a variably adjustable time delay of digital signals comprises a matrix-shaped memory arrangement having storage elements with overlapping write/read cycles. A clock-controlled, continuously steppable row selector normally cyclically circulates, but can be reset at any time. The row selector comprises two mutually phase offset signal outputs per selection step which respectively drive a write word line and a read word line of a word of the matrix. Two separate bit lines, a write bit line and a read bit line, are provided per column and are respectively interconnected to all memory cells of a column. The data input for the data signal to be delayed is connectible to all write bit lines via gates individually assigned to the columns, whereby only one of m gates is activated at a time by the column selector.
摘要翻译：用于提供数字信号的可变调节的时间延迟的电路装置包括具有重叠写/读周期的存储元件的矩阵形存储器装置。一个时钟控制的，连续可执行的行选择器通常循环循环，但可以随时重置。行选择器包括分别驱动矩阵的字的写字线和读字线的每个选择步骤的两个相互相位偏移信号输出。每列提供两个单独的位线，写位线和读位线，并分别互连到列的所有存储单元。要延迟的数据信号的数据输入可以通过单独分配给各列的门连接到所有写入位线，由此，列选择器一次仅激活一个m个门。

77. 发明授权

US4680738A Memory with sequential mode 失效
标题翻译：存储器连续模式
公开(公告)号：US4680738A
公开(公告)日：1987-07-14
申请号：US760712
申请日：1985-07-30
申请人： Aloysius T. Tam
发明人： Aloysius T. Tam
IPC分类号： G11C7/10 , G11C8/04 , G11C8/00
CPC分类号： G11C7/1018 , G11C8/04
摘要： A memory comprising a plurality of memory cells, a column decoder, a row decoder, a plurality of shift registers and a multiplexer is provided for addressing the memory cells in a conventional manner or in a high-speed sequential mode. In the sequential mode alternate cells from each of two sets of cells are addressed and their contents provided on a data output line, or data presented to them on a data input line, at a system clock rate which is much faster than the conventional mode.
摘要翻译：提供包括多个存储器单元，列解码器，行解码器，多个移位寄存器和复用器的存储器，用于以常规方式或以高速顺序模式寻址存储器单元。在顺序模式下，以比常规模式快得多的系统时钟速率寻址来自两组单元格的替代单元，并将其内容提供在数据输出线上或数据输入行上呈现给它们的数据。

78. 发明授权

US4667308A Multi-dimensional-access memory system with combined data rotation and multiplexing 失效
标题翻译：具有组合数据旋转和多路复用的多维存取存储器系统
公开(公告)号：US4667308A
公开(公告)日：1987-05-19
申请号：US596456
申请日：1984-03-16
申请人： David Hayes , Francis E. Rix
发明人： David Hayes , Francis E. Rix
IPC分类号： G06F12/02 , G11C7/10 , G11C8/04 , G06F12/00 , G06F12/06
CPC分类号： G06F12/0207 , G11C7/1006 , G11C8/04
摘要： A data memory arrangement includes n columns of storage elements each column being addressable only one element at a time and having at least n.sup.2 storage elements so as to provide a succession of square arrays. Each square array comprises square sub-sections. On storage of a complementary array of data the data is multiplexed from each square array to the next within each sub-section and after each cycle of such multiplexing the sub-sections are rotated one step cyclically. Such rearrangement of data gives freedom and speed of simultaneous access to data words occurring in original rows and/or columns without excessive penalty in the complexity of the addressing system.
摘要翻译： PCT No.PCT / GB83 / 00178 Sec。 371日期1984年3月16日 102（e）日期1984年3月16日PCT提交1983年7月21日PCT公布。出版物WO84 / 00629 日期1984年2月16日。数据存储器装置包括n列存储元件，每列每次只能寻址一个元件，并且具有至少n2个存储元件，以便提供一系列正方形阵列。每个正方形阵列包括方形子部分。在存储数据的互补阵列时，数据在每个子部分中从每个正方形阵列复用到下一个数据块，并且在这种多路复用的每个周期之后，子部分循环地旋转一步。数据的这种重新排列给出同时访问原始行和/或列中出现的数据字的自由度和速度，而在寻址系统的复杂性中不会过多的惩罚。

79. 发明授权

US4649522A Fast column access memory 失效
标题翻译：快速列存取存储器
公开(公告)号：US4649522A
公开(公告)日：1987-03-10
申请号：US700459
申请日：1985-02-11
申请人： Howard C. Kirsch
发明人： Howard C. Kirsch
IPC分类号： G11C11/41 , G11C7/10 , G11C8/04 , G11C11/401 , G11C11/4096 , G11C13/00
CPC分类号： G11C11/4096 , G11C7/1024 , G11C8/04
摘要： A dynamic random access memory obtains improved access time for reading data from a multiplicity of memory cells along a given selected row. This is obtained by allowing the output data line to remain active between activations of a column enable signal. An increase in data valid time at the memory output is obtained, while allowing increased latitude in memory address setup time.
摘要翻译：动态随机存取存储器从给定的选定行的多个存储单元读取数据获得改进的访问时间。这是通过允许输出数据线在列使能信号的激活之间保持活动而获得的。获得存储器输出的数据有效时间的增加，同时允许在存储器地址建立时间内增加纬度。

80. 发明授权

US4611300A Digital delay line 失效
标题翻译：数字延时线
公开(公告)号：US4611300A
公开(公告)日：1986-09-09
申请号：US643316
申请日：1984-08-21
申请人： Wilson E. Taylor, Jr. , Larry E. Hand
发明人： Wilson E. Taylor, Jr. , Larry E. Hand
IPC分类号： G06F5/10 , G11C7/00 , G11C8/04
CPC分类号： G06F5/10 , G11C7/00 , G11C8/04 , G06F2205/061 , G06F2205/104
摘要： A digital delay system employs a phase-locked loop to control a recall address generator. The phase-locked loop comprises a subtractor for determining the difference between the store address and the recall address and for producing a phase signal corresponding to this difference. The phase signal is directed to a voltage controlled oscillator for controlling the rate at which the recall address generator recalls data from a memory. A delay length is introduced as a phase error into the phase-locked loop. Input data is stored in a memory at a fixed rate, and recalled from the memory at a rate determined by the phase-locked loop. When the error signal is zero, the recall address rate will equal the store address rate and the respective addresses will be equal. When an error signal is introduced into the loop, the VCO will cause the recall address to advance or retard to produce the desired delay, and after the delay has been produced, the phase-locked loop will ensure that the recall address rate is equal to the store address rate. The phase error may be either a constant signal or a low-frequency signal.
摘要翻译：数字延迟系统采用锁相环控制召回地址发生器。锁相环包括用于确定存储地址和调用地址之间的差异并用于产生与该差相对应的相位信号的减法器。相位信号被引导到压控振荡器，用于控制调用地址发生器从存储器调用数据的速率。将延迟长度作为相位误差引入锁相环。输入数据以固定速率存储在存储器中，并以由锁相环确定的速率从存储器中调用。当错误信号为零时，调用地址速率将等于存储地址速率，相应的地址将相等。当误差信号被引入到环路中时，VCO将使调用地址前进或延迟以产生所需的延迟，并且在产生延迟之后，锁相环将确保调用地址速率等于商店地址率。相位误差可以是恒定信号或低频信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式