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71. 发明授权

US09564548B2 Direct wafer bonding 有权
标题翻译：直接晶圆接合
公开(公告)号：US09564548B2
公开(公告)日：2017-02-07
申请号：US14461929
申请日：2014-08-18
申请人： The Boeing Company
发明人： Dhananjay M. Bhusari , Daniel C. Law
IPC分类号： H01L31/0304 , H01L31/0693 , H01L21/20 , H01L31/0687 , H01L31/18 , H01L31/043 , H01L21/18 , H01L29/205
CPC分类号： H01L31/0693 , H01L21/187 , H01L21/2007 , H01L29/205 , H01L31/043 , H01L31/0687 , H01L31/1844 , H01L31/1892 , Y02E10/544 , Y02P70/521
摘要： The disclosure provides for a direct wafer bonding method including providing a bonding layer upon a first and second wafer, and directly bonding the first and second wafers together under heat and pressure. The method may be used for directly bonding an GaAs-based, InP-based, GaP-based, GaSb-based, or Ga(In)N-based device to a GaAs device by introducing a highly doped (Al)(Ga)InP(As)(Sb) layer between the devices. The bonding layer material forms a bond having high bond strength, low electrical resistance, and high optical transmittance.
摘要翻译：本公开提供了直接晶片接合方法，包括在第一和第二晶片上提供结合层，并且在热和压力下将第一和第二晶片直接接合在一起。该方法可以用于通过引入高掺杂（Al）（Ga）InP（Ga）基，GaPb基或Ga（In）N基器件直接结合GaAs器件（As）（Sb）层之间。接合层材料形成具有高粘合强度，低电阻和高透光率的键。

72. 发明授权

US09524872B1 Heterogeneous integrated circuits and devices thereof with a surrogate substrate and transferred semiconductor devices 有权
标题翻译：异质集成电路及其装置具有替代衬底和转移的半导体器件
公开(公告)号：US09524872B1
公开(公告)日：2016-12-20
申请号：US13096780
申请日：2011-04-28
申请人： Peter D. Brewer , Andrew T. Hunter , Yakov Royter
发明人： Peter D. Brewer , Andrew T. Hunter , Yakov Royter
IPC分类号： H01L21/30 , H01L21/18
CPC分类号： H01L21/185 , H01L21/18 , H01L21/187 , H01L21/76251 , H01L21/76264 , H01L21/82 , H01L21/8258
摘要： A heterogeneous integrated circuit and method of making the same. An integrated circuit includes a surrogate substrate including a material selected from the group consisting of Group II, Group III, Group IV, Group V, and Group VI materials and their combinations; at least one active semiconductor device including a material combination selected from the group consisting of Group IV-IV, Group III-V and Group II-VI materials; and at least one transferred semiconductor device including a material combination selected from the group consisting of Group IV-IV, Group III-V and Group II-VI materials. The at least one active semiconductor device and the at least one transferred device are interconnected.
摘要翻译：异构集成电路及其制作方法。集成电路包括包括选自由组II，组III，组IV，组V和组VI材料及其组合组成的组的材料的替代衬底; 至少一个活性半导体器件，其包括选自由IV-IV族，III-V族和II-VI族组成的组的材料组合; 以及至少一个转移的半导体器件，其包括选自由IV-IV族，III-V族和II-VI族组成的组的材料组合。所述至少一个有源半导体器件和所述至少一个转移器件互连。

73. 发明申请

US20160351399A1 Systems and Methods for Bidirectional Device Fabrication 审中-公开
标题翻译：双向器件制造的系统和方法
公开(公告)号：US20160351399A1
公开(公告)日：2016-12-01
申请号：US15164358
申请日：2016-05-25
申请人： Ideal Power Inc.
发明人： Richard A. Blanchard , William C. Alexander
IPC分类号： H01L21/265 , H01L21/283 , H01L21/306 , H01L21/324 , H01L21/683 , H01L29/739 , H01L29/66 , H01L21/18 , H01L21/78
CPC分类号： H01L21/265 , H01L21/187 , H01L21/2252 , H01L21/283 , H01L21/304 , H01L21/30625 , H01L21/324 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L29/0619 , H01L29/0821 , H01L29/1604 , H01L29/4236 , H01L29/66348 , H01L29/732 , H01L29/7375 , H01L29/7397 , H01L2221/68304 , H01L2221/68327 , H03K17/66
摘要： Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.
摘要翻译：双面半导体器件制造的方法和系统。在每个表面上具有多个引线的器件可以使用耐高温处理晶片和中温耐用的晶片来制造。在单个长的高温扩散步骤之前不久可以在两侧引入掺杂剂，将所有掺杂剂扩散到两侧的大致相等的深度。所有的高温处理都是在没有处理晶片的情况下进行的，或者附着有高温处理晶片。一旦安装了中温处理晶片，则不会发生高温处理步骤。可以认为高温可能是在存在铝基金属化时可能导致器件损坏的那些。

74. 发明授权

US09472687B2 Schottky diode and method for making it 有权
标题翻译：肖特基二极管及其制作方法
公开(公告)号：US09472687B2
公开(公告)日：2016-10-18
申请号：US13435221
申请日：2012-03-30
申请人： Stefan Starovecky , Olga Krempaska , Martin Predmersky
发明人： Stefan Starovecky , Olga Krempaska , Martin Predmersky
IPC分类号： H01L21/265 , H01L21/44 , H01L21/18 , H01L29/872 , H01L29/06 , H01L29/47
CPC分类号： H01L29/872 , H01L29/0657 , H01L29/47
摘要： A Schottky diode and a method for making one. The method includes the following steps: providing a semiconductor base body, preferably in the form of a wafer, having a high dopant concentration and having a first main surface, which forms the first electrical contact surface of the Schottky diode; epitaxially depositing a semiconductor layer having the same conductivity and a lower dopant concentration on that surface of the semiconductor base body which lies opposite the first main surface; arranging a first metal layer on the semiconductor layer with the formation of a Schottky contact between the first metal layer and the semiconductor layer; connecting a planar contact body to the first metal layer by means of a connecting means; forming at least one individual Schottky diode; and arranging a passivation layer in the edge region of the at least one Schottky diode.
摘要翻译：肖特基二极管及其制造方法。该方法包括以下步骤：提供优选具有高掺杂浓度的晶片形式的半导体基体，并具有形成肖特基二极管的第一电接触表面的第一主表面; 在半导体基体的与第一主表面相对的表面上外延沉积具有相同导电性和较低掺杂剂浓度的半导体层; 在第一金属层和半导体层之间形成肖特基接触，在半导体层上布置第一金属层; 通过连接装置将平面接触体连接到第一金属层; 形成至少一个单独的肖特基二极管; 以及在所述至少一个肖特基二极管的边缘区域中布置钝化层。

75. 发明申请

US20160300837A1 WAFER STRUCTURE FOR ELECTRONIC INTEGRATED CIRCUIT MANUFACTURING 有权
公开(公告)号：US20160300837A1
公开(公告)日：2016-10-13
申请号：US15181110
申请日：2016-06-13
申请人： Aeroflex Colorado Springs Inc.
发明人： David B. Kerwin , Joseph M. Benedetto
IPC分类号： H01L27/092 , H01L23/552 , H01L21/18 , H01L23/556
CPC分类号： H01L27/0921 , H01L21/187 , H01L23/552 , H01L23/556 , H01L29/1087
摘要： A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

76. 发明申请

US20160268134A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20160268134A1
公开(公告)日：2016-09-15
申请号：US14840926
申请日：2015-08-31
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yasuhiro ISOBE , Kunio TSUDA
IPC分类号： H01L21/18 , H01L21/306 , H01L21/304 , H01L21/02 , H01L21/324
CPC分类号： H01L21/187 , H01L29/0821 , H01L29/2003 , H01L29/41708 , H01L29/41766 , H01L29/66712 , H01L29/732 , H01L29/7802
摘要： A method for manufacturing a semiconductor device includes forming, on a substrate, a first conductivity type nitride semiconductor layer in which gallium nitride is contained, wherein the exposed face of the first conductivity type nitride semiconductor layer has a (0001) face, forming, on a substrate, a second conductivity type nitride semiconductor layer in which gallium nitride is contained, wherein the exposed face of the first conductivity type nitride semiconductor layer has a (000-1) face, and bonding the first conductivity type nitride semiconductor layer and the second conductivity type nitride semiconductor layer together by heating in a state where the first conductivity type nitride semiconductor layer faces and contacts the second conductivity type nitride semiconductor layer.
摘要翻译：一种制造半导体器件的方法包括在衬底上形成其中包含氮化镓的第一导电型氮化物半导体层，其中第一导电型氮化物半导体层的暴露面具有（0001）面，形成衬底，含有氮化镓的第二导电型氮化物半导体层，其中第一导电型氮化物半导体层的暴露面具有（000-1）面，并且将第一导电型氮化物半导体层和第二导电型氮化物半导体层通过在第一导电型氮化物半导体层面对并接触第二导电型氮化物半导体层的状态下加热而一起导电型氮化物半导体层。

77. 发明授权

US09412620B2 Three-dimensional integrated circuit device fabrication including wafer scale membrane 有权
标题翻译：三维集成电路器件制造包括晶圆膜
公开(公告)号：US09412620B2
公开(公告)日：2016-08-09
申请号：US14597327
申请日：2015-01-15
申请人： GlobalFoundries U.S. 2 LLC
发明人： Douglas C. La Tulipe, Jr. , Sampath Purushothaman , James Vichiconti
IPC分类号： H01L21/77 , H01L21/322 , H01L21/02 , H01L21/683 , H01L21/762 , H01L23/00 , H01L25/065 , H01L25/00 , H01L29/06 , C23C16/40 , C23C16/513 , C23C16/56 , H01L21/18 , H01L21/67
CPC分类号： H01L21/3065 , C23C16/402 , C23C16/513 , C23C16/56 , H01L21/02002 , H01L21/187 , H01L21/3221 , H01L21/67063 , H01L21/67069 , H01L21/6835 , H01L21/76251 , H01L21/77 , H01L24/94 , H01L25/00 , H01L25/0657 , H01L25/50 , H01L29/06 , H01L2221/68377 , H01L2224/83121 , H01L2225/06513 , H01L2924/01005 , H01L2924/01033 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： Method and Apparatus so configured for the fabrication of three-dimensional integrated devices. A crystalline substrate within an area of a donor semiconductor wafer is etched. The substrate side is located opposite a device layer and has a buried insulating layer and a substrate thickness. The etching removes at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer in the area is to conform to a pattern specific topology on an acceptor surface. The donor semiconductor wafer is supported with a supporting structure that allows the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.
摘要翻译：如此配置用于制造三维集成装置的方法和装置。在施主半导体晶片的区域内的晶体衬底被蚀刻。衬底侧面与器件层相对，并具有掩埋绝缘层和衬底厚度。蚀刻去除区域内的晶体衬底的至少大部分，使得该区域中的器件层和掩埋绝缘层符合受主表面上的图案特定拓扑。施主半导体晶片由支撑结构支撑，支撑结构允许施主半导体晶片在蚀刻之后在该区域的至少一部分内灵活地符合图案特定拓扑，以使得能够使受保护晶片的器件表面的一致性和可靠地结合到形成三维集成设备。

78. 发明授权

US09406513B2 Graphene laminate with band gap 有权
标题翻译：石墨烯层压板带隙
公开(公告)号：US09406513B2
公开(公告)日：2016-08-02
申请号：US14186055
申请日：2014-02-21
申请人： Samsung Electronics Co., Ltd.
发明人： Si-Young Lee , Young-hee Lee , Jae-young Choi
IPC分类号： H01L29/16 , H01L21/18 , H01L29/786 , H01L29/778
CPC分类号： H01L21/18 , H01L29/1606 , H01L29/778 , H01L29/78684
摘要： A graphene laminate includes a first piezoelectric material layer having a negatively-charged surface and a positively-charged surface, a first graphene layer under the first piezoelectric material layer, the first graphene layer contacting the positively-charged surface of the first piezoelectric material layer, a second graphene layer underlying the first graphene layer, and a second piezoelectric material layer under the second graphene layer, the second piezoelectric material layer having a negatively-charged surface and a positively-charged surface, the negatively-charged surface contacting the second graphene layer.
摘要翻译：石墨烯层压体包括具有带负电荷的表面和带正电荷的表面的第一压电材料层，在第一压电材料层下面的第一石墨烯层，与第一压电材料层的带正电表面相接触的第一石墨烯层，在第一石墨烯层下面的第二石墨烯层，以及在第二石墨烯层下面的第二压电材料层，第二压电材料层具有带负电荷的表面和带正电的表面，与第二石墨烯层接触的带负电的表面。

79. 发明授权

US09373699B2 Semiconductor devices with field plates 有权
公开(公告)号：US09373699B2
公开(公告)日：2016-06-21
申请号：US14660080
申请日：2015-03-17
申请人： Transphorm Inc.
发明人： Rongming Chu , Robert Coffie
IPC分类号： H01L29/66 , H01L21/336 , H01L21/3065 , H01L21/283 , H01L29/12 , H01L21/18 , H01L21/285 , H01L29/20 , H01L29/40 , H01L29/423 , H01L29/778 , H01L29/872 , H01L21/765 , H01L29/06 , H01L21/02 , H01L21/306 , H01L21/311 , H01L29/78 , H01L29/417 , H01L29/51
CPC分类号： H01L29/402 , H01L21/0217 , H01L21/02271 , H01L21/02274 , H01L21/283 , H01L21/28587 , H01L21/30612 , H01L21/31105 , H01L21/765 , H01L29/0607 , H01L29/2003 , H01L29/404 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/518 , H01L29/66212 , H01L29/66462 , H01L29/66522 , H01L29/66666 , H01L29/778 , H01L29/7781 , H01L29/7786 , H01L29/7787 , H01L29/78 , H01L29/872
摘要： A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

80. 发明授权

US09331227B2 Directly bonded, lattice-mismatched semiconductor device 有权
标题翻译：直接键合，晶格失配的半导体器件
公开(公告)号：US09331227B2
公开(公告)日：2016-05-03
申请号：US14152464
申请日：2014-01-10
申请人： The Boeing Company
发明人： Daniel C. Law , Richard R. King , Dimitri Daniel Krut , Dhananjay Bhusari
IPC分类号： H01L21/02 , H01L31/0725 , H01L21/18 , H01L31/18
CPC分类号： H01L31/0725 , H01L21/187 , H01L31/043 , H01L31/0693 , H01L31/18 , H01L31/1892 , Y02E10/544 , Y02P70/521
摘要： A semiconductor device may include a first subassembly and a second subassembly. The first subassembly may include a first bonding layer. The second subassembly may include a second substrate and a second bonding layer directly bonded to the first bonding layer. The first bonding layer and the second bonding layer may be lattice-mismatched to one another. At least one of the following may be selected: the first bonding layer is lattice-mismatched to the first substrate, and the second bonding layer is lattice-mismatched to the second substrate.
摘要翻译：半导体器件可以包括第一子组件和第二子组件。第一子组件可以包括第一结合层。第二子组件可以包括直接接合到第一接合层的第二衬底和第二接合层。第一接合层和第二接合层可以彼此晶格失配。可以选择以下中的至少一个：第一结合层与第一衬底晶格失配，并且第二结合层与第二衬底晶格失配。

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