专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US07425869B2 Distributed circular geometry power amplifier architecture 有权
标题翻译：分布式圆形几何功率放大器架构
公开(公告)号：US07425869B2
公开(公告)日：2008-09-16
申请号：US11480113
申请日：2006-06-30
申请人： Ichiro Aoki , Seyed-Ali Hajimiri , David B. Ruthledge , Scott David Kee
发明人： Ichiro Aoki , Seyed-Ali Hajimiri , David B. Ruthledge , Scott David Kee
IPC分类号： H03F3/26
CPC分类号： H03F1/223 , H03F3/265 , H03F3/423 , H03F3/604 , H03F2200/534 , H03F2200/537 , H03F2200/541
摘要： The present invention discloses a distributed power amplifier topology and device that efficiently and economically enhances the power output of an RF signal to be amplified. The power amplifier comprises a plurality of push-pull amplifiers interconnected in a novel circular geometry that preferably function as a first winding of an active transformer having signal inputs of adjacent amplification devices driven with an input signal of equal magnitude and opposite phase. The topology also discloses the use of a secondary winding that matches the geometry of primary winding and variations thereof that serve to efficiently combine the power of the individual power amplifiers. The novel architecture enables the design of low-cost, fully-integrated, high-power amplifiers in the RF, microwave, and millimeter-wave frequencies.
摘要翻译：本发明公开了一种分布式功率放大器拓扑和器件，其有效且经济地增强待放大的RF信号的功率输出。功率放大器包括以新颖的圆形几何互连的多个推挽放大器，其优选地用作有源变压器的第一绕组，该有源变压器的信号输入由相等幅度和相反相位的输入信号驱动的相邻放大器件的信号输入。该拓扑还公开了使用与初级绕组的几何形状及其变化相匹配的次级绕组，其用于有效地组合各个功率放大器的功率。新颖的架构使得能够在RF，微波和毫米波频率中设计低成本，完全集成的大功率放大器。

72. 发明申请

US20080174369A1 HIGH SPEED, HIGH CURRENT GAIN VOLTAGE BUFFER AND METHOD 有权
标题翻译：高速，高电流增益缓冲器和方法
公开(公告)号：US20080174369A1
公开(公告)日：2008-07-24
申请号：US11655708
申请日：2007-01-19
申请人： Sergey Alenin , Henry Surtihadi
发明人： Sergey Alenin , Henry Surtihadi
IPC分类号： H03F3/26
CPC分类号： H03F3/26
摘要： An amplifying circuit which may be useful in a diamond buffer amplifier or operational amplifier includes an input transistor including an emitter, a collector, and a base coupled to receive an input voltage. An adjustable current source circuit is coupled between a first reference voltage and the emitter of the input transistor. A current source is coupled between a second reference voltage and the collector of the input transistor. An isolation resistor has a first terminal coupled to an output terminal of the adjustable current source circuit and a second terminal coupled to the emitter of the input transistor. A current follower circuit is coupled between the collector of the input transistor and an input terminal of the adjustable current source circuit. A feed-forward capacitor is coupled between the collector of the input transistor and the first terminal of the isolation resistor.
摘要翻译：可用于金刚石缓冲放大器或运算放大器的放大电路包括输入晶体管，其包括耦合以接收输入电压的发射极，集电极和基极。可调电流源电路耦合在第一参考电压和输入晶体管的发射极之间。电流源耦合在第二参考电压和输入晶体管的集电极之间。隔离电阻器具有耦合到可调电流源电路的输出端的第一端子和耦合到输入晶体管的发射极的第二端子。电流跟随器电路耦合在输入晶体管的集电极和可调电流源电路的输入端之间。前馈电容器耦合在输入晶体管的集电极和隔离电阻的第一端之间。

73. 发明授权

US07327194B2 Low voltage low power class A/B output stage 有权
标题翻译：低电压低功耗级A / B输出级
公开(公告)号：US07327194B2
公开(公告)日：2008-02-05
申请号：US11290286
申请日：2005-11-30
申请人： Chin Sing Li
发明人： Chin Sing Li
IPC分类号： H03F3/26
CPC分类号： H03F3/3022 , H03F3/21 , H03F3/347 , H03F3/45183 , H03F3/45188 , H03F2200/162 , H03F2200/513 , H03F2203/45644
摘要： A CMOS class A/B output stage provides the advantages of high speed operation, low supply voltage requirements, and low quiescent current draw, resulting from the use of subthreshold biasing of the output driver transistors. The architecture of the output stage makes it particularly suitable for use in operational amplifiers in power demanding applications, such as portable instruments, smoke detectors, sensors, or the like.
摘要翻译： CMOS级A / B输出级提供了由于使用输出驱动晶体管的阈值偏置而导致的高速运行，低电源电压要求和低静态电流消耗的优点。输出级的架构使其特别适合于在诸如便携式仪器，烟雾探测器，传感器等的电力需求应用中的运算放大器中使用。

74. 发明授权

US07298211B2 Power amplifying apparatus 有权
标题翻译：功率放大装置
公开(公告)号：US07298211B2
公开(公告)日：2007-11-20
申请号：US11144856
申请日：2005-06-03
申请人： Hideo Akama
发明人： Hideo Akama
IPC分类号： H03F3/26
CPC分类号： H03F3/3023 , H03F3/303 , H03F2203/30015
摘要： A push-pull amplifier includes a pair of transistors, wherein each of the transistors has a control terminal, a first terminal, and a second terminal. A current that flows between the first terminal and the second terminal is controlled in accordance with signals applied to the control terminal, such that when an amount of current flowing between the first terminal and the second terminal of one of the transistors is within a predetermined range, a high-frequency component of the signals input to the control terminal of one of the transistors is amplified, and when this current is outside the predetermined range, the high frequency component is not amplified.
摘要翻译：推挽放大器包括一对晶体管，其中每个晶体管具有控制端子，第一端子和第二端子。根据施加到控制端子的信号来控制在第一端子和第二端子之间流动的电流，使得当在一个晶体管的第一端子和第二端子之间流动的电流量在预定范围内时输入到一个晶体管的控制端子的信号的高频分量被放大，并且当该电流在预定范围之外时，高频分量不被放大。

75. 发明授权

US07271655B2 Power amplifier end stage 有权
标题翻译：功放终端
公开(公告)号：US07271655B2
公开(公告)日：2007-09-18
申请号：US10514284
申请日：2003-04-23
申请人： Marco Berkhout
发明人： Marco Berkhout
IPC分类号： H03F3/26
CPC分类号： H03F3/2171
摘要： In a push-pull power amplifier having an end stage (10) in which two power transistors (ML, MH) are connected in series, a dead time is normally used to ensure that the power transistors do not conduct simultaneously. The invention provides an end stage in which the dead time can be omitted. This is achieved by dimensioning the driver circuits (11, 12) in such a way that during switching the control voltages (Vgh, Vgl) of the power transistors cross their threshold level (VT) substantially simultaneously.
摘要翻译：在具有其中两个功率晶体管（ML，MH）串联连接的端级（10）的推挽功率放大器中，通常使用死区时间来确保功率晶体管不同时导通。本发明提供了可以省略死区时间的终止阶段。这通过使驱动电路（11,12）的尺寸确定，使得在功率晶体管的控制电压（Vgh，Vgl）的切换基本上同时跨越其阈值电平（VT）。

76. 发明申请

US20070159255A1 High output current buffer 失效
标题翻译：高输出电流缓冲器
公开(公告)号：US20070159255A1
公开(公告)日：2007-07-12
申请号：US11328671
申请日：2006-01-10
申请人： Steven Smith
发明人： Steven Smith
IPC分类号： H03F3/26
CPC分类号： H03F3/3076
摘要： A bipolar high output current buffer is disclosed using a negative feedback current mirror to supply the base drive to an output transistor. Small quiescent currents are used wherein the buffer demonstrates low quiescent power dissipation. The current mirror supplies the incremental base drive to the output transistor to support high output currents. When the output drive may source or sink the high output currents, two current mirrors may be used, one for each of the source and the sinking circuitry. This invention provides for minimal loss of dynamic range.
摘要翻译：公开了一种双极性高输出电流缓冲器，其使用负反馈电流镜来将基极驱动器提供给输出晶体管。使用小的静态电流，其中缓冲器表现出低的静态功耗。电流镜将增量式基极驱动器提供给输出晶体管，以支持高输出电流。当输出驱动器可以输出或吸收高输出电流时，可以使用两个电流镜，一个用于源极和吸收电路。本发明提供了动态范围的最小损失。

77. 发明授权

US07215201B2 Integrated circuit having a low power, gain-enhanced, low noise amplifying circuit 有权
标题翻译：具有低功率，增益增强，低噪声放大电路的集成电路
公开(公告)号：US07215201B2
公开(公告)日：2007-05-08
申请号：US11156851
申请日：2005-06-20
申请人： Per Torstein Roine
发明人： Per Torstein Roine
IPC分类号： H03F3/26
CPC分类号： H03F3/45264 , H03F3/193
摘要： An amplifying circuit includes an n-type transistor having a source, a gate coupled to a first bias voltage, and a drain coupled to a first supply voltage through a first impedance circuit. A p-type transistor of the circuit has a source coupled to the source of the n-type transistor, a gate coupled to a second bias voltage, and a drain coupled to a second supply voltage through a second impedance circuit. A first differential input is coupled to the gate of the n-type transistor through a first capacitor and to the gate of the p-type transistor through a second capacitor. A second differential input is coupled to the sources of the n-type and the p-type transistors. A third capacitor has a first end coupled to the drain of the n-type transistor, and a fourth capacitor has a first end coupled to the drain of the p-type transistor and a second end coupled to a second end of the third capacitor. An output of the amplifier circuit is provided at the second ends of the third and the fourth capacitors. The n-type transistor and the first impedance circuit serve as a common-source amplifier for a signal at the first differential input and as a common-gate amplifier for the signal at the second differential input. Similarly, the p-type transistor and the second impedance circuit serve as a common-source amplifier for the signal at the first differential input and as a common-gate amplifier for the signal at the second differential input.
摘要翻译：放大电路包括具有源极，耦合到第一偏置电压的栅极和通过第一阻抗电路耦合到第一电源电压的漏极的n型晶体管。电路的p型晶体管具有耦合到n型晶体管的源极，耦合到第二偏置电压的栅极和通过第二阻抗电路耦合到第二电源电压的漏极的源极。第一差分输入通过第一电容器耦合到n型晶体管的栅极，并通过第二电容器耦合到p型晶体管的栅极。第二差分输入耦合到n型和p型晶体管的源极。第三电容器具有耦合到n型晶体管的漏极的第一端，并且第四电容器具有耦合到p型晶体管的漏极的第一端和耦合到第三电容器的第二端的第二端。在第三和第四电容器的第二端设置放大器电路的输出。 n型晶体管和第一阻抗电路用作在第一差分输入处的信号的公共源放大器，以及用作在第二差分输入处的信号的公共栅极放大器。类似地，p型晶体管和第二阻抗电路用作用于第一差分输入处的信号的公共源放大器，以及用作在第二差分输入处的信号的公共栅极放大器。

78. 发明申请

US20060208800A1 Biasing stage for an amplifier 有权
公开(公告)号：US20060208800A1
公开(公告)日：2006-09-21
申请号：US11378029
申请日：2006-03-15
申请人： Jefferson Harman
发明人： Jefferson Harman
IPC分类号： H03F3/26
CPC分类号： H03F3/3069 , H03F1/30 , H03F1/301 , H03F1/307 , H03F1/308 , H03F3/301 , H03F3/3435
摘要： An amplifier biasing stage includes a transistor that provides a biasing signal for a complementary pair of field-effect transistors included in an output stage of an amplifier. The amplifier biasing stage also includes one resistive element connected to an emitter of the transistor, another resistive element connected to a base of the transistor, and still another resistive element connected to a collector of the transistor. The respective resistances of the resistive elements are selected to substantially match a voltage provided by the amplifier biasing stage to a gate-to-source voltage of the complementary pair of field-effect transistors. The resistances of the resistive elements are also selected to substantially match a temperature coefficient of the amplifier biasing stage to a temperature coefficient of the complimentary pair of field-effect transistors.

79. 发明授权

US07091787B2 Transconductance amplifier with temperature sensitive current limiting 有权
标题翻译：具有温度敏感电流限制的跨导放大器
公开(公告)号：US07091787B2
公开(公告)日：2006-08-15
申请号：US10873902
申请日：2004-06-22
申请人： Scott C. Willis
发明人： Scott C. Willis
IPC分类号： H03F3/26
CPC分类号： H03F3/26 , H03F3/3083 , H03F3/3432 , H03F3/45475 , H03F2200/447 , H03F2203/45288
摘要： A transconductance amplifier generally limits its current output, and specifically decreases its current output as a function of temperature. The circuit is made up of an operational amplifier and two drive transistors that are connected to a first part of the amplifier circuit and a second part of the amplifier circuit respectively. The first part of the circuit is driven by positive input voltages, and the second part of the circuit is driven by negative input voltages. A transistor in each part of the circuit clamps a voltage, thereby limiting the current output. The negative temperature coefficient of the transistor also decreases the output current as the temperature of the circuit rises.
摘要翻译：跨导放大器通常限制其电流输出，并且具体地降低其作为温度的函数的电流输出。电路由运算放大器和两个驱动晶体管组成，分别连接到放大器电路的第一部分和放大器电路的第二部分。电路的第一部分由正输入电压驱动，电路的第二部分由负输入电压驱动。电路的每个部分中的晶体管钳位电压，从而限制电流输出。当电路的温度上升时，晶体管的负温度系数也降低了输出电流。

80. 发明授权

US07015756B1 Push-pull buffer/amplifier 有权
标题翻译：推挽缓冲/放大器
公开(公告)号：US07015756B1
公开(公告)日：2006-03-21
申请号：US11189464
申请日：2005-07-26
申请人： Swee-Ann Teo
发明人： Swee-Ann Teo
IPC分类号： H03F3/45 , H03F3/26
CPC分类号： H03F3/26 , H03F3/45089 , H03F3/45103 , H03F2203/45118 , H03F2203/45318 , H03F2203/45512 , H03F2203/45546
摘要： A differential circuit comprises first, second, third and fourth devices that have first, second, third and fourth control terminals, respectively. The second and fourth devices are arranged in series with the first and third devices, respectively. A first output communicates with the first device and the second device. A second output communicates with the third device and the fourth device. First and second inputs communicate with the first and fourth control terminals, respectively. The first, second, third and fourth devices are the same type of devices. The third and second control terminals follow the first and fourth control terminals. When the first device pushes, the third device pulls. When the first device pulls, the third device pushes. When the fourth device pushes, the second device pulls. When the fourth device pulls, the second device pushes. The second and third devices and the first and fourth devices are matched.
摘要翻译：差分电路包括分别具有第一，第二，第三和第四控制端的第一，第二，第三和第四器件。第二和第四装置分别与第一和第三装置串联布置。第一输出与第一设备和第二设备通信。第二输出与第三设备和第四设备通信。第一和第二输入分别与第一和第四控制端相通。第一，第二，第三和第四设备是相同类型的设备。第三和第二控制终端遵循第一和第四控制端。当第一个设备按下时，第三个设备拉。当第一个设备拉动时，第三个设备按下。当第四个设备按下时，第二个设备拉动。当第四个设备拉动时，第二个设备按下。第二和第三设备以及第一和第四设备匹配。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式