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71. 发明授权

US09064330B2 Shared virtual memory between a host and discrete graphics device in a computing system 有权
标题翻译：在计算系统中的主机和独立图形设备之间共享虚拟内存
公开(公告)号：US09064330B2
公开(公告)日：2015-06-23
申请号：US14489023
申请日：2014-09-17
申请人： Intel Corporation
发明人： Boris Ginzburg
IPC分类号： G06F15/167 , G06F15/16 , G06T1/60 , G09G5/39 , G06F12/12 , G06F12/08 , G06F3/14 , G06F12/10 , G09G5/36
CPC分类号： G06T1/60 , G06F3/14 , G06F12/0802 , G06F12/1009 , G06F12/1027 , G06F12/1036 , G06F12/1045 , G06F12/1063 , G06F12/1081 , G06F12/109 , G06F12/12 , G06F2212/302 , G06F2212/455 , G06F2212/656 , G06T2200/28 , G09G5/363 , G09G5/39 , G09G2360/121 , G09G2360/125
摘要： In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有设备处理器和设备存储器的设备。该设备可以连接到具有主机处理器和主机内存的主机。两个存储器都可以具有页表以将虚拟地址映射到相应存储器的物理地址，并且两个存储器可以以用户级应用程序显示为单个虚拟存储器空间。描述和要求保护其他实施例。

72. 发明申请

US20150138217A1 DISPLAY SYSTEM 有权
标题翻译：显示系统
公开(公告)号：US20150138217A1
公开(公告)日：2015-05-21
申请号：US14401083
申请日：2013-05-15
申请人： Piotr Czapla , Sebastian Matysik
发明人： Piotr Czapla , Sebastian Matysik
IPC分类号： G09G5/39
CPC分类号： G09G5/39 , G06F3/1431 , G09G5/006 , G09G5/395 , G09G2360/12 , G09G2360/18
摘要： A display system comprises a processing device connected to a plurality of display devices, the processing device comprising a processor connected to a system memory and to a graphics processing unit, the graphics processing unit comprising a graphics processor connected to a video memory. A method of operating the system comprises the steps of maintaining a system frame buffer in system memory, creating a shared primary surface in video memory for an additional display device not controlled by the graphics processing unit, rendering the contents of the system frame buffer onto the shared primary surface, rendering any and all directly rendered applications onto the shared primary surface, maintaining a second frame buffer in system memory, copying at least some of the content of the shared primary surface to the second frame buffer, and outputting at least some of the content of the second frame buffer to the additional display device.
摘要翻译：显示系统包括连接到多个显示设备的处理设备，所述处理设备包括连接到系统存储器和图形处理单元的处理器，所述图形处理单元包括连接到视频存储器的图形处理器。一种操作该系统的方法包括以下步骤：在系统存储器中保持系统帧缓冲器，在视频存储器中创建共享主表面，用于不由图形处理单元控制的附加显示设备，将系统帧缓冲器的内容呈现到共享主表面，将任何和所有直接呈现的应用呈现到共享主表面上，在系统存储器中维护第二帧缓冲器，将共享主表面的至少一些内容复制到第二帧缓冲器，以及输出至少一些第二帧缓冲器的内容到附加显示设备。

73. 发明授权

US09030481B2 Method and apparatus for reducing power usage during video presentation on a display 有权
标题翻译：用于在显示器上的视频呈现期间减少功率使用的方法和装置
公开(公告)号：US09030481B2
公开(公告)日：2015-05-12
申请号：US13631681
申请日：2012-09-28
申请人： Intel Corporation
发明人： Seh Kwa , Satyanarayana Avadhanam
IPC分类号： G09G5/36 , G09G5/39 , H04N5/46 , H04N5/04 , G06F3/14 , H04N21/4402
CPC分类号： G09G5/18 , G06F3/14 , G09G3/2096 , G09G5/003 , G09G5/12 , G09G5/363 , G09G5/395 , G09G2330/021 , G09G2360/18 , G09G2370/10 , H04N5/04 , H04N5/46 , H04N21/440281
摘要： An apparatus may include a link component and a display component. The link component may be operative to receive media content via data frames over a display interconnect, the data frames received periodically in succession at a first rate corresponding to a native frame rate of the media content. The display component may be operative to display the data frames in succession at a second rate corresponding to a native refresh rate of the display component, the display component operative to re-display data frames already shown to maintain the second rate when new data frames have not been received over the display interconnect.
摘要翻译：装置可以包括链接部件和显示部件。链路组件可以用于经由显示器互连器上的数据帧接收媒体内容，数据帧以对应于媒体内容的本地帧速率的第一速率连续地周期性地接收。所述显示组件可操作以以对应于所述显示组件的本机刷新率的第二速率连续地显示所述数据帧，所述显示组件可操作以重新显示已显示的数据帧，以便当新的数据帧具有未经显示器互连接收。

74. 发明申请

US20150097847A1 MANAGING MEMORY REGIONS TO SUPPORT SPARSE MAPPINGS 有权
标题翻译：管理存储区域来支持SPARSE映射
公开(公告)号：US20150097847A1
公开(公告)日：2015-04-09
申请号：US14046064
申请日：2013-10-04
申请人： NVIDIA CORPORATION
发明人： Jonathan DUNAISKY , Henry Packard MORETON , Jeffrey A. BOLZ , Yury Y. URALSKY , James Leroy DEMING , Rui M. BASTOS , Patrick R. BROWN , Amanpreet GREWAL , Christian AMSINCK , Poornachandra RAO , Jerome F. DULUK, JR. , Andrew J. TAO
IPC分类号： G09G5/39 , G06T1/60
CPC分类号： G09G5/39 , G06F12/0897 , G06F12/1027 , G06T1/60
摘要： One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.
摘要翻译：本发明的一个实施例包括被配置为管理稀疏映射的存储器管理单元（MMU）。 MMU根据指示稀疏状态的页表项（PTE）处理将虚拟地址转换为物理地址的请求。如果MMU确定PTE不包括从虚拟地址到物理地址的映射，则MMU将根据稀疏状态对该请求进行响应。如果稀疏状态为活动状态，则MMU将根据请求的类型是否为写入操作确定物理地址，然后生成请求的确认。相比之下，如果稀疏状态不活动，则MMU会生成页面错误。有利地，所公开的实施例使得计算机系统能够管理稀疏映射，而不会引起与页面故障和常规的基于软件的稀疏映射管理相关联的性能下降。

75. 发明授权

US08970611B2 Display device and method for transferring image data 有权
标题翻译：用于传送图像数据的显示装置和方法
公开(公告)号：US08970611B2
公开(公告)日：2015-03-03
申请号：US13248118
申请日：2011-09-29
申请人： Kazuo Ikeno , Daisuke Satsukawa
发明人： Kazuo Ikeno , Daisuke Satsukawa
IPC分类号： G06F13/00 , G09G5/39 , G09G5/393 , G06F3/14 , G09G3/36
CPC分类号： G09G5/393 , G06F3/14 , G09G3/3622 , G09G2380/10
摘要： For providing a display device and a method for transferring an image data, shortening process time required to transfer image data without greater processing capacity, the CPU 4 outputs the bypass write signal to the GDC 6, the CPU 4 then outputs the read signal to both the ROM 5 and the GDC 6, and the ROM 5 outputs the image data to the data bus 8 according to input of the read signal, wherein the GDC 6 directly reads the image data outputted on the data bus 8 according to input of the read not through the CPU 4 and writes the read image data to the VRAM 7.
摘要翻译：为了提供用于传送图像数据的显示装置和方法，缩短传送图像数据而不增加处理能力所需的处理时间，CPU4将旁路写入信号输出到GDC 6，然后CPU 4将读取信号输出到两者 ROM5和GDC6，并且ROM5根据读取信号的输入将图像数据输出到数据总线8，其中GDC6根据读取的输入直接读取在数据总线8上输出的图像数据不通过CPU 4将读取的图像数据写入VRAM 7。

76. 发明授权

US08963938B2 Modified quality of service (QoS) thresholds 有权
标题翻译：修改服务质量（QoS）阈值
公开(公告)号：US08963938B2
公开(公告)日：2015-02-24
申请号：US13744637
申请日：2013-01-18
申请人： Apple Inc.
发明人： Peter F. Holland
IPC分类号： G06F13/00 , G09G5/39 , G06T1/20
CPC分类号： G06T1/20 , G06T1/60
摘要： In an embodiment, a display pipe processes video data for visual display. The display pipe may read the video data from memory, and may employ QoS levels with the memory requests to ensure that enough data is provided to satisfy the real time display requirements. The display pipe may include a pixel buffer that stores pixels that are ready for display. Additionally, the display pipe may include one or more input buffers configured to store input video data to be processed and/or one or more output buffers configured to store processed data that is ready for blending into the final pixels for display. The display pipe determine a number of output equivalent pixels in the data in the input and output buffers, and may consider those pixels as well as the ready pixels in the pixel buffer in determining the QoS levels for requests.
摘要翻译：在一个实施例中，显示管处理用于视觉显示的视频数据。显示管道可以从存储器读取视频数据，并且可以使用具有存储器请求的QoS级别来确保提供足够的数据以满足实时显示要求。显示管可以包括存储准备显示的像素的像素缓冲器。此外，显示管道可以包括被配置为存储要处理的输入视频数据的一个或多个输入缓冲器和/或被配置为存储处理后的数据的一个或多个输出缓冲器，该处理后的数据准备好进行混合到最终的像素中进行显示。显示管确定输入和输出缓冲器中的数据中的输出等效像素的数量，并且可以在确定请求的QoS等级时考虑像素缓冲器中的那些像素以及就绪像素。

77. 发明申请

US20150049103A1 CONTROL CIRCUIT FOR FRAME MEMORY, DISPLAY DEVICE INCLUDING THE SAME AND METHOD OF CONTROLLING THE SAME 审中-公开
标题翻译：用于框架存储器的控制电路，包括其的显示装置及其控制方法
公开(公告)号：US20150049103A1
公开(公告)日：2015-02-19
申请号：US14526692
申请日：2014-10-29
申请人： SAMSUNG DISPLAY CO., LTD.
发明人： Masayuki KUMETA , Ryo ISHII , Kazuhiro MATSUMOTO , Shinji YAMASHITA , Ansu LEE
IPC分类号： G09G5/39
CPC分类号： G09G5/39 , G09G3/20 , G09G5/005 , G09G2310/0224 , G09G2310/0235 , G09G2310/08 , G09G2360/12 , G09G2360/18
摘要： A control circuit for a frame memory includes a divider, a frame memory, a read control circuit, and a write control circuit. The divider divides image data into subfield data according to a plurality of subfields, where the image data is provided in synchronization with a first synchronization signal and in a unit of a frame. The frame memory has a plurality of blocks to store the subfield data. The read control circuit sequentially reads the subfield data from the blocks in synchronization with a second synchronization signal. The write control circuit writes new data to a first block before data written in a second block is read, and after data written in the first block is read by the read control circuit. The second synchronization signal may have a same cycle as the first synchronization signal and may be delayed by a preset delay time.
摘要翻译：用于帧存储器的控制电路包括分频器，帧存储器，读控制电路和写控制电路。分配器根据多个子场将图像数据分割成子场数据，其中图像数据与第一同步信号同步地以帧为单位提供。帧存储器具有存储子场数据的多个块。读取控制电路与第二同步信号同步地从块中顺序地读取子场数据。写入控制电路在读取写入第二块中的数据之前并且在读取控制电路读取写入第一块的数据之后，将新数据写入第一块。第二同步信号可以具有与第一同步信号相同的周期，并且可以延迟预设的延迟时间。

78. 发明授权

US08937624B2 Method and apparatus for translating memory access address 有权
标题翻译：用于翻译存储器访问地址的方法和装置
公开(公告)号：US08937624B2
公开(公告)日：2015-01-20
申请号：US13297492
申请日：2011-11-16
申请人： Gi Ho Park , Won Chang Lee , Shi Hwa Lee , Do Hyung Kim , Joon Ho Song , Sung Uk Jeong
发明人： Gi Ho Park , Won Chang Lee , Shi Hwa Lee , Do Hyung Kim , Joon Ho Song , Sung Uk Jeong
IPC分类号： G06F12/06 , G06F12/00 , G09G5/37 , G09G5/399 , G06F13/28 , G09G5/39 , G11C8/00 , G06F12/02
CPC分类号： G06F12/0607 , G06F12/0207 , G06F2212/1024
摘要： A memory access address translating apparatus and method may each classify pixels included in an input image into a plurality of tiles, and may generate a new memory for each of the successive tiles to enable the successive tiles, among a plurality of tiles, to be stored in different banks.
摘要翻译：存储器访问地址转换装置和方法可以将输入图像中包括的像素分类为多个瓦片，并且可以为每个连续瓦片生成新的存储器，以使多个瓦片中的连续瓦片能够被存储在不同的银行。

79. 发明授权

US08922573B1 Video non-buffered line memory 有权
标题翻译：视频非缓冲线路存储器
公开(公告)号：US08922573B1
公开(公告)日：2014-12-30
申请号：US12502927
申请日：2009-07-14
申请人： Saif Choudhary
发明人： Saif Choudhary
IPC分类号： G09G5/36 , G09G5/39 , G06F12/02
CPC分类号： G09G5/399 , G06T1/60 , G09G2320/106 , G09G2340/02 , G09G2360/122
摘要： A non-buffered video line memory eliminates the need for double buffering video data during processing. While most double buffering systems double the amount of memory necessary to store video data, a non-buffered approach reduces the hardware memory costs substantially. A set of write and read pointers coupled with write and read incrementors allows data to be stored in raster order and removed in block order from a non-buffered memory device. The incrementors, in conjunction with a set of write and read pointers generate a base address for data to be written to and read from the non-buffered memory at substantially the same time. Encoding systems benefit substantially by being able to read and write information into a common memory rather than continuously switching between two different memories, by reducing complexity and cost.
摘要翻译：非缓冲视频行存储器消除了在处理期间双缓冲视频数据的需要。虽然大多数双缓冲系统将存储视频数据所需的内存量增加一倍，但非缓冲方法大大降低了硬件内存成本。与写入和读取增量器耦合的一组写入和读取指针允许以光栅顺序存储数据，并以块顺序从非缓冲存储器件中移除数据。增量器与一组写入和读取指针结合在一起基本上同时生成要从非缓冲存储器写入和读取的数据的基址。编码系统通过能够通过降低复杂性和成本而将信息读取和写入公共存储器而不是不断地在两个不同存储器之间切换而受益匪浅。

80. 发明授权

US08878834B2 Image display device with mobile communication device detection and identification 有权
标题翻译：具有移动通信设备检测识别的图像显示设备
公开(公告)号：US08878834B2
公开(公告)日：2014-11-04
申请号：US13000412
申请日：2010-04-16
申请人： Tomoko Matsumoto
发明人： Tomoko Matsumoto
IPC分类号： G09G5/39 , G06T17/00 , H04N5/775 , G06F3/147 , H04N21/45 , H04N21/81 , H04N21/41 , H04N7/16 , H04N1/32 , H04N21/442 , H04N1/00 , H04N21/414 , H04N21/4363
CPC分类号： H04N21/8153 , G06F3/147 , G09G2370/04 , G09G2370/042 , G09G2370/16 , G09G2380/16 , H04N1/00307 , H04N1/00912 , H04N1/32128 , H04N5/775 , H04N7/163 , H04N21/4122 , H04N21/41407 , H04N21/43637 , H04N21/44227 , H04N21/4532 , H04N2201/0036 , H04N2201/0055 , H04N2201/0089 , H04N2201/3205 , H04N2201/3214 , H04N2201/3226 , H04N2201/3252 , H04N2201/3253 , H04N2201/3277
摘要： The digital photo frame (1) of the present invention includes: an image data storage section (21) which stores image data associated with identification information of a mobile communication device; a device identifying section (11) which detects the mobile communication device and identifies the identification information of the mobile communication device; and an image display control section (14) which controls, when the mobile communication device is detected, a display section to display image data which is associated with the identification information identified by the device identifying section (11) among image data stored in the image data storage section (21), by carrying out a display control which is different from that for other data. This configuration makes it possible to change a way to display plural pieces of data in accordance with whether or not a detectable mobile communication device is in the device detectable area.
摘要翻译：本发明的数字相框（1）包括：图像数据存储部（21），其存储与移动通信装置的识别信息相关联的图像数据; 设备识别部分，其检测移动通信设备并识别移动通信设备的识别信息; 以及图像显示控制部（14），其在检测到所述移动通信装置时，控制显示部，显示与所述图像中存储的图像数据中的与所述装置识别部（11）识别的识别信息相关联的图像数据数据存储部分（21），通过执行与其他数据不同的显示控制。该配置使得可以根据可检测的移动通信设备是否在设备可检测区域中来改变显示多条数据的方式。

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