专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09836811B2 Memory control device, mobile terminal, and computer-readable recording medium for controlling writing and reading of data to frame memory 有权
公开(公告)号：US09836811B2
公开(公告)日：2017-12-05
申请号：US14423458
申请日：2013-08-28
申请人： Sharp Kabushiki Kaisha
发明人： Junki Asai , Kenji Maeda
IPC分类号： G06T1/60 , G09G3/36
CPC分类号： G06T1/60 , G09G3/20 , G09G3/36 , G09G3/3611 , G09G5/393 , G09G2320/0247 , G09G2340/14 , G09G2350/00 , G09G2360/12 , G09G2360/125 , G09G2360/18
摘要： A memory control device of the present invention comprises a reset control section (32) for (i) suspending, at a time point where rp overtakes wp or wp overtakes rp or a time point immediately before that time point, a reading operation of data, and (ii) conducting again, at a predetermined time point where reading is to be resumed, the reading operation of the data from a position at which the reading operation has been started in a frame memory (31).

2. 发明授权

US09472169B2 Coordinate based QoS escalation 有权
标题翻译：基于协调的QoS升级
公开(公告)号：US09472169B2
公开(公告)日：2016-10-18
申请号：US14258662
申请日：2014-04-22
申请人： Apple Inc.
发明人： Hao Chen , Benjamin K. Dodge , Peter F. Holland
IPC分类号： G06T1/20 , G09G5/397 , G09G5/00 , G09G5/14
CPC分类号： G09G5/397 , G09G5/001 , G09G5/14 , G09G2340/0407 , G09G2340/10 , G09G2350/00 , G09G2352/00 , G09G2360/125
摘要： Systems and methods for determining priorities of pixel fetch requests of separate requestors in a display control unit. The distance between the oldest pixel in an output buffer and the output equivalent coordinate of the oldest outstanding source pixel read request for each requestor in the display control unit is calculated. Then, a priority is assigned to each requestor based on this calculated distance. If a given requestor lags behind the other requestors based on a comparison of the distance between the oldest pixel and the output equivalent coordinate of the oldest outstanding source pixel read, then source pixel fetch requests for this given requestor are given a higher priority than source pixel fetch requests for the other requestors.
摘要翻译：用于确定显示控制单元中单独请求者的像素提取请求的优先级的系统和方法。计算输出缓冲器中的最旧像素与显示控制单元中每个请求者的最早未完成源像素读取请求的输出等效坐标之间的距离。然后，基于该计算出的距离将优先级分配给每个请求者。如果给定的请求者基于最旧的像素读取的最旧的源像素的输出等效坐标之间的距离的比较而落在其他请求者之后，则给予该给定请求者的源像素提取请求被给予比源像素更高的优先级提取其他请求者的请求。

3. 发明授权

US09239699B2 Enabling hardware acceleration in a computing device during a mosaic display mode of operation thereof 有权
标题翻译：在马赛克显示操作模式期间，在计算设备中启用硬件加速
公开(公告)号：US09239699B2
公开(公告)日：2016-01-19
申请号：US14102326
申请日：2013-12-10
申请人： NVIDIA Corporation
发明人： Praful Jotshi , Arpit Agrawal
IPC分类号： G09G5/00 , G06F15/16 , G06F3/14 , G06T1/60 , G06T1/20
CPC分类号： G06F3/1446 , G06F3/1438 , G06T1/20 , G06T1/60 , G09G2300/026 , G09G2360/06 , G09G2360/125
摘要： A method includes providing a memory unit in a computing device already including a number of processors communicatively coupled to a memory through a system bus, and providing a non-system bus based dedicated channel between the number of processors and the memory unit. The method also includes rendering a different video frame and/or a surface on each processor of the number of processors, and leveraging the memory unit to store a video frame and/or a surface rendered on a processor therein through the non-system bus based dedicated channel. Further, the method includes copying, to other processors, the stored video frame and/or the surface rendered on the processor from the memory unit through the non-system bus based dedicated channel, and scanning out, through the number of processors, the video frame and/or the surface rendered on the processor following the copying to enable display thereof on a corresponding number of displays.
摘要翻译：一种方法包括在已经包括通过系统总线通信地耦合到存储器的多个处理器的计算设备中提供存储器单元，以及在处理器数量和存储器单元之间提供基于非系统总线的专用信道。该方法还包括在处理器数量的每个处理器上呈现不同的视频帧和/或表面，并且利用存储器单元通过非系统总线来存储在其中的处理器上呈现的视频帧和/或表面专用频道此外，该方法包括通过基于非系统总线的专用信道从存储器单元将存储的视频帧和/或在处理器上呈现的表面复制到其他处理器，并且通过处理器的数量扫描视频框架和/或在复制之后在处理器上呈现的表面，以使其能够在相应数量的显示器上显示。

4. 发明授权

US09111369B2 Graphics accelerator 有权
标题翻译：图形加速器
公开(公告)号：US09111369B2
公开(公告)日：2015-08-18
申请号：US13782081
申请日：2013-03-01
申请人： Broadcom Corporation
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiadong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G06T1/60 , G06T1/20 , G06T9/00 , G09G5/00 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/34 , G09G5/36 , H04N5/04 , H04N5/14 , H04N5/445 , H04N5/45 , H04N7/01 , H04N9/45 , H04N9/64 , H04N21/422 , H04N21/426 , H04N21/43 , H04N21/431 , H04N21/434 , H04N21/4402 , H04N21/443 , H04N21/47 , H04N19/61 , H04N19/44 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/59 , G09G5/02 , H04N5/12 , H04N5/44 , H04N5/46 , H04N11/14 , H04N11/20
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： Disclosed herein are various embodiments of a graphics accelerator, which may include an integrated circuit. The integrated circuit may include a local memory; a direct memory access (DMA) engine; a processor; and one or more processing pipelines. The local memory stores graphics data that includes a plurality of pixels. The DMA engine transfers the graphics data between the local memory and an external memory. The processor performs at least one operation, in parallel, on components of at least a portion of the pixels. The one or more processing pipelines process the graphics data. The graphics accelerator works on operands and produces outputs for one set of pixels while the DMA engine is bringing in operands for a future set of pixel operations, and transfers data from the external memory to the one or more processing pipelines by directing data to the one or more pipelines.
摘要翻译：这里公开了图形加速器的各种实施例，其可以包括集成电路。集成电路可以包括本地存储器; 直接存储器访问（DMA）引擎; 处理器和一个或多个处理管道。本地存储器存储包括多个像素的图形数据。 DMA引擎在本地存储器和外部存储器之间传输图形数据。处理器并行地执行至少一部分像素的组件上的至少一个操作。一个或多个处理管线处理图形数据。图形加速器对操作数起作用，并产生一组像素的输出，而DMA引擎为未来的像素运算组提供操作数，并通过将数据指向一个或多个处理流水线将数据从外部存储器传输到一个或多个处理流水线或更多管道。

5. 发明授权

US09077997B2 Graphics display system with unified memory architecture 有权
公开(公告)号：US09077997B2
公开(公告)日：2015-07-07
申请号：US10763087
申请日：2004-01-22
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G06F3/00 , H04N19/436 , G06T9/00 , G09G5/00 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/34 , G09G5/36 , H04N5/04 , H04N5/14 , H04N5/445 , H04N5/45 , H04N7/01 , H04N9/45 , H04N9/64 , H04N21/422 , H04N21/43 , H04N21/426 , H04N21/431 , H04N21/434 , H04N21/4402 , H04N21/443 , H04N21/47 , H04N19/61 , H04N19/44 , H04N19/42 , H04N19/423 , H04N19/59 , G09G5/02 , H04N5/12 , H04N5/44 , H04N5/46 , H04N11/14 , H04N11/20
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

6. 发明申请

US20150154735A1 MEMORY DEVICE FOR PROVIDING DATA IN A GRAPHICS SYSTEM AND METHOD AND APPARATUS THEREOF 有权
标题翻译：用于在图形系统中提供数据的存储器件及其方法和装置
公开(公告)号：US20150154735A1
公开(公告)日：2015-06-04
申请号：US14556801
申请日：2014-12-01
申请人： ATI Technologies ULC
发明人： Milivoje Aleksic , Raymond M. Li , Danny H.M. Cheng , Carl K. Mizuyabu , Antonio Asaro
IPC分类号： G06T1/60 , G06F13/28 , G06T1/20 , G06F13/16
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.
摘要翻译：中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。由系统/图形控制器访问的统一的系统/图形存储器。统一存储器包含系统数据和图形数据。在具体实施例中，两个通道CH0和CH1访问统一存储器。每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。

7. 发明申请

US20150138237A1 SYSTEMS AND METHODS FOR COMPOSITING A DISPLAY IMAGE FROM DISPLAY PLANES USING ENHANCED BLENDING HARDWARE 有权
标题翻译：使用增强混合硬件从显示平面组合显示图像的系统和方法
公开(公告)号：US20150138237A1
公开(公告)日：2015-05-21
申请号：US14255709
申请日：2014-04-17
申请人： nComputing Inc.
发明人： Subir Ghosh , Anita Chowdhry
IPC分类号： G06T11/60
CPC分类号： G09G5/393 , G06F3/1438 , G06F3/1454 , G09G5/02 , G09G5/022 , G09G5/36 , G09G5/397 , G09G2340/02 , G09G2340/10 , G09G2340/125 , G09G2350/00 , G09G2360/10 , G09G2360/125 , G09G2360/127 , G09G2370/022 , G09G2370/20
摘要： An internal matrix corresponding to a representation of a display screen and having transparency data of a macro block is accessed. Display plane data from either a first or second plane is read if the internal matrix indicates the macro block is non-translucent and from both planes when the internal matrix indicates translucency. A high-level external matrix having high-level external transparency data indicating transparency of pixels is accessed if the internal transparency data indicates the macro block includes a window boundary. Display plane data from either the first or second plane is read if the high-level external transparency data indicates a non-translucent pixel and from both planes when the internal matrix indicates translucency. A detailed external matrix is accessed if the internal transparency data indicates the macro block is translucent or if the high-level external transparency data indicates the pixel is translucent. The first and second planes are blended accordingly.
摘要翻译：访问对应于显示屏幕的表示并具有宏块的透明度数据的内部矩阵。如果内部矩阵表示宏块是非半透明的，并且当内部矩阵表示半透明度时，则从第一或第二平面显示平面数据。如果内部透明度数据指示宏块包括窗口边界，则访问具有指示像素的透明度的高级外部透明度数据的高级外部矩阵。如果高级外部透明度数据表示非半透明像素，并且当内部矩阵表示半透明度时，则从第一或第二平面显示平面数据。如果内部透明度数据指示宏块是半透明的，或者高级外部透明度数据指示像素是半透明的，则会访问详细的外部矩阵。相应地混合第一和第二平面。

8. 发明申请

US20150002526A1 Shared Virtual Memory Between A Host And Discrete Graphics Device In A Computing System 审中-公开
标题翻译：计算系统中主机与离散图形设备之间的共享虚拟内存
公开(公告)号：US20150002526A1
公开(公告)日：2015-01-01
申请号：US14489023
申请日：2014-09-17
申请人： Intel Corporation
发明人： Boris Ginzburg
IPC分类号： G06T1/60 , G06F12/08 , G06F12/10
CPC分类号： G06T1/60 , G06F3/14 , G06F12/0802 , G06F12/1009 , G06F12/1027 , G06F12/1036 , G06F12/1045 , G06F12/1063 , G06F12/1081 , G06F12/109 , G06F12/12 , G06F2212/302 , G06F2212/455 , G06F2212/656 , G06T2200/28 , G09G5/363 , G09G5/39 , G09G2360/121 , G09G2360/125
摘要： In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有设备处理器和设备存储器的设备。该设备可以连接到具有主机处理器和主机内存的主机。两个存储器都可以具有页表以将虚拟地址映射到相应存储器的物理地址，并且两个存储器可以以用户级应用程序显示为单个虚拟存储器空间。描述和要求保护其他实施例。

9. 发明申请

US20140156942A1 Shared Virtual Memory Between A Host And Discrete Graphics Device In A Computing System 有权
标题翻译：计算系统中主机与离散图形设备之间的共享虚拟内存
公开(公告)号：US20140156942A1
公开(公告)日：2014-06-05
申请号：US14172493
申请日：2014-02-04
申请人： Boris Ginzburg
发明人： Boris Ginzburg
IPC分类号： G06F12/10 , G06F12/12
CPC分类号： G06T1/60 , G06F3/14 , G06F12/0802 , G06F12/1009 , G06F12/1027 , G06F12/1036 , G06F12/1045 , G06F12/1063 , G06F12/1081 , G06F12/109 , G06F12/12 , G06F2212/302 , G06F2212/455 , G06F2212/656 , G06T2200/28 , G09G5/363 , G09G5/39 , G09G2360/121 , G09G2360/125
摘要： In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有设备处理器和设备存储器的设备。该设备可以连接到具有主机处理器和主机内存的主机。两个存储器都可以具有页表以将虚拟地址映射到相应存储器的物理地址，并且两个存储器可以以用户级应用程序显示为单个虚拟存储器空间。描述和要求保护其他实施例。

10. 发明授权

US08711164B2 Memory controller including a hardware compression and decompression engine for managing system memory and graphical operations 失效
标题翻译：内存控制器包括用于管理系统内存和图形操作的硬件压缩和解压缩引擎
公开(公告)号：US08711164B2
公开(公告)日：2014-04-29
申请号：US13465838
申请日：2012-05-07
申请人： Thomas A. Dye
发明人： Thomas A. Dye
IPC分类号： G06F12/00 , G06T9/00
CPC分类号： G06F12/08 , G06F2212/401 , G09G5/02 , G09G5/14 , G09G5/363 , G09G5/39 , G09G2340/02 , G09G2340/0407 , G09G2340/125 , G09G2360/121 , G09G2360/125
摘要： An integrated memory controller (IMC) may sit on the main CPU bus or a high speed system peripheral bus and couple to system memory. The IMC may use a lossless data compression and decompression scheme for improved performance. The IMC may also include microcode for specific decompression of particular data formats such as digital video and digital audio. Compressed data may be decompressed in the IMC and stored into system memory or saved in the system memory in compressed format. Internal memory mapping may allow for format definition spaces which may define the format of the data and the data type to be read or written. Software overrides may be placed in applications software in systems that desire to control data decompression at the software application level.
摘要翻译：集成存储器控制器（IMC）可以位于主CPU总线或高速系统外设总线上并耦合到系统存储器。 IMC可以使用无损数据压缩和解压缩方案来提高性能。 IMC还可以包括用于特定解压缩特定数据格式（例如数字视频和数字音频）的微码。压缩数据可以在IMC中解压缩并存储到系统存储器中或以压缩格式保存在系统存储器中。内部存储器映射可以允许格式定义空间，其可以定义要读取或写入的数据的格式和数据类型。软件覆盖可以放置在希望在软件应用级别控制数据解压缩的系统中的应用软件中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式