专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US4420871A Method of producing a monolithically integrated two-transistor memory cell in accordance with MOS technology 失效
标题翻译：根据MOS技术制造单片集成双晶体管存储单元的方法
公开(公告)号：US4420871A
公开(公告)日：1983-12-20
申请号：US307884
申请日：1981-10-02
申请人： Adolf Scheibe
发明人： Adolf Scheibe
IPC分类号： H01L27/112 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L27/088 , H01L27/115 , H01L27/11517 , H01L29/788 , H01L29/792 , H01L21/76 , H01L21/88 , H01L21/95
CPC分类号： H01L29/66825 , H01L27/088 , H01L27/115 , H01L27/11517
摘要： A method of producing a monolithically integrated two-transistor memory cell, including a silicon crystal for accommodating the memory cell, a first MOS field effect transistor having a current-carrying channel and both a control gate and a floating gate disposed between the control gate and surface of the crystal, a second MOS field effect transistor having a current-carrying channel and a control gate, an SiO.sub.2 film supporting the gates, a doped polycrystalline silicon layer deposited on the SiO.sub.2 film, the control gates and the floating gate being formed from the doped polycrystalline silicon layer, and an erase area for the floating gate, the improvement which includes covering a part of the silicon crystal intended for the memory cell with an SiO.sub.2 film, forming a part of the gate oxide of the first MOS field effect transistor, forming a window through the SiO.sub.2 film at a location intended for the erase area, re-oxidizing the exposed area of the surface of the crystal in the window and increasing the remaining areas of the SiO.sub.2 film, depositing a first doped polycrystalline silicon layer forming a base of the floating gate, covering the polycrystalline silicon layer with another SiO.sub.2 film, depositing a second doped polycrystalline silicon layer, and forming the control gate of the first MOS field effect transistor from the second doped polycrystalline silicon layer and producing the source and drain zone of the two MOS field effect transistors.
摘要翻译：一种制造单片集成的双晶体管存储单元的方法，包括用于容纳存储单元的硅晶体，具有载流通道的第一MOS场效应晶体管，以及设置在控制栅极与控制栅极之间的浮栅晶体表面，具有载流通道和控制栅极的第二MOS场效应晶体管，支撑栅极的SiO 2膜，沉积在SiO 2膜上的掺杂多晶硅层，控制栅极和浮置栅极由掺杂多晶硅层和用于浮置栅极的擦除区域，其改进包括用SiO 2膜覆盖用于存储单元的硅晶体的一部分，形成第一MOS场效应晶体管的栅极氧化物的一部分在旨在用于擦除区域的位置处形成通过SiO 2膜的窗口，再次氧化窗口中晶体表面的暴露区域 d增加SiO 2膜的剩余面积，沉积形成浮栅的基极的第一掺杂多晶硅层，用另一SiO 2膜覆盖多晶硅层，沉积第二掺杂多晶硅层，以及形成第二掺杂多晶硅层的控制栅极第一MOS场效应晶体管和第二掺杂多晶硅层，并产生两个MOS场效应晶体管的源极和漏极区。

72. 发明授权

US11600663B2 Memory cell and memory array select transistor 有权
公开(公告)号：US11600663B2
公开(公告)日：2023-03-07
申请号：US16740652
申请日：2020-01-13
申请人： Zeno Semiconductor, Inc.
发明人： Jin-Woo Han , Yuniarto Widjaja
IPC分类号： H01L27/24 , H01L27/11517 , H01L27/22
摘要： A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) with increased on-state current obtained through a parasitic bipolar junction transistor (BJT) of the MOSFET. Methods of operating the MOSFET as a memory cell or a memory array select transistor are provided.

73. 发明申请

US20230064914A1 TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME 有权
公开(公告)号：US20230064914A1
公开(公告)日：2023-03-02
申请号：US17446556
申请日：2021-08-31
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yu-Chu LIN , Wen-Chih CHIANG , Chi-Chung JEN , Ming-Hong SU , Mei-Chen SU , Chia-Wei LEE , Kuan-Wei SU , Chia-Ming PAN
IPC分类号： H01L29/788 , H01L29/423 , H01L27/11517 , H01L29/06
摘要： Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.

74. 发明授权

US11443971B2 3D semiconductor device and structure with memory 有权
公开(公告)号：US11443971B2
公开(公告)日：2022-09-13
申请号：US17146416
申请日：2021-01-11
申请人： Monolithic 3D Inc.
发明人： Zvi Or-Bach , Brian Cronquist , Deepak C. Sekar
IPC分类号： H01L21/8239 , H01L21/8242 , H01L21/8244 , H01L21/8246 , H01L27/108 , H01L27/11 , H01L27/112 , H01L27/115 , H01L27/11514 , H01L27/11517 , H01L21/683 , H01L21/74 , H01L21/762 , H01L21/768 , H01L21/822 , H01L21/8238 , H01L21/84 , H01L23/48 , H01L23/525 , H01L27/02 , H01L27/06 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/11573 , H01L27/11578 , H01L27/118 , H01L27/12 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/788 , H01L29/792 , G11C8/16 , H01L23/367 , H01L25/065 , H01L25/00 , H01L23/00
摘要： A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors and a first metal layer, where the first transistors include forming memory control circuits; a second level including a plurality of second transistors; a third level including a plurality of third transistors, where the second level is above the first level, and where the third level is above the second level; a second metal layer above the third level; and a third metal layer above the second metal layer, where the second transistors are aligned to the first transistors with less than 140 nm alignment error, where the second level includes a plurality of first memory cells, where the third level includes a plurality of second memory cells, and where the memory control circuits are designed to adjust a memory write voltage according to the device specific process parameters.

75. 发明授权

US11368157B2 Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells 有权
公开(公告)号：US11368157B2
公开(公告)日：2022-06-21
申请号：US17008605
申请日：2020-08-31
申请人： iCometrue Company Ltd.
发明人： Jin-Yuan Lee , Mou-Shiung Lin
IPC分类号： H03K19/1776 , H03K19/173 , H01L23/00 , H01L23/538 , H01L25/18 , H01L27/11517 , H01L27/24 , H03K19/17728 , H03K19/21 , H03K19/20
摘要： A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

76. 发明授权

US11362218B2 Method of forming split gate memory cells with thinned side edge tunnel oxide 有权
公开(公告)号：US11362218B2
公开(公告)日：2022-06-14
申请号：US16910022
申请日：2020-06-23
申请人： Silicon Storage Technology, Inc.
发明人： Jinho Kim , Elizabeth Cuevas , Yuri Tkachev , Parviz Ghazavi , Bernard Bertello , Gilles Festes , Bruno Villard , Catherine Decobert , Nhan Do , Jean Francois Thiery
IPC分类号： H01L27/11517 , H01L27/11531 , H01L29/788 , H01L29/66 , H01L27/11543 , H01L27/11551 , H01L27/11524 , H01L27/11521 , H01L27/11529 , H01L27/11534
摘要： A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.

77. 发明授权

US11362100B2 FinFET split gate non-volatile memory cells with enhanced floating gate to floating gate capacitive coupling 有权
公开(公告)号：US11362100B2
公开(公告)日：2022-06-14
申请号：US17069563
申请日：2020-10-13
申请人： Silicon Storage Technology, Inc.
发明人： Feng Zhou , Xian Liu , Steven Lemke , Hieu Van Tran , Nhan Do
IPC分类号： H01L27/11517 , H01L27/11529 , H01L29/788 , H01L29/423 , H01L29/66 , H01L27/11551
摘要： Memory cells formed on upwardly extending fins of a semiconductor substrate, each including source and drain regions with a channel region therebetween, a floating gate extending along the channel region and wrapping around the fin, a word line gate extending along the channel region and wrapping around the fin, a control gate over the floating gate, and an erase gate over the source region. The control gates are a continuous conductive strip of material. First and second fins are spaced apart by a first distance. Third and fourth fins are spaced apart by a second distance. The second and third fins are spaced apart by a third distance greater than the first and second distances. The continuous strip includes a portion disposed between the second and third fins, but no portion of the continuous strip is disposed between the first and second fins nor between the third and fourth fins.

78. 发明申请

US20220059531A1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20220059531A1
公开(公告)日：2022-02-24
申请号：US17520977
申请日：2021-11-08
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei YAMAZAKI , Jun KOYAMA , Kiyoshi KATO
IPC分类号： H01L27/088 , G11C11/405 , G11C11/404 , G11C16/02 , H01L27/02 , H01L27/115 , H01L27/11517 , H01L27/1156 , H01L27/12 , H01L27/105
摘要： It is an object to provide a semiconductor having a novel structure. In the semiconductor device, a plurality of memory elements are connected in series and each of the plurality of memory elements includes first to third transistors thus forming a memory circuit. A source or a drain of a first transistor which includes an oxide semiconductor layer is in electrical contact with a gate of one of a second and a third transistor. The extremely low off current of a first transistor containing the oxide semiconductor layer allows storing, for long periods of time, electrical charges in the gate electrode of one of the second and the third transistor, whereby a substantially permanent memory effect can be obtained. The second and the third transistors which do not contain an oxide semiconductor layer allow high-speed operations when using the memory circuit.

79. 发明申请

US20210399127A1 Method Of Forming Split Gate Memory Cells With Thinned Side Edge Tunnel Oxide 有权
公开(公告)号：US20210399127A1
公开(公告)日：2021-12-23
申请号：US16910022
申请日：2020-06-23
申请人： Silicon Storage Technology, Inc.
发明人： Jinho Kim , Elizabeth Cuevas , Yuri Tkachev , Parviz Ghazavi , Bernard Bertello , Gilles Festes , Bruno Villard , Catherine Decobert , Nhan Do , Jean Francois Thiery
IPC分类号： H01L29/788 , H01L29/66 , H01L27/11517
摘要： A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.

80. 发明授权

US11164946B2 Manufacturing method for flash device 有权
公开(公告)号：US11164946B2
公开(公告)日：2021-11-02
申请号：US16461721
申请日：2017-12-14
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Tao Liu , Zhibin Liang , Song Zhang , Yan Jin , Dejin Wang
IPC分类号： H01L29/423 , H01L21/28 , H01L29/66 , H01L27/11517 , H01L29/788
摘要： A manufacturing method for a flash device. A manufacturing method for a flash device, comprising: providing a substrate; forming sequentially, on the substrate, a floating gate (FG) oxide layer, an FG polycrystalline layer, and an FG mask layer; etching, at the FG location region, the FG polycrystalline layer and the FG mask layer, forming a window on the FG mask layer, and forming a trench on the FG polycrystalline layer, the window being communicated with the trench; performing second etching of the side wall of the window of the FG mask layer, enabling the width of the trench located on the FG polycrystalline layer to be less than the width of the secondarily-etched window located on the FG mask layer; and oxidizing the FG polycrystalline layer, enabling the oxide to fill the trench to form a field oxide layer; and etching an FG having sharp angles.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式